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Poonam Aggrwal18bacc22009-07-31 12:07:45 +05301/*
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +00002 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Poonam Aggrwal18bacc22009-07-31 12:07:45 +05303 *
Stefan Roesea47a12b2010-04-15 16:07:28 +02004 * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and
5 * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains
Peter Tyser8d1f2682010-04-12 22:28:09 -05006 * cpu specific common code for 85xx/86xx processors.
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Poonam Aggrwal18bacc22009-07-31 12:07:45 +05308 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
13#include <tsec.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050014#include <fm_eth.h>
Poonam Aggrwal18bacc22009-07-31 12:07:45 +053015#include <netdev.h>
16#include <asm/cache.h>
17#include <asm/io.h>
Codrin Ciubotariu7e40e4b2015-01-21 11:54:10 +020018#include <vsc9953.h>
Poonam Aggrwal18bacc22009-07-31 12:07:45 +053019
20DECLARE_GLOBAL_DATA_PTR;
21
Kim Phillips2ed2e912012-10-29 13:34:37 +000022static struct cpu_type cpu_type_list[] = {
Poonam Aggrwal18bacc22009-07-31 12:07:45 +053023#if defined(CONFIG_MPC85xx)
Poonam Aggrwal0e870982009-07-31 12:08:14 +053024 CPU_TYPE_ENTRY(8533, 8533, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053025 CPU_TYPE_ENTRY(8535, 8535, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053026 CPU_TYPE_ENTRY(8536, 8536, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053027 CPU_TYPE_ENTRY(8540, 8540, 1),
28 CPU_TYPE_ENTRY(8541, 8541, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053029 CPU_TYPE_ENTRY(8543, 8543, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053030 CPU_TYPE_ENTRY(8544, 8544, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053031 CPU_TYPE_ENTRY(8545, 8545, 1),
York Sun48f6a5c2012-07-06 17:10:33 -050032 CPU_TYPE_ENTRY(8547, 8547, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053033 CPU_TYPE_ENTRY(8548, 8548, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053034 CPU_TYPE_ENTRY(8555, 8555, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053035 CPU_TYPE_ENTRY(8560, 8560, 1),
36 CPU_TYPE_ENTRY(8567, 8567, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053037 CPU_TYPE_ENTRY(8568, 8568, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053038 CPU_TYPE_ENTRY(8569, 8569, 1),
Poonam Aggrwal0e870982009-07-31 12:08:14 +053039 CPU_TYPE_ENTRY(8572, 8572, 2),
Poonam Aggrwalb8cdd012011-01-13 21:39:27 +053040 CPU_TYPE_ENTRY(P1010, P1010, 1),
Poonam Aggrwala713ba92009-08-20 18:57:45 +053041 CPU_TYPE_ENTRY(P1011, P1011, 1),
Kumar Gala21608272010-03-30 23:06:53 -050042 CPU_TYPE_ENTRY(P1012, P1012, 1),
Kumar Gala21608272010-03-30 23:06:53 -050043 CPU_TYPE_ENTRY(P1013, P1013, 1),
Poonam Aggrwalb5debec2011-01-13 21:40:05 +053044 CPU_TYPE_ENTRY(P1014, P1014, 1),
Roy Zang67a719d2011-02-03 22:14:19 -060045 CPU_TYPE_ENTRY(P1017, P1017, 1),
Poonam Aggrwal87c76612009-07-31 12:08:27 +053046 CPU_TYPE_ENTRY(P1020, P1020, 2),
Kumar Gala21608272010-03-30 23:06:53 -050047 CPU_TYPE_ENTRY(P1021, P1021, 2),
Kumar Gala21608272010-03-30 23:06:53 -050048 CPU_TYPE_ENTRY(P1022, P1022, 2),
Roy Zang67a719d2011-02-03 22:14:19 -060049 CPU_TYPE_ENTRY(P1023, P1023, 2),
Kumar Gala093cffb2011-02-05 13:45:07 -060050 CPU_TYPE_ENTRY(P1024, P1024, 2),
Kumar Gala093cffb2011-02-05 13:45:07 -060051 CPU_TYPE_ENTRY(P1025, P1025, 2),
Poonam Aggrwala713ba92009-08-20 18:57:45 +053052 CPU_TYPE_ENTRY(P2010, P2010, 1),
Poonam Aggrwala713ba92009-08-20 18:57:45 +053053 CPU_TYPE_ENTRY(P2020, P2020, 2),
Kumar Galaf193e3d2010-06-01 10:29:11 -050054 CPU_TYPE_ENTRY(P2040, P2040, 4),
Kumar Gala1f979872011-05-13 01:16:07 -050055 CPU_TYPE_ENTRY(P2041, P2041, 4),
Kumar Galac26de2d2010-01-27 10:26:46 -060056 CPU_TYPE_ENTRY(P3041, P3041, 4),
Kumar Gala7e4259b2009-03-19 02:39:17 -050057 CPU_TYPE_ENTRY(P4040, P4040, 4),
Kumar Gala7e4259b2009-03-19 02:39:17 -050058 CPU_TYPE_ENTRY(P4080, P4080, 8),
Kumar Gala19dbcc92009-10-21 13:32:58 -050059 CPU_TYPE_ENTRY(P5010, P5010, 1),
Kumar Gala19dbcc92009-10-21 13:32:58 -050060 CPU_TYPE_ENTRY(P5020, P5020, 2),
Timur Tabi49054432012-10-05 11:09:19 +000061 CPU_TYPE_ENTRY(P5021, P5021, 2),
62 CPU_TYPE_ENTRY(P5040, P5040, 4),
York Sun9e758752012-10-08 07:44:19 +000063 CPU_TYPE_ENTRY(T4240, T4240, 0),
64 CPU_TYPE_ENTRY(T4120, T4120, 0),
York Sunb6240842013-03-25 07:33:29 +000065 CPU_TYPE_ENTRY(T4160, T4160, 0),
Shengzhou Liu5122dfa2014-04-25 16:31:22 +080066 CPU_TYPE_ENTRY(T4080, T4080, 4),
York Sund2404142012-10-08 07:44:20 +000067 CPU_TYPE_ENTRY(B4860, B4860, 0),
68 CPU_TYPE_ENTRY(G4860, G4860, 0),
York Sund2404142012-10-08 07:44:20 +000069 CPU_TYPE_ENTRY(B4440, B4440, 0),
Shaveta Leekha9c3fdd82014-05-07 14:43:23 +053070 CPU_TYPE_ENTRY(B4460, B4460, 0),
York Sund2404142012-10-08 07:44:20 +000071 CPU_TYPE_ENTRY(G4440, G4440, 0),
72 CPU_TYPE_ENTRY(B4420, B4420, 0),
73 CPU_TYPE_ENTRY(B4220, B4220, 0),
York Sun5f208d12013-03-25 07:40:06 +000074 CPU_TYPE_ENTRY(T1040, T1040, 0),
75 CPU_TYPE_ENTRY(T1041, T1041, 0),
76 CPU_TYPE_ENTRY(T1042, T1042, 0),
77 CPU_TYPE_ENTRY(T1020, T1020, 0),
78 CPU_TYPE_ENTRY(T1021, T1021, 0),
79 CPU_TYPE_ENTRY(T1022, T1022, 0),
Shengzhou Liuf6050792014-11-24 17:11:54 +080080 CPU_TYPE_ENTRY(T1024, T1024, 0),
81 CPU_TYPE_ENTRY(T1023, T1023, 0),
82 CPU_TYPE_ENTRY(T1014, T1014, 0),
83 CPU_TYPE_ENTRY(T1013, T1013, 0),
Shengzhou Liu629d6b32013-11-22 17:39:10 +080084 CPU_TYPE_ENTRY(T2080, T2080, 0),
85 CPU_TYPE_ENTRY(T2081, T2081, 0),
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +000086 CPU_TYPE_ENTRY(BSC9130, 9130, 1),
Prabhakar Kushwaha19a8dbd2012-04-24 20:16:49 +000087 CPU_TYPE_ENTRY(BSC9131, 9131, 1),
Prabhakar Kushwaha35fe9482013-01-23 17:59:57 +000088 CPU_TYPE_ENTRY(BSC9132, 9132, 2),
89 CPU_TYPE_ENTRY(BSC9232, 9232, 2),
Mingkai Hu3b75e982013-07-04 17:30:36 +080090 CPU_TYPE_ENTRY(C291, C291, 1),
91 CPU_TYPE_ENTRY(C292, C292, 1),
92 CPU_TYPE_ENTRY(C293, C293, 1),
Poonam Aggrwal18bacc22009-07-31 12:07:45 +053093#elif defined(CONFIG_MPC86xx)
Poonam Aggrwal0e870982009-07-31 12:08:14 +053094 CPU_TYPE_ENTRY(8610, 8610, 1),
95 CPU_TYPE_ENTRY(8641, 8641, 2),
96 CPU_TYPE_ENTRY(8641D, 8641D, 2),
Poonam Aggrwal18bacc22009-07-31 12:07:45 +053097#endif
98};
99
York Sun123bd962012-08-17 08:20:22 +0000100#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
York Sunf6981432013-03-25 07:40:07 +0000101static inline u32 init_type(u32 cluster, int init_id)
102{
103 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
104 u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
105 u32 type = in_be32(&gur->tp_ityp[idx]);
106
107 if (type & TP_ITYP_AV)
108 return type;
109
110 return 0;
111}
112
York Sun123bd962012-08-17 08:20:22 +0000113u32 compute_ppc_cpumask(void)
114{
York Sunf6981432013-03-25 07:40:07 +0000115 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
York Sun123bd962012-08-17 08:20:22 +0000116 int i = 0, count = 0;
York Sunf6981432013-03-25 07:40:07 +0000117 u32 cluster, type, mask = 0;
York Sun123bd962012-08-17 08:20:22 +0000118
119 do {
120 int j;
York Sunf6981432013-03-25 07:40:07 +0000121 cluster = in_be32(&gur->tp_cluster[i].lower);
122 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
123 type = init_type(cluster, j);
124 if (type) {
York Sun123bd962012-08-17 08:20:22 +0000125 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
126 mask |= 1 << count;
York Sunf6981432013-03-25 07:40:07 +0000127 count++;
York Sun123bd962012-08-17 08:20:22 +0000128 }
York Sun123bd962012-08-17 08:20:22 +0000129 }
York Sunf6981432013-03-25 07:40:07 +0000130 i++;
York Sun123bd962012-08-17 08:20:22 +0000131 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
132
133 return mask;
134}
York Sunf6981432013-03-25 07:40:07 +0000135
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530136#ifdef CONFIG_HETROGENOUS_CLUSTERS
137u32 compute_dsp_cpumask(void)
138{
139 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
140 int i = CONFIG_DSP_CLUSTER_START, count = 0;
141 u32 cluster, type, dsp_mask = 0;
142
143 do {
144 int j;
145 cluster = in_be32(&gur->tp_cluster[i].lower);
146 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
147 type = init_type(cluster, j);
148 if (type) {
149 if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_SC)
150 dsp_mask |= 1 << count;
151 count++;
152 }
153 }
154 i++;
155 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
156
157 return dsp_mask;
158}
159
160int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
161{
162 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
163 int count = 0, i = CONFIG_DSP_CLUSTER_START;
164 u32 cluster;
165
166 do {
167 int j;
168 cluster = in_be32(&gur->tp_cluster[i].lower);
169 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
170 if (init_type(cluster, j)) {
171 if (count == core)
172 return i;
173 count++;
174 }
175 }
176 i++;
177 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
178
179 return -1; /* cannot identify the cluster */
180}
181#endif
182
York Sunf6981432013-03-25 07:40:07 +0000183int fsl_qoriq_core_to_cluster(unsigned int core)
184{
185 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
186 int i = 0, count = 0;
187 u32 cluster;
188
189 do {
190 int j;
191 cluster = in_be32(&gur->tp_cluster[i].lower);
192 for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
193 if (init_type(cluster, j)) {
194 if (count == core)
195 return i;
196 count++;
197 }
198 }
199 i++;
200 } while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
201
202 return -1; /* cannot identify the cluster */
203}
204
York Sun123bd962012-08-17 08:20:22 +0000205#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
206/*
207 * Before chassis genenration 2, the cpumask should be hard-coded.
208 * In case of cpu type unknown or cpumask unset, use 1 as fail save.
209 */
210#define compute_ppc_cpumask() 1
York Sunf6981432013-03-25 07:40:07 +0000211#define fsl_qoriq_core_to_cluster(x) x
York Sun123bd962012-08-17 08:20:22 +0000212#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
213
Kim Phillips2ed2e912012-10-29 13:34:37 +0000214static struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 0);
Poonam Aggrwal58442dc2009-09-02 13:35:21 +0530215
Poonam Aggrwal18bacc22009-07-31 12:07:45 +0530216struct cpu_type *identify_cpu(u32 ver)
217{
218 int i;
219 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) {
220 if (cpu_type_list[i].soc_ver == ver)
221 return &cpu_type_list[i];
222 }
Poonam Aggrwal58442dc2009-09-02 13:35:21 +0530223 return &cpu_type_unknown;
Poonam Aggrwal18bacc22009-07-31 12:07:45 +0530224}
225
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500226#define MPC8xxx_PICFRR_NCPU_MASK 0x00001f00
227#define MPC8xxx_PICFRR_NCPU_SHIFT 8
228
229/*
230 * Return a 32-bit mask indicating which cores are present on this SOC.
231 */
Alexander Grafb5395342014-04-30 19:21:10 +0200232__weak u32 cpu_mask(void)
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500233{
234 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
Simon Glass67ac13b2012-12-13 20:48:48 +0000235 struct cpu_type *cpu = gd->arch.cpu;
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500236
237 /* better to query feature reporting register than just assume 1 */
238 if (cpu == &cpu_type_unknown)
239 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
240 MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
241
York Sun123bd962012-08-17 08:20:22 +0000242 if (cpu->num_cores == 0)
243 return compute_ppc_cpumask();
244
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500245 return cpu->mask;
246}
247
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530248#ifdef CONFIG_HETROGENOUS_CLUSTERS
249__weak u32 cpu_dsp_mask(void)
250{
251 ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
252 struct cpu_type *cpu = gd->arch.cpu;
253
254 /* better to query feature reporting register than just assume 1 */
255 if (cpu == &cpu_type_unknown)
256 return ((in_be32(&pic->frr) & MPC8xxx_PICFRR_NCPU_MASK) >>
257 MPC8xxx_PICFRR_NCPU_SHIFT) + 1;
258
259 if (cpu->dsp_num_cores == 0)
260 return compute_dsp_cpumask();
261
262 return cpu->dsp_mask;
263}
264
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500265/*
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530266 * Return the number of SC/DSP cores on this SOC.
267 */
268__weak int cpu_num_dspcores(void)
269{
270 struct cpu_type *cpu = gd->arch.cpu;
271
272 /*
273 * Report # of cores in terms of the cpu_mask if we haven't
274 * figured out how many there are yet
275 */
276 if (cpu->dsp_num_cores == 0)
277 return hweight32(cpu_dsp_mask());
278
279 return cpu->dsp_num_cores;
280}
281#endif
282
283/*
284 * Return the number of PPC cores on this SOC.
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500285 */
Alexander Grafb5395342014-04-30 19:21:10 +0200286__weak int cpu_numcores(void)
Kim Phillips2ed2e912012-10-29 13:34:37 +0000287{
Simon Glass67ac13b2012-12-13 20:48:48 +0000288 struct cpu_type *cpu = gd->arch.cpu;
Kim Phillipsa37c36f2010-07-14 19:47:29 -0500289
York Sun123bd962012-08-17 08:20:22 +0000290 /*
291 * Report # of cores in terms of the cpu_mask if we haven't
292 * figured out how many there are yet
293 */
294 if (cpu->num_cores == 0)
295 return hweight32(cpu_mask());
Kim Phillipsa37c36f2010-07-14 19:47:29 -0500296
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530297 return cpu->num_cores;
298}
299
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530300
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500301/*
302 * Check if the given core ID is valid
303 *
304 * Returns zero if it isn't, 1 if it is.
305 */
306int is_core_valid(unsigned int core)
307{
York Sun123bd962012-08-17 08:20:22 +0000308 return !!((1 << core) & cpu_mask());
Timur Tabifbb9ecf2011-08-05 16:15:24 -0500309}
310
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530311int probecpu (void)
312{
313 uint svr;
314 uint ver;
315
316 svr = get_svr();
317 ver = SVR_SOC_VER(svr);
318
Simon Glass67ac13b2012-12-13 20:48:48 +0000319 gd->arch.cpu = identify_cpu(ver);
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530320
Poonam Aggrwal0e870982009-07-31 12:08:14 +0530321 return 0;
322}
323
York Sun123bd962012-08-17 08:20:22 +0000324/* Once in memory, compute mask & # cores once and save them off */
325int fixup_cpu(void)
326{
Simon Glass67ac13b2012-12-13 20:48:48 +0000327 struct cpu_type *cpu = gd->arch.cpu;
York Sun123bd962012-08-17 08:20:22 +0000328
329 if (cpu->num_cores == 0) {
330 cpu->mask = cpu_mask();
331 cpu->num_cores = cpu_numcores();
332 }
333
Shaveta Leekhab8bf0ad2015-01-19 12:46:54 +0530334#ifdef CONFIG_HETROGENOUS_CLUSTERS
335 if (cpu->dsp_num_cores == 0) {
336 cpu->dsp_mask = cpu_dsp_mask();
337 cpu->dsp_num_cores = cpu_num_dspcores();
338 }
339#endif
York Sun123bd962012-08-17 08:20:22 +0000340 return 0;
341}
342
Poonam Aggrwal18bacc22009-07-31 12:07:45 +0530343/*
344 * Initializes on-chip ethernet controllers.
345 * to override, implement board_eth_init()
346 */
347int cpu_eth_init(bd_t *bis)
348{
349#if defined(CONFIG_ETHER_ON_FCC)
350 fec_initialize(bis);
351#endif
352
353#if defined(CONFIG_UEC_ETH)
354 uec_standard_init(bis);
355#endif
356
357#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_MPC85XX_FEC)
358 tsec_standard_init(bis);
359#endif
360
Kumar Galac916d7c2011-04-13 08:37:44 -0500361#ifdef CONFIG_FMAN_ENET
362 fm_standard_init(bis);
363#endif
Codrin Ciubotariu7e40e4b2015-01-21 11:54:10 +0200364
365#ifdef CONFIG_VSC9953
366 vsc9953_init(bis);
367#endif
Poonam Aggrwal18bacc22009-07-31 12:07:45 +0530368 return 0;
369}