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Kumar Gala44a23cf2008-01-16 22:33:22 -06001/*
Kumar Galad30f9042009-09-11 11:27:00 -05002 * Copyright 2008-2009 Freescale Semiconductor, Inc.
Kumar Gala44a23cf2008-01-16 22:33:22 -06003 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/processor.h>
28#include <asm/mmu.h>
Kumar Galaecf5b982008-12-16 14:59:20 -060029#ifdef CONFIG_ADDR_MAP
30#include <addr_map.h>
31#endif
32
33DECLARE_GLOBAL_DATA_PTR;
Kumar Gala44a23cf2008-01-16 22:33:22 -060034
Kumar Galab2eec282009-09-11 12:32:01 -050035void invalidate_tlb(u8 tlb)
36{
37 if (tlb == 0)
38 mtspr(MMUCSR0, 0x4);
39 if (tlb == 1)
40 mtspr(MMUCSR0, 0x2);
41}
42
43void init_tlbs(void)
44{
45 int i;
46
47 for (i = 0; i < num_tlb_entries; i++) {
48 write_tlb(tlb_table[i].mas0,
49 tlb_table[i].mas1,
50 tlb_table[i].mas2,
51 tlb_table[i].mas3,
52 tlb_table[i].mas7);
53 }
54
55 return ;
56}
57
Mingkai Hu7da53352009-09-11 14:19:10 +080058#ifndef CONFIG_NAND_SPL
Kumar Gala44a23cf2008-01-16 22:33:22 -060059void set_tlb(u8 tlb, u32 epn, u64 rpn,
60 u8 perms, u8 wimge,
61 u8 ts, u8 esel, u8 tsize, u8 iprot)
62{
63 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
64
65 _mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
66 _mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
67 _mas2 = FSL_BOOKE_MAS2(epn, wimge);
68 _mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
Kumar Galad30f9042009-09-11 11:27:00 -050069 _mas7 = FSL_BOOKE_MAS7(rpn);
Kumar Gala44a23cf2008-01-16 22:33:22 -060070
Kumar Galad30f9042009-09-11 11:27:00 -050071 write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
Kumar Galaecf5b982008-12-16 14:59:20 -060072
73#ifdef CONFIG_ADDR_MAP
74 if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
75 addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), esel);
76#endif
Kumar Gala44a23cf2008-01-16 22:33:22 -060077}
78
79void disable_tlb(u8 esel)
80{
81 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
82
83 _mas0 = FSL_BOOKE_MAS0(1, esel, 0);
84 _mas1 = 0;
85 _mas2 = 0;
86 _mas3 = 0;
87 _mas7 = 0;
88
89 mtspr(MAS0, _mas0);
90 mtspr(MAS1, _mas1);
91 mtspr(MAS2, _mas2);
92 mtspr(MAS3, _mas3);
93#ifdef CONFIG_ENABLE_36BIT_PHYS
94 mtspr(MAS7, _mas7);
95#endif
96 asm volatile("isync;msync;tlbwe;isync");
Kumar Galaecf5b982008-12-16 14:59:20 -060097
98#ifdef CONFIG_ADDR_MAP
99 if (gd->flags & GD_FLG_RELOC)
100 addrmap_set_entry(0, 0, 0, esel);
101#endif
Kumar Gala44a23cf2008-01-16 22:33:22 -0600102}
103
Kumar Galac2287af2009-09-03 08:20:24 -0500104static void tlbsx (const volatile unsigned *addr)
105{
106 __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
107}
108
109/* return -1 if we didn't find anything */
110int find_tlb_idx(void *addr, u8 tlbsel)
111{
112 u32 _mas0, _mas1;
113
114 /* zero out Search PID, AS */
115 mtspr(MAS6, 0);
116
117 tlbsx(addr);
118
119 _mas0 = mfspr(MAS0);
120 _mas1 = mfspr(MAS1);
121
122 /* we found something, and its in the TLB we expect */
123 if ((MAS1_VALID & _mas1) &&
124 (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
125 return ((_mas0 & MAS0_ESEL_MSK) >> 16);
126 }
127
128 return -1;
129}
130
Kumar Galaecf5b982008-12-16 14:59:20 -0600131#ifdef CONFIG_ADDR_MAP
132void init_addr_map(void)
133{
134 int i;
Kumar Galacdbdbe62009-11-13 08:52:21 -0600135 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
Kumar Galaecf5b982008-12-16 14:59:20 -0600136
Kumar Galae393e2e2009-08-14 16:43:22 -0500137 /* walk all the entries */
Kumar Galacdbdbe62009-11-13 08:52:21 -0600138 for (i = 0; i < num_cam; i++) {
Kumar Galae393e2e2009-08-14 16:43:22 -0500139 unsigned long epn;
Wolfgang Denk963f2f62009-08-22 23:27:26 +0200140 u32 tsize, _mas1;
Kumar Galae393e2e2009-08-14 16:43:22 -0500141 phys_addr_t rpn;
142
143 mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
144
145 asm volatile("tlbre;isync");
146 _mas1 = mfspr(MAS1);
147
148 /* if the entry isn't valid skip it */
149 if (!(_mas1 & MAS1_VALID))
Kumar Galaecf5b982008-12-16 14:59:20 -0600150 continue;
151
Kumar Galae393e2e2009-08-14 16:43:22 -0500152 tsize = (_mas1 >> 8) & 0xf;
153 epn = mfspr(MAS2) & MAS2_EPN;
154 rpn = mfspr(MAS3) & MAS3_RPN;
155#ifdef CONFIG_ENABLE_36BIT_PHYS
156 rpn |= ((phys_addr_t)mfspr(MAS7)) << 32;
157#endif
158
159 addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i);
Kumar Galaecf5b982008-12-16 14:59:20 -0600160 }
161
162 return ;
163}
164#endif
165
Haiying Wang95026432009-01-13 16:29:22 -0500166#ifndef CONFIG_SYS_DDR_TLB_START
167#define CONFIG_SYS_DDR_TLB_START 8
168#endif
169
Kumar Gala6fb1b732008-06-09 11:07:46 -0500170unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
171{
172 unsigned int tlb_size;
Kumar Galaf8523cb2009-02-06 09:56:35 -0600173 unsigned int ram_tlb_index = CONFIG_SYS_DDR_TLB_START;
174 unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
Fredrik Arnerup90d13b82009-06-02 16:27:10 -0500175 unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf;
Kumar Galaf8523cb2009-02-06 09:56:35 -0600176 u64 size, memsize = (u64)memsize_in_meg << 20;
Kumar Gala6fb1b732008-06-09 11:07:46 -0500177
Kumar Galaf8523cb2009-02-06 09:56:35 -0600178 size = min(memsize, CONFIG_MAX_MEM_MAPPED);
Kumar Gala6fb1b732008-06-09 11:07:46 -0500179
Kumar Galaf8523cb2009-02-06 09:56:35 -0600180 /* Convert (4^max) kB to (2^max) bytes */
181 max_cam = max_cam * 2 + 10;
Kumar Gala6fb1b732008-06-09 11:07:46 -0500182
Kumar Galaf8523cb2009-02-06 09:56:35 -0600183 for (; size && ram_tlb_index < 16; ram_tlb_index++) {
184 u32 camsize = __ilog2_u64(size) & ~1U;
185 u32 align = __ilog2(ram_tlb_address) & ~1U;
186
187 if (align == -2) align = max_cam;
188 if (camsize > align)
189 camsize = align;
190
191 if (camsize > max_cam)
192 camsize = max_cam;
193
194 tlb_size = (camsize - 10) / 2;
195
Kumar Gala6fb1b732008-06-09 11:07:46 -0500196 set_tlb(1, ram_tlb_address, ram_tlb_address,
197 MAS3_SX|MAS3_SW|MAS3_SR, 0,
198 0, ram_tlb_index, tlb_size, 1);
199
Kumar Galaf8523cb2009-02-06 09:56:35 -0600200 size -= 1ULL << camsize;
201 memsize -= 1ULL << camsize;
202 ram_tlb_address += 1UL << camsize;
Kumar Gala6fb1b732008-06-09 11:07:46 -0500203 }
204
Kumar Galaf8523cb2009-02-06 09:56:35 -0600205 if (memsize)
Kumar Galad4b130d2009-06-11 23:40:34 -0500206 print_size(memsize, " left unmapped\n");
Kumar Galaf8523cb2009-02-06 09:56:35 -0600207
Kumar Gala6fb1b732008-06-09 11:07:46 -0500208 /*
209 * Confirm that the requested amount of memory was mapped.
210 */
211 return memsize_in_meg;
212}
Mingkai Hu7da53352009-09-11 14:19:10 +0800213#endif /* !CONFIG_NAND_SPL */