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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher0f8bc282013-12-02 07:47:22 +01002/*
3 * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards
4 * (C) Copyright 2013 Siemens AG
5 *
6 * Based on:
7 * U-Boot file: include/configs/at91sam9260ek.h
8 *
9 * (C) Copyright 2007-2008
10 * Stelian Pop <stelian@popies.net>
11 * Lead Tech Design <www.leadtechdesign.com>
Heiko Schocher0f8bc282013-12-02 07:47:22 +010012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * SoC must be defined first, before hardware.h is included.
19 * In this case SoC is defined in boards.cfg.
20 */
21#include <asm/hardware.h>
Heiko Schocher40540822015-08-21 18:53:46 +020022#include <linux/sizes.h>
Heiko Schocher0f8bc282013-12-02 07:47:22 +010023
Heiko Schocher389aee82014-11-18 09:41:57 +010024#if defined(CONFIG_SPL_BUILD)
Heiko Schocher389aee82014-11-18 09:41:57 +010025#define CONFIG_SYS_ICACHE_OFF
26#define CONFIG_SYS_DCACHE_OFF
27#endif
Heiko Schocher0f8bc282013-12-02 07:47:22 +010028/*
29 * Warning: changing CONFIG_SYS_TEXT_BASE requires
30 * adapting the initial boot program.
31 * Since the linker has to swallow that define, we must use a pure
32 * hex number here!
33 */
34
Heiko Schocher0f8bc282013-12-02 07:47:22 +010035/* ARM asynchronous clock */
36#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
37#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */
Heiko Schocher0f8bc282013-12-02 07:47:22 +010038
39/* Misc CPU related */
40#define CONFIG_ARCH_CPU_INIT
41#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
42#define CONFIG_SETUP_MEMORY_TAGS
43#define CONFIG_INITRD_TAG
Heiko Schocher8e6e8222016-05-25 07:23:48 +020044#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
Heiko Schocher0f8bc282013-12-02 07:47:22 +010045
Heiko Schocher0f8bc282013-12-02 07:47:22 +010046/* general purpose I/O */
47#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
48#define CONFIG_AT91_GPIO
49#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
50
51/* serial console */
52#define CONFIG_ATMEL_USART
53#define CONFIG_USART_BASE ATMEL_BASE_DBGU
54#define CONFIG_USART_ID ATMEL_ID_SYS
Heiko Schocher0f8bc282013-12-02 07:47:22 +010055
Heiko Schocher0f8bc282013-12-02 07:47:22 +010056
57/*
Heiko Schocher0f8bc282013-12-02 07:47:22 +010058 * SDRAM: 1 bank, min 32, max 128 MB
59 * Initialized before u-boot gets started.
60 */
Heiko Schocher0f8bc282013-12-02 07:47:22 +010061#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
Heiko Schocher0ed366f2015-08-21 18:55:07 +020062#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
Heiko Schocher0f8bc282013-12-02 07:47:22 +010063
64/*
65 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
66 * leaving the correct space for initial global data structure above
67 * that address while providing maximum stack area below.
68 */
Heiko Schocher0ed366f2015-08-21 18:55:07 +020069#define CONFIG_SYS_INIT_SP_ADDR \
Heiko Schocher0f8bc282013-12-02 07:47:22 +010070 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
71
72/* NAND flash */
73#ifdef CONFIG_CMD_NAND
Heiko Schocher0f8bc282013-12-02 07:47:22 +010074#define CONFIG_SYS_MAX_NAND_DEVICE 1
75#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
76#define CONFIG_SYS_NAND_DBW_8
77#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
78#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
79#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
80#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
81#endif
82
Heiko Schocher0f8bc282013-12-02 07:47:22 +010083/* Ethernet */
84#define CONFIG_MACB
85#define CONFIG_RMII
86#define CONFIG_AT91_WANTS_COMMON_PHY
87
88/* USB */
89#if defined(CONFIG_BOARD_TAURUS)
90#define CONFIG_USB_ATMEL
Heiko Schochere8b81ee2015-09-08 11:52:52 +020091#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Heiko Schocher0f8bc282013-12-02 07:47:22 +010092#define CONFIG_USB_OHCI_NEW
93#define CONFIG_SYS_USB_OHCI_CPU_INIT
94#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
95#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
96#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Heiko Schochere8b81ee2015-09-08 11:52:52 +020097
98/* USB DFU support */
Heiko Schochere8b81ee2015-09-08 11:52:52 +020099
Heiko Schochere8b81ee2015-09-08 11:52:52 +0200100#define CONFIG_USB_GADGET_AT91
101
102/* DFU class support */
Heiko Schochere8b81ee2015-09-08 11:52:52 +0200103#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M)
104#define DFU_MANIFEST_POLL_TIMEOUT 25000
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100105#endif
106
Heiko Schocher50921cd2014-10-31 08:30:56 +0100107/* SPI EEPROM */
Heiko Schocher50921cd2014-10-31 08:30:56 +0100108#define TAURUS_SPI_MASK (1 << 4)
109#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
110
Heiko Schochera1655bb2014-11-18 09:41:58 +0100111#if defined(CONFIG_SPL_BUILD)
112/* SPL related */
Heiko Schochera1655bb2014-11-18 09:41:58 +0100113#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
114
115#define CONFIG_SF_DEFAULT_BUS 0
Heiko Schocher0ed366f2015-08-21 18:55:07 +0200116#define CONFIG_SF_DEFAULT_SPEED 1000000
117#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
Heiko Schochera1655bb2014-11-18 09:41:58 +0100118#endif
119
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100120/* load address */
121#define CONFIG_SYS_LOAD_ADDR 0x22000000
122
123/* bootstrap in spi flash , u-boot + env + linux in nandflash */
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100124#define CONFIG_ENV_OFFSET 0x100000
125#define CONFIG_ENV_OFFSET_REDUND 0x180000
Heiko Schocher0ed366f2015-08-21 18:55:07 +0200126#define CONFIG_ENV_SIZE (SZ_128K) /* 1 sector = 128 kB */
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100127#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
Heiko Schocher40540822015-08-21 18:53:46 +0200128
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100129/*
130 * Size of malloc() pool
131 */
132#define CONFIG_SYS_MALLOC_LEN \
Heiko Schochere8b81ee2015-09-08 11:52:52 +0200133 ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000)
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100134
Heiko Schocher237e3792014-10-31 08:31:05 +0100135/* Defines for SPL */
Heiko Schocher237e3792014-10-31 08:31:05 +0100136#define CONFIG_SPL_TEXT_BASE 0x0
Heiko Schocher40540822015-08-21 18:53:46 +0200137#define CONFIG_SPL_MAX_SIZE (31 * SZ_512)
138#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K)
Heiko Schochera1655bb2014-11-18 09:41:58 +0100139#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \
140 CONFIG_SYS_MALLOC_LEN)
141#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
Heiko Schocher237e3792014-10-31 08:31:05 +0100142
143#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE
Heiko Schocher0ed366f2015-08-21 18:55:07 +0200144#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512)
Heiko Schocher237e3792014-10-31 08:31:05 +0100145
Heiko Schocher237e3792014-10-31 08:31:05 +0100146#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14)
Heiko Schocher237e3792014-10-31 08:31:05 +0100147#define CONFIG_SYS_USE_NANDFLASH 1
148#define CONFIG_SPL_NAND_DRIVERS
149#define CONFIG_SPL_NAND_BASE
150#define CONFIG_SPL_NAND_ECC
151#define CONFIG_SPL_NAND_RAW_ONLY
152#define CONFIG_SPL_NAND_SOFTECC
153#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000
Heiko Schochere8b81ee2015-09-08 11:52:52 +0200154#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K
Heiko Schocher237e3792014-10-31 08:31:05 +0100155#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
156#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
157#define CONFIG_SYS_NAND_5_ADDR_CYCLE
158
Heiko Schocher0ed366f2015-08-21 18:55:07 +0200159#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
160#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K
161#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K)
Heiko Schocher237e3792014-10-31 08:31:05 +0100162#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
163 CONFIG_SYS_NAND_PAGE_SIZE)
164#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
165#define CONFIG_SYS_NAND_ECCSIZE 256
166#define CONFIG_SYS_NAND_ECCBYTES 3
167#define CONFIG_SYS_NAND_OOBSIZE 64
168#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
169 48, 49, 50, 51, 52, 53, 54, 55, \
170 56, 57, 58, 59, 60, 61, 62, 63, }
171
Heiko Schocher237e3792014-10-31 08:31:05 +0100172#define CONFIG_SPL_ATMEL_SIZE
173#define CONFIG_SYS_MASTER_CLOCK 132096000
174#define AT91_PLL_LOCK_TIMEOUT 1000000
175#define CONFIG_SYS_AT91_PLLA 0x202A3F01
176#define CONFIG_SYS_MCKR 0x1300
177#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR)
178#define CONFIG_SYS_AT91_PLLB 0x10193F05
Heiko Schocher40540822015-08-21 18:53:46 +0200179
Heiko Schocher0f8bc282013-12-02 07:47:22 +0100180#endif