blob: 6c3dfe894f171da584c9efd4b1c092335346538c [file] [log] [blame]
Simon Glass3a1a18f2015-01-27 22:13:47 -07001/*
2 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#include <common.h>
8#include <mmc.h>
9#include <pci_ids.h>
Bin Mengfe3fbd32015-07-30 03:49:18 -070010#include <asm/irq.h>
Simon Glass3a1a18f2015-01-27 22:13:47 -070011#include <asm/post.h>
Simon Glass46f8efe2015-08-10 07:05:10 -060012#include <asm/fsp/fsp_support.h>
Simon Glass3a1a18f2015-01-27 22:13:47 -070013
14static struct pci_device_id mmc_supported[] = {
15 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDIO },
16 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SDCARD },
17};
18
19int cpu_mmc_init(bd_t *bis)
20{
Simon Glass3a1a18f2015-01-27 22:13:47 -070021 return pci_mmc_init("ValleyView SDHCI", mmc_supported,
22 ARRAY_SIZE(mmc_supported));
23}
24
Simon Glassb4302582015-08-04 12:34:02 -060025#ifndef CONFIG_EFI_APP
Simon Glass3a1a18f2015-01-27 22:13:47 -070026int arch_cpu_init(void)
27{
28 int ret;
29
30 post_code(POST_CPU_INIT);
31#ifdef CONFIG_SYS_X86_TSC_TIMER
32 timer_set_base(rdtsc());
33#endif
34
35 ret = x86_cpu_init_f();
36 if (ret)
37 return ret;
38
39 return 0;
40}
Bin Mengfe3fbd32015-07-30 03:49:18 -070041
42int arch_misc_init(void)
43{
Simon Glass46f8efe2015-08-10 07:05:10 -060044 int ret;
45
Simon Glassc8896ee2015-08-10 07:05:12 -060046 if (!ll_boot_init())
47 return 0;
Simon Glass46f8efe2015-08-10 07:05:10 -060048 ret = pirq_init();
49 if (ret)
50 return ret;
51
52 return fsp_init_phase_pci();
Bin Mengfe3fbd32015-07-30 03:49:18 -070053}
Simon Glassb4302582015-08-04 12:34:02 -060054#endif