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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese0299c902015-10-20 15:14:47 +02002/*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
Stefan Roese0299c902015-10-20 15:14:47 +02004 */
5
6#include <common.h>
Simon Glass09140112020-05-10 11:40:03 -06007#include <env.h>
Stefan Roese0299c902015-10-20 15:14:47 +02008#include <i2c.h>
Simon Glass691d7192020-05-10 11:40:02 -06009#include <init.h>
Stefan Roese0299c902015-10-20 15:14:47 +020010#include <miiphy.h>
Simon Glass90526e92020-05-10 11:39:56 -060011#include <net.h>
Stefan Roese0299c902015-10-20 15:14:47 +020012#include <netdev.h>
Martin Rowec733fe92023-03-27 21:24:09 +100013#include <mmc.h>
Simon Glass401d1c42020-10-30 21:38:53 -060014#include <asm/global_data.h>
Stefan Roese0299c902015-10-20 15:14:47 +020015#include <asm/io.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/soc.h>
Simon Glasscd93d622020-05-10 11:40:13 -060018#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060019#include <linux/delay.h>
Baruch Siacha2e41ad2020-01-20 14:20:11 +020020#include "../common/tlv_data.h"
Stefan Roese0299c902015-10-20 15:14:47 +020021
Chris Packham2b4ffbf2018-05-10 13:28:29 +120022#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
Stefan Roese0299c902015-10-20 15:14:47 +020023#include <../serdes/a38x/high_speed_env_spec.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
Stefan Roese0299c902015-10-20 15:14:47 +020027/*
28 * Those values and defines are taken from the Marvell U-Boot version
29 * "u-boot-2013.01-15t1-clearfog"
30 */
31#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
32#define BOARD_GPP_OUT_ENA_MID 0xffffffff
33
34#define BOARD_GPP_OUT_VAL_LOW 0x0
35#define BOARD_GPP_OUT_VAL_MID 0x0
36#define BOARD_GPP_POL_LOW 0x0
37#define BOARD_GPP_POL_MID 0x0
38
Baruch Siacha2e41ad2020-01-20 14:20:11 +020039static struct tlv_data cf_tlv_data;
40
41static void cf_read_tlv_data(void)
42{
43 static bool read_once;
44
45 if (read_once)
46 return;
47 read_once = true;
48
49 read_tlv_data(&cf_tlv_data);
50}
51
Joel Johnson9f205d62020-03-23 14:21:32 -060052/* The starting board_serdes_map reflects original Clearfog Pro usage */
Stefan Roese0299c902015-10-20 15:14:47 +020053static struct serdes_map board_serdes_map[] = {
54 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
55 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
56 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
57 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
58 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
59 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
60};
61
Joel Johnson9f205d62020-03-23 14:21:32 -060062void config_cfbase_serdes_map(void)
63{
64 board_serdes_map[4].serdes_type = USB3_HOST0;
65 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
66 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
67}
68
Stefan Roese0299c902015-10-20 15:14:47 +020069int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
70{
Baruch Siach5e983842020-01-20 14:20:14 +020071 cf_read_tlv_data();
72
Joel Johnson8a863082020-03-23 14:21:33 -060073 /* Apply build configuration options before runtime configuration */
74 if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
75 board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
76
Joel Johnson009d4cf2020-03-23 14:21:34 -060077 if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
78 board_serdes_map[4].serdes_type = SATA2;
79 board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
80 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
81 board_serdes_map[4].swap_rx = 1;
82 }
83
84 if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
85 board_serdes_map[2].serdes_type = SATA1;
86 board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
87 board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
88 board_serdes_map[2].swap_rx = 1;
89 }
90
Joel Johnson8a863082020-03-23 14:21:33 -060091 /* Apply runtime detection changes */
Baruch Siach5e983842020-01-20 14:20:14 +020092 if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
93 board_serdes_map[0].serdes_type = PEX0;
94 board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
95 board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
Joel Johnson9f205d62020-03-23 14:21:32 -060096 } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
97 /* handle recognized product as noop, no adjustment required */
98 } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
99 config_cfbase_serdes_map();
100 } else {
101 /*
102 * Fallback to static default. EEPROM TLV support is not
103 * enabled, runtime detection failed, hardware support is not
104 * present, EEPROM is corrupt, or an unrecognized product name
105 * is present.
106 */
107 if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
108 puts("EEPROM TLV detection failed: ");
109 puts("Using static config for ");
110 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
111 puts("Clearfog Base.\n");
112 config_cfbase_serdes_map();
113 } else {
114 puts("Clearfog Pro.\n");
115 }
Baruch Siach584a3d22020-01-20 14:20:15 +0200116 }
117
Stefan Roese0299c902015-10-20 15:14:47 +0200118 *serdes_map_array = board_serdes_map;
119 *count = ARRAY_SIZE(board_serdes_map);
120 return 0;
121}
122
123/*
124 * Define the DDR layout / topology here in the board file. This will
125 * be used by the DDR3 init code in the SPL U-Boot version to configure
126 * the DDR3 controller.
127 */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200128static struct mv_ddr_topology_map board_topology_map = {
129 DEBUG_LEVEL_ERROR,
Stefan Roese0299c902015-10-20 15:14:47 +0200130 0x1, /* active interfaces */
131 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
132 { { { {0x1, 0, 0, 0},
133 {0x1, 0, 0, 0},
134 {0x1, 0, 0, 0},
135 {0x1, 0, 0, 0},
136 {0x1, 0, 0, 0} },
137 SPEED_BIN_DDR_1600K, /* speed_bin */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200138 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
139 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
Chris Packhamebb1a592018-12-03 14:26:49 +1300140 MV_DDR_FREQ_800, /* frequency */
Chris Packham01c541e2017-11-29 10:38:34 +1300141 0, 0, /* cas_wl cas_l */
Chris Packhame6f61622018-05-10 13:28:30 +1200142 MV_DDR_TEMP_LOW, /* temperature */
143 MV_DDR_TIM_DEFAULT} }, /* timing */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200144 BUS_MASK_32BIT, /* Busses mask */
145 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
Moti Buskila32e7a6b2021-02-19 17:11:19 +0100146 NOT_COMBINED, /* ddr twin-die combined */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200147 { {0} }, /* raw spd data */
Baruch Siach66646fa2020-01-20 14:20:07 +0200148 {0}, /* timing parameters */
149 { {0} }, /* electrical configuration */
150 {0,}, /* electrical parameters */
Chris Packham0a6f0292022-03-01 13:53:23 +1300151 0, /* ODT configuration */
Baruch Siach66646fa2020-01-20 14:20:07 +0200152 0x3, /* clock enable mask */
Stefan Roese0299c902015-10-20 15:14:47 +0200153};
154
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200155struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
Stefan Roese0299c902015-10-20 15:14:47 +0200156{
Baruch Siacha2e41ad2020-01-20 14:20:11 +0200157 struct if_params *ifp = &board_topology_map.interface_params[0];
158
159 cf_read_tlv_data();
160
161 switch (cf_tlv_data.ram_size) {
162 case 4:
163 default:
164 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
165 break;
166 case 8:
167 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
168 break;
169 }
170
Stefan Roese0299c902015-10-20 15:14:47 +0200171 /* Return the board topology as defined in the board code */
172 return &board_topology_map;
173}
174
175int board_early_init_f(void)
176{
177 /* Configure MPP */
178 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
179 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
180 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
181 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
182 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
183 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
184 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
185 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
186
187 /* Set GPP Out value */
188 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
189 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
190
191 /* Set GPP Polarity */
192 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
193 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
194
195 /* Set GPP Out Enable */
196 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
197 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
198
199 return 0;
200}
201
202int board_init(void)
203{
Stefan Roese0299c902015-10-20 15:14:47 +0200204 /* Address of boot parameters */
205 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
206
207 /* Toggle GPIO41 to reset onboard switch and phy */
208 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
209 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
Patrick Wildtfb9765d2017-05-09 13:54:44 +0200210 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
211 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
212 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
Stefan Roese0299c902015-10-20 15:14:47 +0200213 mdelay(1);
214 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
Patrick Wildtfb9765d2017-05-09 13:54:44 +0200215 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
Stefan Roese0299c902015-10-20 15:14:47 +0200216 mdelay(10);
217
Stefan Roese0299c902015-10-20 15:14:47 +0200218 return 0;
219}
220
221int checkboard(void)
222{
Joel Johnsonee26e852020-03-23 14:21:31 -0600223 char *board = "Clearfog Pro";
Joel Johnson9f205d62020-03-23 14:21:32 -0600224 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
225 board = "Clearfog Base";
Baruch Siach7211fa62020-01-20 14:20:12 +0200226
227 cf_read_tlv_data();
228 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
229 board = cf_tlv_data.tlv_product_name[0];
230
231 printf("Board: SolidRun %s", board);
232 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
233 printf(", %s", cf_tlv_data.tlv_product_name[1]);
234 puts("\n");
Stefan Roese0299c902015-10-20 15:14:47 +0200235
236 return 0;
237}
238
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900239int board_eth_init(struct bd_info *bis)
Stefan Roese0299c902015-10-20 15:14:47 +0200240{
241 cpu_eth_init(bis); /* Built in controller(s) come first */
242 return pci_eth_init(bis);
243}
Baruch Siach867572f2020-01-20 14:20:13 +0200244
245int board_late_init(void)
246{
Baruch Siach5a3f5e62020-09-09 15:14:39 +0300247 if (env_get("fdtfile"))
248 return 0;
249
Baruch Siach867572f2020-01-20 14:20:13 +0200250 cf_read_tlv_data();
251
252 if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
253 env_set("fdtfile", "armada-388-clearfog-base.dtb");
254 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
255 env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
256 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
257 env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
Joel Johnson9f205d62020-03-23 14:21:32 -0600258 else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
259 env_set("fdtfile", "armada-388-clearfog-base.dtb");
Joel Johnson8eccd0d2020-03-23 14:21:35 -0600260 else
Joel Johnson27f48f72020-03-23 14:21:40 -0600261 env_set("fdtfile", "armada-388-clearfog-pro.dtb");
Baruch Siach867572f2020-01-20 14:20:13 +0200262
263 return 0;
264}
Martin Rowec733fe92023-03-27 21:24:09 +1000265
266static bool has_emmc(void)
267{
268 struct mmc *mmc;
269
270 mmc = find_mmc_device(0);
271 if (!mmc)
272 return 0;
273 return (!mmc_init(mmc) && IS_MMC(mmc)) ? true : false;
274}
275
276/*
277 * The Clearfog devices have only one SDHC device. This is either eMMC
278 * if it is populated on the SOM or SDHC if not. The Linux device tree
279 * assumes the SDHC case. Detect if the device is an eMMC and fixup the
280 * device-tree, so that it will be detected by Linux.
281 */
282int ft_board_setup(void *blob, struct bd_info *bd)
283{
284 int node;
285
286 if (has_emmc()) {
287 node = fdt_node_offset_by_compatible(blob, -1, "marvell,armada-380-sdhci");
288 if (node < 0)
289 return 0; /* Unexpected eMMC device; patching not supported */
290
291 puts("Patching FDT so that eMMC is detected by OS\n");
292 return fdt_setprop_empty(blob, node, "non-removable");
293 }
294
295 return 0;
296}