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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roese0299c902015-10-20 15:14:47 +02002/*
3 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
Stefan Roese0299c902015-10-20 15:14:47 +02004 */
5
6#include <common.h>
Simon Glass09140112020-05-10 11:40:03 -06007#include <env.h>
Stefan Roese0299c902015-10-20 15:14:47 +02008#include <i2c.h>
Simon Glass691d7192020-05-10 11:40:02 -06009#include <init.h>
Stefan Roese0299c902015-10-20 15:14:47 +020010#include <miiphy.h>
Simon Glass90526e92020-05-10 11:39:56 -060011#include <net.h>
Stefan Roese0299c902015-10-20 15:14:47 +020012#include <netdev.h>
13#include <asm/io.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/soc.h>
Simon Glasscd93d622020-05-10 11:40:13 -060016#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060017#include <linux/delay.h>
Baruch Siacha2e41ad2020-01-20 14:20:11 +020018#include "../common/tlv_data.h"
Stefan Roese0299c902015-10-20 15:14:47 +020019
Chris Packham2b4ffbf2018-05-10 13:28:29 +120020#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
Stefan Roese0299c902015-10-20 15:14:47 +020021#include <../serdes/a38x/high_speed_env_spec.h>
22
23DECLARE_GLOBAL_DATA_PTR;
24
Stefan Roese0299c902015-10-20 15:14:47 +020025/*
26 * Those values and defines are taken from the Marvell U-Boot version
27 * "u-boot-2013.01-15t1-clearfog"
28 */
29#define BOARD_GPP_OUT_ENA_LOW 0xffffffff
30#define BOARD_GPP_OUT_ENA_MID 0xffffffff
31
32#define BOARD_GPP_OUT_VAL_LOW 0x0
33#define BOARD_GPP_OUT_VAL_MID 0x0
34#define BOARD_GPP_POL_LOW 0x0
35#define BOARD_GPP_POL_MID 0x0
36
Baruch Siacha2e41ad2020-01-20 14:20:11 +020037static struct tlv_data cf_tlv_data;
38
39static void cf_read_tlv_data(void)
40{
41 static bool read_once;
42
43 if (read_once)
44 return;
45 read_once = true;
46
47 read_tlv_data(&cf_tlv_data);
48}
49
Joel Johnson9f205d62020-03-23 14:21:32 -060050/* The starting board_serdes_map reflects original Clearfog Pro usage */
Stefan Roese0299c902015-10-20 15:14:47 +020051static struct serdes_map board_serdes_map[] = {
52 {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
53 {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
54 {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
55 {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
56 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
57 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
58};
59
Joel Johnson9f205d62020-03-23 14:21:32 -060060void config_cfbase_serdes_map(void)
61{
62 board_serdes_map[4].serdes_type = USB3_HOST0;
63 board_serdes_map[4].serdes_speed = SERDES_SPEED_5_GBPS;
64 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
65}
66
Stefan Roese0299c902015-10-20 15:14:47 +020067int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
68{
Baruch Siach5e983842020-01-20 14:20:14 +020069 cf_read_tlv_data();
70
Joel Johnson8a863082020-03-23 14:21:33 -060071 /* Apply build configuration options before runtime configuration */
72 if (IS_ENABLED(CONFIG_CLEARFOG_SFP_25GB))
73 board_serdes_map[5].serdes_speed = SERDES_SPEED_3_125_GBPS;
74
Joel Johnson009d4cf2020-03-23 14:21:34 -060075 if (IS_ENABLED(CONFIG_CLEARFOG_CON2_SATA)) {
76 board_serdes_map[4].serdes_type = SATA2;
77 board_serdes_map[4].serdes_speed = SERDES_SPEED_3_GBPS;
78 board_serdes_map[4].serdes_mode = SERDES_DEFAULT_MODE;
79 board_serdes_map[4].swap_rx = 1;
80 }
81
82 if (IS_ENABLED(CONFIG_CLEARFOG_CON3_SATA)) {
83 board_serdes_map[2].serdes_type = SATA1;
84 board_serdes_map[2].serdes_speed = SERDES_SPEED_3_GBPS;
85 board_serdes_map[2].serdes_mode = SERDES_DEFAULT_MODE;
86 board_serdes_map[2].swap_rx = 1;
87 }
88
Joel Johnson8a863082020-03-23 14:21:33 -060089 /* Apply runtime detection changes */
Baruch Siach5e983842020-01-20 14:20:14 +020090 if (sr_product_is(&cf_tlv_data, "Clearfog GTR")) {
91 board_serdes_map[0].serdes_type = PEX0;
92 board_serdes_map[0].serdes_speed = SERDES_SPEED_5_GBPS;
93 board_serdes_map[0].serdes_mode = PEX_ROOT_COMPLEX_X1;
Joel Johnson9f205d62020-03-23 14:21:32 -060094 } else if (sr_product_is(&cf_tlv_data, "Clearfog Pro")) {
95 /* handle recognized product as noop, no adjustment required */
96 } else if (sr_product_is(&cf_tlv_data, "Clearfog Base")) {
97 config_cfbase_serdes_map();
98 } else {
99 /*
100 * Fallback to static default. EEPROM TLV support is not
101 * enabled, runtime detection failed, hardware support is not
102 * present, EEPROM is corrupt, or an unrecognized product name
103 * is present.
104 */
105 if (IS_ENABLED(CONFIG_SPL_CMD_TLV_EEPROM))
106 puts("EEPROM TLV detection failed: ");
107 puts("Using static config for ");
108 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE)) {
109 puts("Clearfog Base.\n");
110 config_cfbase_serdes_map();
111 } else {
112 puts("Clearfog Pro.\n");
113 }
Baruch Siach584a3d22020-01-20 14:20:15 +0200114 }
115
Stefan Roese0299c902015-10-20 15:14:47 +0200116 *serdes_map_array = board_serdes_map;
117 *count = ARRAY_SIZE(board_serdes_map);
118 return 0;
119}
120
121/*
122 * Define the DDR layout / topology here in the board file. This will
123 * be used by the DDR3 init code in the SPL U-Boot version to configure
124 * the DDR3 controller.
125 */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200126static struct mv_ddr_topology_map board_topology_map = {
127 DEBUG_LEVEL_ERROR,
Stefan Roese0299c902015-10-20 15:14:47 +0200128 0x1, /* active interfaces */
129 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
130 { { { {0x1, 0, 0, 0},
131 {0x1, 0, 0, 0},
132 {0x1, 0, 0, 0},
133 {0x1, 0, 0, 0},
134 {0x1, 0, 0, 0} },
135 SPEED_BIN_DDR_1600K, /* speed_bin */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200136 MV_DDR_DEV_WIDTH_16BIT, /* memory_width */
137 MV_DDR_DIE_CAP_4GBIT, /* mem_size */
Chris Packhamebb1a592018-12-03 14:26:49 +1300138 MV_DDR_FREQ_800, /* frequency */
Chris Packham01c541e2017-11-29 10:38:34 +1300139 0, 0, /* cas_wl cas_l */
Chris Packhame6f61622018-05-10 13:28:30 +1200140 MV_DDR_TEMP_LOW, /* temperature */
141 MV_DDR_TIM_DEFAULT} }, /* timing */
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200142 BUS_MASK_32BIT, /* Busses mask */
143 MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
144 { {0} }, /* raw spd data */
Baruch Siach66646fa2020-01-20 14:20:07 +0200145 {0}, /* timing parameters */
146 { {0} }, /* electrical configuration */
147 {0,}, /* electrical parameters */
148 0x3, /* clock enable mask */
Stefan Roese0299c902015-10-20 15:14:47 +0200149};
150
Chris Packham2b4ffbf2018-05-10 13:28:29 +1200151struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
Stefan Roese0299c902015-10-20 15:14:47 +0200152{
Baruch Siacha2e41ad2020-01-20 14:20:11 +0200153 struct if_params *ifp = &board_topology_map.interface_params[0];
154
155 cf_read_tlv_data();
156
157 switch (cf_tlv_data.ram_size) {
158 case 4:
159 default:
160 ifp->memory_size = MV_DDR_DIE_CAP_4GBIT;
161 break;
162 case 8:
163 ifp->memory_size = MV_DDR_DIE_CAP_8GBIT;
164 break;
165 }
166
Stefan Roese0299c902015-10-20 15:14:47 +0200167 /* Return the board topology as defined in the board code */
168 return &board_topology_map;
169}
170
171int board_early_init_f(void)
172{
173 /* Configure MPP */
174 writel(0x11111111, MVEBU_MPP_BASE + 0x00);
175 writel(0x11111111, MVEBU_MPP_BASE + 0x04);
176 writel(0x10400011, MVEBU_MPP_BASE + 0x08);
177 writel(0x22043333, MVEBU_MPP_BASE + 0x0c);
178 writel(0x44400002, MVEBU_MPP_BASE + 0x10);
179 writel(0x41144004, MVEBU_MPP_BASE + 0x14);
180 writel(0x40333333, MVEBU_MPP_BASE + 0x18);
181 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
182
183 /* Set GPP Out value */
184 writel(BOARD_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
185 writel(BOARD_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
186
187 /* Set GPP Polarity */
188 writel(BOARD_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
189 writel(BOARD_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
190
191 /* Set GPP Out Enable */
192 writel(BOARD_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
193 writel(BOARD_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
194
195 return 0;
196}
197
198int board_init(void)
199{
Stefan Roese0299c902015-10-20 15:14:47 +0200200 /* Address of boot parameters */
201 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
202
203 /* Toggle GPIO41 to reset onboard switch and phy */
204 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
205 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9));
Patrick Wildtfb9765d2017-05-09 13:54:44 +0200206 /* GPIO 19 on ClearFog rev 2.1 controls the uSOM onboard phy reset */
207 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
208 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19));
Stefan Roese0299c902015-10-20 15:14:47 +0200209 mdelay(1);
210 setbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9));
Patrick Wildtfb9765d2017-05-09 13:54:44 +0200211 setbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19));
Stefan Roese0299c902015-10-20 15:14:47 +0200212 mdelay(10);
213
Stefan Roese0299c902015-10-20 15:14:47 +0200214 return 0;
215}
216
217int checkboard(void)
218{
Joel Johnsonee26e852020-03-23 14:21:31 -0600219 char *board = "Clearfog Pro";
Joel Johnson9f205d62020-03-23 14:21:32 -0600220 if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
221 board = "Clearfog Base";
Baruch Siach7211fa62020-01-20 14:20:12 +0200222
223 cf_read_tlv_data();
224 if (strlen(cf_tlv_data.tlv_product_name[0]) > 0)
225 board = cf_tlv_data.tlv_product_name[0];
226
227 printf("Board: SolidRun %s", board);
228 if (strlen(cf_tlv_data.tlv_product_name[1]) > 0)
229 printf(", %s", cf_tlv_data.tlv_product_name[1]);
230 puts("\n");
Stefan Roese0299c902015-10-20 15:14:47 +0200231
232 return 0;
233}
234
235int board_eth_init(bd_t *bis)
236{
237 cpu_eth_init(bis); /* Built in controller(s) come first */
238 return pci_eth_init(bis);
239}
Baruch Siach867572f2020-01-20 14:20:13 +0200240
241int board_late_init(void)
242{
243 cf_read_tlv_data();
244
245 if (sr_product_is(&cf_tlv_data, "Clearfog Base"))
246 env_set("fdtfile", "armada-388-clearfog-base.dtb");
247 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR S4"))
248 env_set("fdtfile", "armada-385-clearfog-gtr-s4.dtb");
249 else if (sr_product_is(&cf_tlv_data, "Clearfog GTR L8"))
250 env_set("fdtfile", "armada-385-clearfog-gtr-l8.dtb");
Joel Johnson9f205d62020-03-23 14:21:32 -0600251 else if (IS_ENABLED(CONFIG_TARGET_CLEARFOG_BASE))
252 env_set("fdtfile", "armada-388-clearfog-base.dtb");
Joel Johnson8eccd0d2020-03-23 14:21:35 -0600253 else
Joel Johnson27f48f72020-03-23 14:21:40 -0600254 env_set("fdtfile", "armada-388-clearfog-pro.dtb");
Baruch Siach867572f2020-01-20 14:20:13 +0200255
256 return 0;
257}