blob: 9fa0b659499b8c21dd6cafa9fd9704c6a1076057 [file] [log] [blame]
Anton Vorontsov42dbd662008-05-28 18:20:15 +04001/*
2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#ifndef __ASM_PPC_FSL_LBC_H
14#define __ASM_PPC_FSL_LBC_H
15
16#include <config.h>
17
18/* BR - Base Registers
19 */
20#define BR0 0x5000 /* Register offset to immr */
21#define BR1 0x5008
22#define BR2 0x5010
23#define BR3 0x5018
24#define BR4 0x5020
25#define BR5 0x5028
26#define BR6 0x5030
27#define BR7 0x5038
28
29#define BR_BA 0xFFFF8000
30#define BR_BA_SHIFT 15
Kumar Galac51fc5d2009-01-23 14:22:13 -060031#define BR_XBA 0x00006000
32#define BR_XBA_SHIFT 13
Anton Vorontsov42dbd662008-05-28 18:20:15 +040033#define BR_PS 0x00001800
34#define BR_PS_SHIFT 11
35#define BR_PS_8 0x00000800 /* Port Size 8 bit */
36#define BR_PS_16 0x00001000 /* Port Size 16 bit */
37#define BR_PS_32 0x00001800 /* Port Size 32 bit */
38#define BR_DECC 0x00000600
39#define BR_DECC_SHIFT 9
40#define BR_DECC_OFF 0x00000000
41#define BR_DECC_CHK 0x00000200
42#define BR_DECC_CHK_GEN 0x00000400
43#define BR_WP 0x00000100
44#define BR_WP_SHIFT 8
45#define BR_MSEL 0x000000E0
46#define BR_MSEL_SHIFT 5
47#define BR_MS_GPCM 0x00000000 /* GPCM */
48#define BR_MS_FCM 0x00000020 /* FCM */
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040049#ifdef CONFIG_MPC83xx
Anton Vorontsov42dbd662008-05-28 18:20:15 +040050#define BR_MS_SDRAM 0x00000060 /* SDRAM */
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040051#elif defined(CONFIG_MPC85xx)
52#define BR_MS_SDRAM 0x00000000 /* SDRAM */
53#endif
Anton Vorontsov42dbd662008-05-28 18:20:15 +040054#define BR_MS_UPMA 0x00000080 /* UPMA */
55#define BR_MS_UPMB 0x000000A0 /* UPMB */
56#define BR_MS_UPMC 0x000000C0 /* UPMC */
57#if !defined(CONFIG_MPC834X)
58#define BR_ATOM 0x0000000C
59#define BR_ATOM_SHIFT 2
60#endif
61#define BR_V 0x00000001
62#define BR_V_SHIFT 0
63
Sergei Poselenov740280e2008-06-06 15:42:40 +020064#define UPMA 0
65#define UPMB 1
66#define UPMC 2
67
Anton Vorontsov42dbd662008-05-28 18:20:15 +040068#if defined(CONFIG_MPC834X)
69#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
70#else
71#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
72#endif
73
Kumar Galaea154a12008-11-24 10:25:14 -060074/* Convert an address into the right format for the BR registers */
Kumar Galac51fc5d2009-01-23 14:22:13 -060075#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
Kumar Galaea154a12008-11-24 10:25:14 -060076#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
77 ((x & 0x300000000ULL) >> 19)))
78#else
79#define BR_PHYS_ADDR(x) (x & 0xffff8000)
80#endif
81
Anton Vorontsov42dbd662008-05-28 18:20:15 +040082/* OR - Option Registers
83 */
84#define OR0 0x5004 /* Register offset to immr */
85#define OR1 0x500C
86#define OR2 0x5014
87#define OR3 0x501C
88#define OR4 0x5024
89#define OR5 0x502C
90#define OR6 0x5034
91#define OR7 0x503C
92
93#define OR_GPCM_AM 0xFFFF8000
94#define OR_GPCM_AM_SHIFT 15
Kumar Galac51fc5d2009-01-23 14:22:13 -060095#define OR_GPCM_XAM 0x00006000
96#define OR_GPCM_XAM_SHIFT 13
Anton Vorontsov42dbd662008-05-28 18:20:15 +040097#define OR_GPCM_BCTLD 0x00001000
98#define OR_GPCM_BCTLD_SHIFT 12
99#define OR_GPCM_CSNT 0x00000800
100#define OR_GPCM_CSNT_SHIFT 11
101#define OR_GPCM_ACS 0x00000600
102#define OR_GPCM_ACS_SHIFT 9
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +0400103#define OR_GPCM_ACS_DIV2 0x00000600
104#define OR_GPCM_ACS_DIV4 0x00000400
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400105#define OR_GPCM_XACS 0x00000100
106#define OR_GPCM_XACS_SHIFT 8
107#define OR_GPCM_SCY 0x000000F0
108#define OR_GPCM_SCY_SHIFT 4
109#define OR_GPCM_SCY_1 0x00000010
110#define OR_GPCM_SCY_2 0x00000020
111#define OR_GPCM_SCY_3 0x00000030
112#define OR_GPCM_SCY_4 0x00000040
113#define OR_GPCM_SCY_5 0x00000050
114#define OR_GPCM_SCY_6 0x00000060
115#define OR_GPCM_SCY_7 0x00000070
116#define OR_GPCM_SCY_8 0x00000080
117#define OR_GPCM_SCY_9 0x00000090
118#define OR_GPCM_SCY_10 0x000000a0
119#define OR_GPCM_SCY_11 0x000000b0
120#define OR_GPCM_SCY_12 0x000000c0
121#define OR_GPCM_SCY_13 0x000000d0
122#define OR_GPCM_SCY_14 0x000000e0
123#define OR_GPCM_SCY_15 0x000000f0
124#define OR_GPCM_SETA 0x00000008
125#define OR_GPCM_SETA_SHIFT 3
126#define OR_GPCM_TRLX 0x00000004
127#define OR_GPCM_TRLX_SHIFT 2
128#define OR_GPCM_EHTR 0x00000002
129#define OR_GPCM_EHTR_SHIFT 1
130#define OR_GPCM_EAD 0x00000001
131#define OR_GPCM_EAD_SHIFT 0
132
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +0400133/* helpers to convert values into an OR address mask (GPCM mode) */
134#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
135#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
136
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400137#define OR_FCM_AM 0xFFFF8000
138#define OR_FCM_AM_SHIFT 15
Kumar Galac51fc5d2009-01-23 14:22:13 -0600139#define OR_FCM_XAM 0x00006000
140#define OR_FCM_XAM_SHIFT 13
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400141#define OR_FCM_BCTLD 0x00001000
142#define OR_FCM_BCTLD_SHIFT 12
143#define OR_FCM_PGS 0x00000400
144#define OR_FCM_PGS_SHIFT 10
145#define OR_FCM_CSCT 0x00000200
146#define OR_FCM_CSCT_SHIFT 9
147#define OR_FCM_CST 0x00000100
148#define OR_FCM_CST_SHIFT 8
149#define OR_FCM_CHT 0x00000080
150#define OR_FCM_CHT_SHIFT 7
151#define OR_FCM_SCY 0x00000070
152#define OR_FCM_SCY_SHIFT 4
153#define OR_FCM_SCY_1 0x00000010
154#define OR_FCM_SCY_2 0x00000020
155#define OR_FCM_SCY_3 0x00000030
156#define OR_FCM_SCY_4 0x00000040
157#define OR_FCM_SCY_5 0x00000050
158#define OR_FCM_SCY_6 0x00000060
159#define OR_FCM_SCY_7 0x00000070
160#define OR_FCM_RST 0x00000008
161#define OR_FCM_RST_SHIFT 3
162#define OR_FCM_TRLX 0x00000004
163#define OR_FCM_TRLX_SHIFT 2
164#define OR_FCM_EHTR 0x00000002
165#define OR_FCM_EHTR_SHIFT 1
166
167#define OR_UPM_AM 0xFFFF8000
168#define OR_UPM_AM_SHIFT 15
169#define OR_UPM_XAM 0x00006000
170#define OR_UPM_XAM_SHIFT 13
171#define OR_UPM_BCTLD 0x00001000
172#define OR_UPM_BCTLD_SHIFT 12
173#define OR_UPM_BI 0x00000100
174#define OR_UPM_BI_SHIFT 8
175#define OR_UPM_TRLX 0x00000004
176#define OR_UPM_TRLX_SHIFT 2
177#define OR_UPM_EHTR 0x00000002
178#define OR_UPM_EHTR_SHIFT 1
179#define OR_UPM_EAD 0x00000001
180#define OR_UPM_EAD_SHIFT 0
181
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400182#define OR_SDRAM_AM 0xFFFF8000
183#define OR_SDRAM_AM_SHIFT 15
184#define OR_SDRAM_XAM 0x00006000
185#define OR_SDRAM_XAM_SHIFT 13
186#define OR_SDRAM_COLS 0x00001C00
187#define OR_SDRAM_COLS_SHIFT 10
188#define OR_SDRAM_ROWS 0x000001C0
189#define OR_SDRAM_ROWS_SHIFT 6
190#define OR_SDRAM_PMSEL 0x00000020
191#define OR_SDRAM_PMSEL_SHIFT 5
192#define OR_SDRAM_EAD 0x00000001
193#define OR_SDRAM_EAD_SHIFT 0
194
195#define OR_AM_32KB 0xFFFF8000
196#define OR_AM_64KB 0xFFFF0000
197#define OR_AM_128KB 0xFFFE0000
198#define OR_AM_256KB 0xFFFC0000
199#define OR_AM_512KB 0xFFF80000
200#define OR_AM_1MB 0xFFF00000
201#define OR_AM_2MB 0xFFE00000
202#define OR_AM_4MB 0xFFC00000
203#define OR_AM_8MB 0xFF800000
204#define OR_AM_16MB 0xFF000000
205#define OR_AM_32MB 0xFE000000
206#define OR_AM_64MB 0xFC000000
207#define OR_AM_128MB 0xF8000000
208#define OR_AM_256MB 0xF0000000
209#define OR_AM_512MB 0xE0000000
210#define OR_AM_1GB 0xC0000000
211#define OR_AM_2GB 0x80000000
212#define OR_AM_4GB 0x00000000
213
Wolfgang Grandegger6fab2fe2008-06-02 12:09:30 +0200214/* MxMR - UPM Machine A/B/C Mode Registers
215 */
216#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
217#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
218#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
219#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
220#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
221#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
222#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
223#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
224#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
225#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
226#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
227#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
228#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
229#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
230#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
231#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
232#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
233#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
234#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
235#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
236#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
237#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
238#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
239#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
240#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
241#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
242#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
243#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
244#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
245#define MxMR_OP_WARR 0x10000000 /* Write to Array */
246#define MxMR_OP_RARR 0x20000000 /* Read from Array */
247#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
248#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
249#define MxMR_RFEN 0x40000000 /* Refresh Enable */
250#define MxMR_BSEL 0x80000000 /* Bus Select */
251
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400252#define LBLAWAR_EN 0x80000000
253#define LBLAWAR_4KB 0x0000000B
254#define LBLAWAR_8KB 0x0000000C
255#define LBLAWAR_16KB 0x0000000D
256#define LBLAWAR_32KB 0x0000000E
257#define LBLAWAR_64KB 0x0000000F
258#define LBLAWAR_128KB 0x00000010
259#define LBLAWAR_256KB 0x00000011
260#define LBLAWAR_512KB 0x00000012
261#define LBLAWAR_1MB 0x00000013
262#define LBLAWAR_2MB 0x00000014
263#define LBLAWAR_4MB 0x00000015
264#define LBLAWAR_8MB 0x00000016
265#define LBLAWAR_16MB 0x00000017
266#define LBLAWAR_32MB 0x00000018
267#define LBLAWAR_64MB 0x00000019
268#define LBLAWAR_128MB 0x0000001A
269#define LBLAWAR_256MB 0x0000001B
270#define LBLAWAR_512MB 0x0000001C
271#define LBLAWAR_1GB 0x0000001D
272#define LBLAWAR_2GB 0x0000001E
273
274/* LBCR - Local Bus Configuration Register
275 */
276#define LBCR_LDIS 0x80000000
277#define LBCR_LDIS_SHIFT 31
278#define LBCR_BCTLC 0x00C00000
279#define LBCR_BCTLC_SHIFT 22
280#define LBCR_LPBSE 0x00020000
281#define LBCR_LPBSE_SHIFT 17
282#define LBCR_EPAR 0x00010000
283#define LBCR_EPAR_SHIFT 16
284#define LBCR_BMT 0x0000FF00
285#define LBCR_BMT_SHIFT 8
286
287/* LCRR - Clock Ratio Register
288 */
289#define LCRR_DBYP 0x80000000
290#define LCRR_DBYP_SHIFT 31
291#define LCRR_BUFCMDC 0x30000000
292#define LCRR_BUFCMDC_SHIFT 28
293#define LCRR_BUFCMDC_1 0x10000000
294#define LCRR_BUFCMDC_2 0x20000000
295#define LCRR_BUFCMDC_3 0x30000000
296#define LCRR_BUFCMDC_4 0x00000000
297#define LCRR_ECL 0x03000000
298#define LCRR_ECL_SHIFT 24
299#define LCRR_ECL_4 0x00000000
300#define LCRR_ECL_5 0x01000000
301#define LCRR_ECL_6 0x02000000
302#define LCRR_ECL_7 0x03000000
303#define LCRR_EADC 0x00030000
304#define LCRR_EADC_SHIFT 16
305#define LCRR_EADC_1 0x00010000
306#define LCRR_EADC_2 0x00020000
307#define LCRR_EADC_3 0x00030000
308#define LCRR_EADC_4 0x00000000
Trent Piephoa5d212a2008-12-03 15:16:34 -0800309/* CLKDIV is five bits only on 8536, 8572, and 8610, so far, but the fifth bit
310 * should always be zero on older parts that have a four bit CLKDIV.
311 */
312#define LCRR_CLKDIV 0x0000001F
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400313#define LCRR_CLKDIV_SHIFT 0
314#define LCRR_CLKDIV_2 0x00000002
315#define LCRR_CLKDIV_4 0x00000004
316#define LCRR_CLKDIV_8 0x00000008
317
Stefan Roesef2302d42008-08-06 14:05:38 +0200318/* LTEDR - Transfer Error Check Disable Register
319 */
320#define LTEDR_BMD 0x80000000 /* Bus monitor disable */
321#define LTEDR_PARD 0x20000000 /* Parity error checking disabled */
322#define LTEDR_WPD 0x04000000 /* Write protect error checking diable */
323#define LTEDR_WARA 0x00800000 /* Write-after-read-atomic error checking diable */
324#define LTEDR_RAWA 0x00400000 /* Read-after-write-atomic error checking disable */
325#define LTEDR_CSD 0x00080000 /* Chip select error checking disable */
326
Haiying Wang4e190b02008-10-29 11:05:55 -0400327/* FMR - Flash Mode Register
328 */
329#define FMR_CWTO 0x0000F000
330#define FMR_CWTO_SHIFT 12
331#define FMR_BOOT 0x00000800
332#define FMR_ECCM 0x00000100
333#define FMR_AL 0x00000030
334#define FMR_AL_SHIFT 4
335#define FMR_OP 0x00000003
336#define FMR_OP_SHIFT 0
337
338/* FIR - Flash Instruction Register
339 */
340#define FIR_OP0 0xF0000000
341#define FIR_OP0_SHIFT 28
342#define FIR_OP1 0x0F000000
343#define FIR_OP1_SHIFT 24
344#define FIR_OP2 0x00F00000
345#define FIR_OP2_SHIFT 20
346#define FIR_OP3 0x000F0000
347#define FIR_OP3_SHIFT 16
348#define FIR_OP4 0x0000F000
349#define FIR_OP4_SHIFT 12
350#define FIR_OP5 0x00000F00
351#define FIR_OP5_SHIFT 8
352#define FIR_OP6 0x000000F0
353#define FIR_OP6_SHIFT 4
354#define FIR_OP7 0x0000000F
355#define FIR_OP7_SHIFT 0
356#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
357#define FIR_OP_CA 0x1 /* Issue current column address */
358#define FIR_OP_PA 0x2 /* Issue current block+page address */
359#define FIR_OP_UA 0x3 /* Issue user defined address */
360#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
361#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
362#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
363#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
364#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
365#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
366#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
367#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
368#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
369#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
370#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
371#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */
372
373/* FCR - Flash Command Register
374 */
375#define FCR_CMD0 0xFF000000
376#define FCR_CMD0_SHIFT 24
377#define FCR_CMD1 0x00FF0000
378#define FCR_CMD1_SHIFT 16
379#define FCR_CMD2 0x0000FF00
380#define FCR_CMD2_SHIFT 8
381#define FCR_CMD3 0x000000FF
382#define FCR_CMD3_SHIFT 0
383/* FBAR - Flash Block Address Register
384 */
385#define FBAR_BLK 0x00FFFFFF
386
387/* FPAR - Flash Page Address Register
388 */
389#define FPAR_SP_PI 0x00007C00
390#define FPAR_SP_PI_SHIFT 10
391#define FPAR_SP_MS 0x00000200
392#define FPAR_SP_CI 0x000001FF
393#define FPAR_SP_CI_SHIFT 0
394#define FPAR_LP_PI 0x0003F000
395#define FPAR_LP_PI_SHIFT 12
396#define FPAR_LP_MS 0x00000800
397#define FPAR_LP_CI 0x000007FF
398#define FPAR_LP_CI_SHIFT 0
399
400/* LTESR - Transfer Error Status Register
401 */
402#define LTESR_BM 0x80000000
403#define LTESR_FCT 0x40000000
404#define LTESR_PAR 0x20000000
405#define LTESR_WP 0x04000000
406#define LTESR_ATMW 0x00800000
407#define LTESR_ATMR 0x00400000
408#define LTESR_CS 0x00080000
409#define LTESR_CC 0x00000001
410
411#ifndef __ASSEMBLY__
412/*
413 * Local Bus Controller Registers.
414 */
415typedef struct lbus_bank {
416 u32 br; /* Base Register */
417 u32 or; /* Option Register */
418} lbus_bank_t;
419
420typedef struct fsl_lbus {
421 lbus_bank_t bank[8];
422 u8 res0[0x28];
423 u32 mar; /* UPM Address Register */
424 u8 res1[0x4];
425 u32 mamr; /* UPMA Mode Register */
426 u32 mbmr; /* UPMB Mode Register */
427 u32 mcmr; /* UPMC Mode Register */
428 u8 res2[0x8];
429 u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
430 u32 mdr; /* UPM Data Register */
431 u8 res3[0x4];
432 u32 lsor; /* Special Operation Initiation Register */
433 u32 lsdmr; /* SDRAM Mode Register */
434 u8 res4[0x8];
435 u32 lurt; /* UPM Refresh Timer */
436 u32 lsrt; /* SDRAM Refresh Timer */
437 u8 res5[0x8];
438 u32 ltesr; /* Transfer Error Status Register */
439 u32 ltedr; /* Transfer Error Disable Register */
440 u32 lteir; /* Transfer Error Interrupt Register */
441 u32 lteatr; /* Transfer Error Attributes Register */
442 u32 ltear; /* Transfer Error Address Register */
443 u8 res6[0xC];
444 u32 lbcr; /* Configuration Register */
445 u32 lcrr; /* Clock Ratio Register */
446 u8 res7[0x8];
447 u32 fmr; /* Flash Mode Register */
448 u32 fir; /* Flash Instruction Register */
449 u32 fcr; /* Flash Command Register */
450 u32 fbar; /* Flash Block Addr Register */
451 u32 fpar; /* Flash Page Addr Register */
452 u32 fbcr; /* Flash Byte Count Register */
453 u8 res8[0xF08];
454} fsl_lbus_t;
455#endif /* __ASSEMBLY__ */
456
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400457#endif /* __ASM_PPC_FSL_LBC_H */