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Anton Vorontsov42dbd662008-05-28 18:20:15 +04001/*
2 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 */
12
13#ifndef __ASM_PPC_FSL_LBC_H
14#define __ASM_PPC_FSL_LBC_H
15
16#include <config.h>
17
18/* BR - Base Registers
19 */
20#define BR0 0x5000 /* Register offset to immr */
21#define BR1 0x5008
22#define BR2 0x5010
23#define BR3 0x5018
24#define BR4 0x5020
25#define BR5 0x5028
26#define BR6 0x5030
27#define BR7 0x5038
28
29#define BR_BA 0xFFFF8000
30#define BR_BA_SHIFT 15
31#define BR_PS 0x00001800
32#define BR_PS_SHIFT 11
33#define BR_PS_8 0x00000800 /* Port Size 8 bit */
34#define BR_PS_16 0x00001000 /* Port Size 16 bit */
35#define BR_PS_32 0x00001800 /* Port Size 32 bit */
36#define BR_DECC 0x00000600
37#define BR_DECC_SHIFT 9
38#define BR_DECC_OFF 0x00000000
39#define BR_DECC_CHK 0x00000200
40#define BR_DECC_CHK_GEN 0x00000400
41#define BR_WP 0x00000100
42#define BR_WP_SHIFT 8
43#define BR_MSEL 0x000000E0
44#define BR_MSEL_SHIFT 5
45#define BR_MS_GPCM 0x00000000 /* GPCM */
46#define BR_MS_FCM 0x00000020 /* FCM */
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040047#ifdef CONFIG_MPC83xx
Anton Vorontsov42dbd662008-05-28 18:20:15 +040048#define BR_MS_SDRAM 0x00000060 /* SDRAM */
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040049#elif defined(CONFIG_MPC85xx)
50#define BR_MS_SDRAM 0x00000000 /* SDRAM */
51#endif
Anton Vorontsov42dbd662008-05-28 18:20:15 +040052#define BR_MS_UPMA 0x00000080 /* UPMA */
53#define BR_MS_UPMB 0x000000A0 /* UPMB */
54#define BR_MS_UPMC 0x000000C0 /* UPMC */
55#if !defined(CONFIG_MPC834X)
56#define BR_ATOM 0x0000000C
57#define BR_ATOM_SHIFT 2
58#endif
59#define BR_V 0x00000001
60#define BR_V_SHIFT 0
61
Sergei Poselenov740280e2008-06-06 15:42:40 +020062#define UPMA 0
63#define UPMB 1
64#define UPMC 2
65
Anton Vorontsov42dbd662008-05-28 18:20:15 +040066#if defined(CONFIG_MPC834X)
67#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
68#else
69#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
70#endif
71
72/* OR - Option Registers
73 */
74#define OR0 0x5004 /* Register offset to immr */
75#define OR1 0x500C
76#define OR2 0x5014
77#define OR3 0x501C
78#define OR4 0x5024
79#define OR5 0x502C
80#define OR6 0x5034
81#define OR7 0x503C
82
83#define OR_GPCM_AM 0xFFFF8000
84#define OR_GPCM_AM_SHIFT 15
85#define OR_GPCM_BCTLD 0x00001000
86#define OR_GPCM_BCTLD_SHIFT 12
87#define OR_GPCM_CSNT 0x00000800
88#define OR_GPCM_CSNT_SHIFT 11
89#define OR_GPCM_ACS 0x00000600
90#define OR_GPCM_ACS_SHIFT 9
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +040091#define OR_GPCM_ACS_DIV2 0x00000600
92#define OR_GPCM_ACS_DIV4 0x00000400
Anton Vorontsov42dbd662008-05-28 18:20:15 +040093#define OR_GPCM_XACS 0x00000100
94#define OR_GPCM_XACS_SHIFT 8
95#define OR_GPCM_SCY 0x000000F0
96#define OR_GPCM_SCY_SHIFT 4
97#define OR_GPCM_SCY_1 0x00000010
98#define OR_GPCM_SCY_2 0x00000020
99#define OR_GPCM_SCY_3 0x00000030
100#define OR_GPCM_SCY_4 0x00000040
101#define OR_GPCM_SCY_5 0x00000050
102#define OR_GPCM_SCY_6 0x00000060
103#define OR_GPCM_SCY_7 0x00000070
104#define OR_GPCM_SCY_8 0x00000080
105#define OR_GPCM_SCY_9 0x00000090
106#define OR_GPCM_SCY_10 0x000000a0
107#define OR_GPCM_SCY_11 0x000000b0
108#define OR_GPCM_SCY_12 0x000000c0
109#define OR_GPCM_SCY_13 0x000000d0
110#define OR_GPCM_SCY_14 0x000000e0
111#define OR_GPCM_SCY_15 0x000000f0
112#define OR_GPCM_SETA 0x00000008
113#define OR_GPCM_SETA_SHIFT 3
114#define OR_GPCM_TRLX 0x00000004
115#define OR_GPCM_TRLX_SHIFT 2
116#define OR_GPCM_EHTR 0x00000002
117#define OR_GPCM_EHTR_SHIFT 1
118#define OR_GPCM_EAD 0x00000001
119#define OR_GPCM_EAD_SHIFT 0
120
Anton Vorontsovc8c5fc22008-05-29 18:14:56 +0400121/* helpers to convert values into an OR address mask (GPCM mode) */
122#define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
123#define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)
124
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400125#define OR_FCM_AM 0xFFFF8000
126#define OR_FCM_AM_SHIFT 15
127#define OR_FCM_BCTLD 0x00001000
128#define OR_FCM_BCTLD_SHIFT 12
129#define OR_FCM_PGS 0x00000400
130#define OR_FCM_PGS_SHIFT 10
131#define OR_FCM_CSCT 0x00000200
132#define OR_FCM_CSCT_SHIFT 9
133#define OR_FCM_CST 0x00000100
134#define OR_FCM_CST_SHIFT 8
135#define OR_FCM_CHT 0x00000080
136#define OR_FCM_CHT_SHIFT 7
137#define OR_FCM_SCY 0x00000070
138#define OR_FCM_SCY_SHIFT 4
139#define OR_FCM_SCY_1 0x00000010
140#define OR_FCM_SCY_2 0x00000020
141#define OR_FCM_SCY_3 0x00000030
142#define OR_FCM_SCY_4 0x00000040
143#define OR_FCM_SCY_5 0x00000050
144#define OR_FCM_SCY_6 0x00000060
145#define OR_FCM_SCY_7 0x00000070
146#define OR_FCM_RST 0x00000008
147#define OR_FCM_RST_SHIFT 3
148#define OR_FCM_TRLX 0x00000004
149#define OR_FCM_TRLX_SHIFT 2
150#define OR_FCM_EHTR 0x00000002
151#define OR_FCM_EHTR_SHIFT 1
152
153#define OR_UPM_AM 0xFFFF8000
154#define OR_UPM_AM_SHIFT 15
155#define OR_UPM_XAM 0x00006000
156#define OR_UPM_XAM_SHIFT 13
157#define OR_UPM_BCTLD 0x00001000
158#define OR_UPM_BCTLD_SHIFT 12
159#define OR_UPM_BI 0x00000100
160#define OR_UPM_BI_SHIFT 8
161#define OR_UPM_TRLX 0x00000004
162#define OR_UPM_TRLX_SHIFT 2
163#define OR_UPM_EHTR 0x00000002
164#define OR_UPM_EHTR_SHIFT 1
165#define OR_UPM_EAD 0x00000001
166#define OR_UPM_EAD_SHIFT 0
167
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400168#define OR_SDRAM_AM 0xFFFF8000
169#define OR_SDRAM_AM_SHIFT 15
170#define OR_SDRAM_XAM 0x00006000
171#define OR_SDRAM_XAM_SHIFT 13
172#define OR_SDRAM_COLS 0x00001C00
173#define OR_SDRAM_COLS_SHIFT 10
174#define OR_SDRAM_ROWS 0x000001C0
175#define OR_SDRAM_ROWS_SHIFT 6
176#define OR_SDRAM_PMSEL 0x00000020
177#define OR_SDRAM_PMSEL_SHIFT 5
178#define OR_SDRAM_EAD 0x00000001
179#define OR_SDRAM_EAD_SHIFT 0
180
181#define OR_AM_32KB 0xFFFF8000
182#define OR_AM_64KB 0xFFFF0000
183#define OR_AM_128KB 0xFFFE0000
184#define OR_AM_256KB 0xFFFC0000
185#define OR_AM_512KB 0xFFF80000
186#define OR_AM_1MB 0xFFF00000
187#define OR_AM_2MB 0xFFE00000
188#define OR_AM_4MB 0xFFC00000
189#define OR_AM_8MB 0xFF800000
190#define OR_AM_16MB 0xFF000000
191#define OR_AM_32MB 0xFE000000
192#define OR_AM_64MB 0xFC000000
193#define OR_AM_128MB 0xF8000000
194#define OR_AM_256MB 0xF0000000
195#define OR_AM_512MB 0xE0000000
196#define OR_AM_1GB 0xC0000000
197#define OR_AM_2GB 0x80000000
198#define OR_AM_4GB 0x00000000
199
Wolfgang Grandegger6fab2fe2008-06-02 12:09:30 +0200200/* MxMR - UPM Machine A/B/C Mode Registers
201 */
202#define MxMR_MAD_MSK 0x0000003f /* Machine Address Mask */
203#define MxMR_TLFx_MSK 0x000003c0 /* Refresh Loop Field Mask */
204#define MxMR_WLFx_MSK 0x00003c00 /* Write Loop Field Mask */
205#define MxMR_WLFx_1X 0x00000400 /* executed 1 time */
206#define MxMR_WLFx_2X 0x00000800 /* executed 2 times */
207#define MxMR_WLFx_3X 0x00000c00 /* executed 3 times */
208#define MxMR_WLFx_4X 0x00001000 /* executed 4 times */
209#define MxMR_WLFx_5X 0x00001400 /* executed 5 times */
210#define MxMR_WLFx_6X 0x00001800 /* executed 6 times */
211#define MxMR_WLFx_7X 0x00001c00 /* executed 7 times */
212#define MxMR_WLFx_8X 0x00002000 /* executed 8 times */
213#define MxMR_WLFx_9X 0x00002400 /* executed 9 times */
214#define MxMR_WLFx_10X 0x00002800 /* executed 10 times */
215#define MxMR_WLFx_11X 0x00002c00 /* executed 11 times */
216#define MxMR_WLFx_12X 0x00003000 /* executed 12 times */
217#define MxMR_WLFx_13X 0x00003400 /* executed 13 times */
218#define MxMR_WLFx_14X 0x00003800 /* executed 14 times */
219#define MxMR_WLFx_15X 0x00003c00 /* executed 15 times */
220#define MxMR_WLFx_16X 0x00000000 /* executed 16 times */
221#define MxMR_RLFx_MSK 0x0003c000 /* Read Loop Field Mask */
222#define MxMR_GPL_x4DIS 0x00040000 /* GPL_A4 Ouput Line Disable */
223#define MxMR_G0CLx_MSK 0x00380000 /* General Line 0 Control Mask */
224#define MxMR_DSx_1_CYCL 0x00000000 /* 1 cycle Disable Period */
225#define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */
226#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */
227#define MxMR_DSx_4_CYCL 0x00c00000 /* 4 cycle Disable Period */
228#define MxMR_DSx_MSK 0x00c00000 /* Disable Timer Period Mask */
229#define MxMR_AMx_MSK 0x07000000 /* Addess Multiplex Size Mask */
230#define MxMR_OP_NORM 0x00000000 /* Normal Operation */
231#define MxMR_OP_WARR 0x10000000 /* Write to Array */
232#define MxMR_OP_RARR 0x20000000 /* Read from Array */
233#define MxMR_OP_RUNP 0x30000000 /* Run Pattern */
234#define MxMR_OP_MSK 0x30000000 /* Command Opcode Mask */
235#define MxMR_RFEN 0x40000000 /* Refresh Enable */
236#define MxMR_BSEL 0x80000000 /* Bus Select */
237
Anton Vorontsov42dbd662008-05-28 18:20:15 +0400238#define LBLAWAR_EN 0x80000000
239#define LBLAWAR_4KB 0x0000000B
240#define LBLAWAR_8KB 0x0000000C
241#define LBLAWAR_16KB 0x0000000D
242#define LBLAWAR_32KB 0x0000000E
243#define LBLAWAR_64KB 0x0000000F
244#define LBLAWAR_128KB 0x00000010
245#define LBLAWAR_256KB 0x00000011
246#define LBLAWAR_512KB 0x00000012
247#define LBLAWAR_1MB 0x00000013
248#define LBLAWAR_2MB 0x00000014
249#define LBLAWAR_4MB 0x00000015
250#define LBLAWAR_8MB 0x00000016
251#define LBLAWAR_16MB 0x00000017
252#define LBLAWAR_32MB 0x00000018
253#define LBLAWAR_64MB 0x00000019
254#define LBLAWAR_128MB 0x0000001A
255#define LBLAWAR_256MB 0x0000001B
256#define LBLAWAR_512MB 0x0000001C
257#define LBLAWAR_1GB 0x0000001D
258#define LBLAWAR_2GB 0x0000001E
259
260/* LBCR - Local Bus Configuration Register
261 */
262#define LBCR_LDIS 0x80000000
263#define LBCR_LDIS_SHIFT 31
264#define LBCR_BCTLC 0x00C00000
265#define LBCR_BCTLC_SHIFT 22
266#define LBCR_LPBSE 0x00020000
267#define LBCR_LPBSE_SHIFT 17
268#define LBCR_EPAR 0x00010000
269#define LBCR_EPAR_SHIFT 16
270#define LBCR_BMT 0x0000FF00
271#define LBCR_BMT_SHIFT 8
272
273/* LCRR - Clock Ratio Register
274 */
275#define LCRR_DBYP 0x80000000
276#define LCRR_DBYP_SHIFT 31
277#define LCRR_BUFCMDC 0x30000000
278#define LCRR_BUFCMDC_SHIFT 28
279#define LCRR_BUFCMDC_1 0x10000000
280#define LCRR_BUFCMDC_2 0x20000000
281#define LCRR_BUFCMDC_3 0x30000000
282#define LCRR_BUFCMDC_4 0x00000000
283#define LCRR_ECL 0x03000000
284#define LCRR_ECL_SHIFT 24
285#define LCRR_ECL_4 0x00000000
286#define LCRR_ECL_5 0x01000000
287#define LCRR_ECL_6 0x02000000
288#define LCRR_ECL_7 0x03000000
289#define LCRR_EADC 0x00030000
290#define LCRR_EADC_SHIFT 16
291#define LCRR_EADC_1 0x00010000
292#define LCRR_EADC_2 0x00020000
293#define LCRR_EADC_3 0x00030000
294#define LCRR_EADC_4 0x00000000
295#define LCRR_CLKDIV 0x0000000F
296#define LCRR_CLKDIV_SHIFT 0
297#define LCRR_CLKDIV_2 0x00000002
298#define LCRR_CLKDIV_4 0x00000004
299#define LCRR_CLKDIV_8 0x00000008
300
301#endif /* __ASM_PPC_FSL_LBC_H */