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Stelian Pop2118ebb2008-05-08 18:52:25 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop2118ebb2008-05-08 18:52:25 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop2118ebb2008-05-08 18:52:25 +02007 */
8
9#include <common.h>
Xu, Hong21d671d2011-08-01 03:56:53 +000010#include <asm/io.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020011#include <asm/arch/at91sam9rl.h>
12#include <asm/arch/at91sam9rl_matrix.h>
13#include <asm/arch/at91sam9_smc.h>
Jean-Christophe PLAGNIOL-VILLARD1332a2a2009-03-21 21:07:59 +010014#include <asm/arch/at91_common.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020015#include <asm/arch/at91_pmc.h>
16#include <asm/arch/at91_rstc.h>
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020017#include <asm/arch/clk.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020018#include <asm/arch/gpio.h>
Xu, Hong21d671d2011-08-01 03:56:53 +000019
Stelian Pop761c70b2008-05-08 14:52:32 +020020#include <lcd.h>
21#include <atmel_lcdc.h>
Stelian Pop2118ebb2008-05-08 18:52:25 +020022#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
23#include <net.h>
24#endif
25
26DECLARE_GLOBAL_DATA_PTR;
27
28/* ------------------------------------------------------------------------- */
29/*
30 * Miscelaneous platform dependent initialisations
31 */
32
Stelian Pop2118ebb2008-05-08 18:52:25 +020033#ifdef CONFIG_CMD_NAND
34static void at91sam9rlek_nand_hw_init(void)
35{
Xu, Hong21d671d2011-08-01 03:56:53 +000036 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
37 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
38 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
Stelian Pop2118ebb2008-05-08 18:52:25 +020039 unsigned long csa;
40
41 /* Enable CS3 */
Xu, Hong21d671d2011-08-01 03:56:53 +000042 csa = readl(&matrix->ebicsa);
43 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
44
45 writel(csa, &matrix->ebicsa);
Stelian Pop2118ebb2008-05-08 18:52:25 +020046
47 /* Configure SMC CS3 for NAND/SmartMedia */
Xu, Hong21d671d2011-08-01 03:56:53 +000048 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
49 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
50 &smc->cs[3].setup);
51 writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
52 AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
53 &smc->cs[3].pulse);
54 writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
55 &smc->cs[3].cycle);
56 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
57 AT91_SMC_MODE_EXNW_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058#ifdef CONFIG_SYS_NAND_DBW_16
Xu, Hong21d671d2011-08-01 03:56:53 +000059 AT91_SMC_MODE_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#else /* CONFIG_SYS_NAND_DBW_8 */
Xu, Hong21d671d2011-08-01 03:56:53 +000061 AT91_SMC_MODE_DBW_8 |
Stelian Pop2118ebb2008-05-08 18:52:25 +020062#endif
Xu, Hong21d671d2011-08-01 03:56:53 +000063 AT91_SMC_MODE_TDF_CYCLE(2),
64 &smc->cs[3].mode);
Stelian Pop2118ebb2008-05-08 18:52:25 +020065
Xu, Hong21d671d2011-08-01 03:56:53 +000066 writel(1 << ATMEL_ID_PIOD, &pmc->pcer);
Stelian Pop2118ebb2008-05-08 18:52:25 +020067
68 /* Configure RDY/BSY */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010069 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
Stelian Pop2118ebb2008-05-08 18:52:25 +020070
71 /* Enable NandFlash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +010072 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
Stelian Pop2118ebb2008-05-08 18:52:25 +020073
74 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
75 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
76}
77#endif
78
Stelian Pop761c70b2008-05-08 14:52:32 +020079#ifdef CONFIG_LCD
80vidinfo_t panel_info = {
Jeroen Hofsteec346e462014-06-10 00:16:23 +020081 .vl_col = 240,
82 .vl_row = 320,
83 .vl_clk = 4965000,
84 .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
85 ATMEL_LCDC_INVFRAME_INVERTED,
86 .vl_bpix = 3,
87 .vl_tft = 1,
88 .vl_hsync_len = 5,
89 .vl_left_margin = 1,
90 .vl_right_margin = 33,
91 .vl_vsync_len = 1,
92 .vl_upper_margin = 1,
93 .vl_lower_margin = 0,
94 .mmio = ATMEL_BASE_LCDC,
Stelian Pop761c70b2008-05-08 14:52:32 +020095};
96
97void lcd_enable(void)
98{
99 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
100}
101
102void lcd_disable(void)
103{
104 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
105}
106static void at91sam9rlek_lcd_hw_init(void)
107{
Xu, Hong21d671d2011-08-01 03:56:53 +0000108 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
109
Stelian Pop761c70b2008-05-08 14:52:32 +0200110 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
111 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
112 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
113 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
114 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
115 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
116 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
117 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
118 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
119 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
120 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
121 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
122 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
123 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
124 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
125 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
126 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
127 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
128 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
129 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
130 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
131
Xu, Hong21d671d2011-08-01 03:56:53 +0000132 writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
Stelian Pop761c70b2008-05-08 14:52:32 +0200133}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200134
135#ifdef CONFIG_LCD_INFO
136#include <nand.h>
137#include <version.h>
138
139void lcd_show_board_info(void)
140{
141 ulong dram_size, nand_size;
142 int i;
143 char temp[32];
144
145 lcd_printf ("%s\n", U_BOOT_VERSION);
146 lcd_printf ("(C) 2008 ATMEL Corp\n");
147 lcd_printf ("at91support@atmel.com\n");
148 lcd_printf ("%s CPU at %s MHz\n",
Xu, Hong21d671d2011-08-01 03:56:53 +0000149 ATMEL_CPU_NAME,
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +0200150 strmhz(temp, get_cpu_clk_rate()));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200151
152 dram_size = 0;
153 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
154 dram_size += gd->bd->bi_dram[i].size;
155 nand_size = 0;
156 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
157 nand_size += nand_info[i].size;
158 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
159 dram_size >> 20,
160 nand_size >> 20 );
161}
162#endif /* CONFIG_LCD_INFO */
Stelian Pop761c70b2008-05-08 14:52:32 +0200163#endif
164
Xu, Hong21d671d2011-08-01 03:56:53 +0000165int board_early_init_f(void)
166{
167 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
168
169 /* Enable clocks for all PIOs */
170 writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) |
171 (1 << ATMEL_ID_PIOC) | (1 << ATMEL_ID_PIOD),
172 &pmc->pcer);
173
174 return 0;
175}
Stelian Pop761c70b2008-05-08 14:52:32 +0200176
Stelian Pop2118ebb2008-05-08 18:52:25 +0200177int board_init(void)
178{
Stelian Pop2118ebb2008-05-08 18:52:25 +0200179 /* arch number of AT91SAM9RLEK-Board */
180 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9RLEK;
181 /* adress of boot parameters */
Xu, Hong21d671d2011-08-01 03:56:53 +0000182 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
Stelian Pop2118ebb2008-05-08 18:52:25 +0200183
Xu, Hong21d671d2011-08-01 03:56:53 +0000184 at91_seriald_hw_init();
Stelian Pop2118ebb2008-05-08 18:52:25 +0200185#ifdef CONFIG_CMD_NAND
186 at91sam9rlek_nand_hw_init();
187#endif
188#ifdef CONFIG_HAS_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD7ebafb72009-03-21 21:07:59 +0100189 at91_spi0_hw_init(1 << 0);
Stelian Pop2118ebb2008-05-08 18:52:25 +0200190#endif
Stelian Pop761c70b2008-05-08 14:52:32 +0200191#ifdef CONFIG_LCD
192 at91sam9rlek_lcd_hw_init();
193#endif
Stelian Pop2118ebb2008-05-08 18:52:25 +0200194 return 0;
195}
196
197int dram_init(void)
198{
Xu, Hong21d671d2011-08-01 03:56:53 +0000199 gd->ram_size = get_ram_size(
200 (void *)CONFIG_SYS_SDRAM_BASE,
201 CONFIG_SYS_SDRAM_SIZE);
Stelian Pop2118ebb2008-05-08 18:52:25 +0200202 return 0;
203}