Blame - arch/arm/include/asm/arch-am33xx/hardware.h - github/trini/u-boot

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Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	1	/*
				2	* hardware.h
				3	*
				4	* hardware specific header
				5	*
Matt Porter	3ba65f9	2013-03-15 10:07:03 +0000	[diff] [blame]	6	* Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	7	*
Wolfgang Denk	1a45966	2013-07-08 09:37:19 +0200	[diff] [blame]	8	* SPDX-License-Identifier: GPL-2.0+
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	9	*/
				10
				11	#ifndef __AM33XX_HARDWARE_H
				12	#define __AM33XX_HARDWARE_H
				13
Matt Porter	8b029f2	2013-03-15 10:07:06 +0000	[diff] [blame]	14	#include <config.h>
Tom Rini	41aebf8	2012-08-08 17:03:10 -0700	[diff] [blame]	15	#include <asm/arch/omap.h>
Matt Porter	3ba65f9	2013-03-15 10:07:03 +0000	[diff] [blame]	16	#ifdef CONFIG_AM33XX
				17	#include <asm/arch/hardware_am33xx.h>
				18	#elif defined(CONFIG_TI814X)
				19	#include <asm/arch/hardware_ti814x.h>
Lokesh Vutla	c06e498	2013-07-30 11:36:28 +0530	[diff] [blame^]	20	#elif defined(CONFIG_AM43XX)
				21	#include <asm/arch/hardware_am43xx.h>
Matt Porter	3ba65f9	2013-03-15 10:07:03 +0000	[diff] [blame]	22	#endif
Tom Rini	41aebf8	2012-08-08 17:03:10 -0700	[diff] [blame]	23
Matt Porter	8b029f2	2013-03-15 10:07:06 +0000	[diff] [blame]	24	/*
				25	* Common hardware definitions
				26	*/
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	27
				28	/* DM Timer base addresses */
				29	#define DM_TIMER0_BASE 0x4802C000
				30	#define DM_TIMER1_BASE 0x4802E000
				31	#define DM_TIMER2_BASE 0x48040000
				32	#define DM_TIMER3_BASE 0x48042000
				33	#define DM_TIMER4_BASE 0x48044000
				34	#define DM_TIMER5_BASE 0x48046000
				35	#define DM_TIMER6_BASE 0x48048000
				36	#define DM_TIMER7_BASE 0x4804A000
				37
				38	/* GPIO Base address */
				39	#define GPIO0_BASE 0x48032000
				40	#define GPIO1_BASE 0x4804C000
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	41
				42	/* BCH Error Location Module */
				43	#define ELM_BASE 0x48080000
				44
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	45	/* EMIF Base address */
				46	#define EMIF4_0_CFG_BASE 0x4C000000
				47	#define EMIF4_1_CFG_BASE 0x4D000000
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	48
				49	/* PLL related registers */
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	50	#define CM_DPLL 0x44E00500
				51	#define CM_DEVICE 0x44E00700
Vaibhav Hiremath	000820b	2012-03-08 17:15:47 +0530	[diff] [blame]	52	#define CM_RTC 0x44E00800
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	53	#define CM_CEFUSE 0x44E00A00
				54	#define PRM_DEVICE 0x44E00F00
				55
				56	/* VTP Base address */
Matt Porter	3ba65f9	2013-03-15 10:07:03 +0000	[diff] [blame]	57	#define VTP1_CTRL_ADDR 0x48140E10
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	58
				59	/* DDR Base address */
				60	#define DDR_CTRL_ADDR 0x44E10E04
				61	#define DDR_CONTROL_BASE_ADDR 0x44E11404
Matt Porter	3ba65f9	2013-03-15 10:07:03 +0000	[diff] [blame]	62	#define DDR_PHY_CMD_ADDR2 0x47C0C800
				63	#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	64
				65	/* UART */
				66	#define DEFAULT_UART_BASE UART0_BASE
				67
				68	#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
				69	#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
				70
Ilya Yanok	8eb16b7	2012-11-06 13:06:30 +0000	[diff] [blame]	71	/* GPMC Base address */
				72	#define GPMC_BASE 0x50000000
				73
Chandan Nath	e79cd8e	2012-07-24 12:22:17 +0000	[diff] [blame]	74	/* CPSW Config space */
Matt Porter	81df2ba	2013-03-15 10:07:02 +0000	[diff] [blame]	75	#define CPSW_BASE 0x4A100000
Vaibhav Hiremath	000820b	2012-03-08 17:15:47 +0530	[diff] [blame]	76
Chandan Nath	5655108	2011-10-14 02:58:22 +0000	[diff] [blame]	77	#endif /* __AM33XX_HARDWARE_H */