| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * hardware.h |
| 3 | * |
| 4 | * hardware specific header |
| 5 | * |
| 6 | * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #ifndef __AM33XX_HARDWARE_H |
| 20 | #define __AM33XX_HARDWARE_H |
| 21 | |
| Tom Rini | 41aebf8 | 2012-08-08 17:03:10 -0700 | [diff] [blame] | 22 | #include <asm/arch/omap.h> |
| 23 | |
| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 24 | /* Module base addresses */ |
| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 25 | #define UART0_BASE 0x44E09000 |
| 26 | |
| 27 | /* DM Timer base addresses */ |
| 28 | #define DM_TIMER0_BASE 0x4802C000 |
| 29 | #define DM_TIMER1_BASE 0x4802E000 |
| 30 | #define DM_TIMER2_BASE 0x48040000 |
| 31 | #define DM_TIMER3_BASE 0x48042000 |
| 32 | #define DM_TIMER4_BASE 0x48044000 |
| 33 | #define DM_TIMER5_BASE 0x48046000 |
| 34 | #define DM_TIMER6_BASE 0x48048000 |
| 35 | #define DM_TIMER7_BASE 0x4804A000 |
| 36 | |
| 37 | /* GPIO Base address */ |
| 38 | #define GPIO0_BASE 0x48032000 |
| 39 | #define GPIO1_BASE 0x4804C000 |
| 40 | #define GPIO2_BASE 0x481AC000 |
| 41 | |
| 42 | /* BCH Error Location Module */ |
| 43 | #define ELM_BASE 0x48080000 |
| 44 | |
| 45 | /* Watchdog Timer */ |
| 46 | #define WDT_BASE 0x44E35000 |
| 47 | |
| 48 | /* Control Module Base Address */ |
| 49 | #define CTRL_BASE 0x44E10000 |
| Chandan Nath | e79cd8e | 2012-07-24 12:22:17 +0000 | [diff] [blame] | 50 | #define CTRL_DEVICE_BASE 0x44E10600 |
| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 51 | |
| 52 | /* PRCM Base Address */ |
| 53 | #define PRCM_BASE 0x44E00000 |
| 54 | |
| 55 | /* EMIF Base address */ |
| 56 | #define EMIF4_0_CFG_BASE 0x4C000000 |
| 57 | #define EMIF4_1_CFG_BASE 0x4D000000 |
| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 58 | |
| 59 | /* PLL related registers */ |
| 60 | #define CM_PER 0x44E00000 |
| 61 | #define CM_WKUP 0x44E00400 |
| 62 | #define CM_DPLL 0x44E00500 |
| 63 | #define CM_DEVICE 0x44E00700 |
| Vaibhav Hiremath | 000820b | 2012-03-08 17:15:47 +0530 | [diff] [blame^] | 64 | #define CM_RTC 0x44E00800 |
| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 65 | #define CM_CEFUSE 0x44E00A00 |
| 66 | #define PRM_DEVICE 0x44E00F00 |
| 67 | |
| 68 | /* VTP Base address */ |
| 69 | #define VTP0_CTRL_ADDR 0x44E10E0C |
| 70 | |
| 71 | /* DDR Base address */ |
| 72 | #define DDR_CTRL_ADDR 0x44E10E04 |
| 73 | #define DDR_CONTROL_BASE_ADDR 0x44E11404 |
| 74 | #define DDR_PHY_BASE_ADDR 0x44E12000 |
| 75 | #define DDR_PHY_BASE_ADDR2 0x44E120A4 |
| 76 | |
| 77 | /* UART */ |
| 78 | #define DEFAULT_UART_BASE UART0_BASE |
| 79 | |
| 80 | #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400) |
| 81 | #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE |
| 82 | |
| Chandan Nath | e79cd8e | 2012-07-24 12:22:17 +0000 | [diff] [blame] | 83 | /* CPSW Config space */ |
| 84 | #define AM335X_CPSW_BASE 0x4A100000 |
| 85 | #define AM335X_CPSW_MDIO_BASE 0x4A101000 |
| 86 | |
| Vaibhav Hiremath | 000820b | 2012-03-08 17:15:47 +0530 | [diff] [blame^] | 87 | /* RTC base address */ |
| 88 | #define AM335X_RTC_BASE 0x44E3E000 |
| 89 | |
| Chandan Nath | 5655108 | 2011-10-14 02:58:22 +0000 | [diff] [blame] | 90 | #endif /* __AM33XX_HARDWARE_H */ |