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wdenk7aa78612003-05-03 15:50:43 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_ATC 1 /* ...on a ATC board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk7aa78612003-05-03 15:50:43 +000039
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFF000000
41
wdenk7aa78612003-05-03 15:50:43 +000042/*
43 * select serial console configuration
44 *
45 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
46 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
47 * for SCC).
48 *
49 * if CONFIG_CONS_NONE is defined, then the serial console routines must
50 * defined elsewhere (for example, on the cogent platform, there are serial
51 * ports on the motherboard which are used for the serial console - see
52 * cogent/cma101/serial.[ch]).
53 */
54#define CONFIG_CONS_ON_SMC /* define if console on SMC */
55#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
56#undef CONFIG_CONS_NONE /* define if console on something else*/
57#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
58
59#define CONFIG_BAUDRATE 115200
60
61/*
62 * select ethernet configuration
63 *
64 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
65 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
66 * for FCC)
67 *
68 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050069 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk7aa78612003-05-03 15:50:43 +000070 */
71#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
72#undef CONFIG_ETHER_NONE /* define if ether on something else */
73#define CONFIG_ETHER_ON_FCC
74
wdenk7aa78612003-05-03 15:50:43 +000075#define CONFIG_ETHER_ON_FCC2
76
77/*
78 * - Rx-CLK is CLK13
79 * - Tx-CLK is CLK14
80 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
81 * - Enable Full Duplex in FSMR
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
84# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
85# define CONFIG_SYS_CPMFCR_RAMTYPE 0
86# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk7aa78612003-05-03 15:50:43 +000087
88#define CONFIG_ETHER_ON_FCC3
89
90/*
91 * - Rx-CLK is CLK15
92 * - Tx-CLK is CLK16
93 * - RAM for BD/Buffers is on the local Bus (see 28-13)
94 * - Enable Half Duplex in FSMR
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096# define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
97# define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
wdenk7aa78612003-05-03 15:50:43 +000098
99/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
100#define CONFIG_8260_CLKIN 64000000 /* in Hz */
101
102#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
103
104#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in Hz */
105
106#define CONFIG_PREBOOT \
107 "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100108 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;"\
wdenk7aa78612003-05-03 15:50:43 +0000109 "echo"
110
111#undef CONFIG_BOOTARGS
112#define CONFIG_BOOTCOMMAND \
113 "bootp;" \
114 "setenv bootargs root=/dev/nfs rw " \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200115 "nfsroot=${serverip}:${rootpath} " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100116 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"\
wdenk7aa78612003-05-03 15:50:43 +0000117 "bootm"
118
119/*-----------------------------------------------------------------------
120 * Miscellaneous configuration options
121 */
122
123#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk7aa78612003-05-03 15:50:43 +0000125
Jon Loeliger2fd90ce2007-07-09 21:48:26 -0500126
127/*
128 * BOOTP options
129 */
130#define CONFIG_BOOTP_SUBNETMASK
131#define CONFIG_BOOTP_GATEWAY
132#define CONFIG_BOOTP_HOSTNAME
133#define CONFIG_BOOTP_BOOTPATH
134#define CONFIG_BOOTP_BOOTFILESIZE
wdenk7aa78612003-05-03 15:50:43 +0000135
Jon Loeliger0b361c92007-07-04 22:31:42 -0500136
137/*
138 * Command line configuration.
139 */
140#include <config_cmd_default.h>
141
142#define CONFIG_CMD_EEPROM
143#define CONFIG_CMD_PCI
144#define CONFIG_CMD_PCMCIA
145#define CONFIG_CMD_DATE
146#define CONFIG_CMD_IDE
wdenk15ef8a52003-06-18 20:22:24 +0000147
148
wdenk66fd3d12003-05-18 11:30:09 +0000149#define CONFIG_DOS_PARTITION
wdenk7aa78612003-05-03 15:50:43 +0000150
wdenk7aa78612003-05-03 15:50:43 +0000151/*
152 * Miscellaneous configurable options
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_LONGHELP /* undef to save memory */
155#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500156#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk7aa78612003-05-03 15:50:43 +0000158#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk7aa78612003-05-03 15:50:43 +0000160#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
162#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
163#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk7aa78612003-05-03 15:50:43 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
166#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk7aa78612003-05-03 15:50:43 +0000167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk7aa78612003-05-03 15:50:43 +0000169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
wdenk66fd3d12003-05-18 11:30:09 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk7aa78612003-05-03 15:50:43 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
wdenk7aa78612003-05-03 15:50:43 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_ALLOC_DPRAM
wdenk7aa78612003-05-03 15:50:43 +0000177
178#undef CONFIG_WATCHDOG /* watchdog disabled */
179
180#define CONFIG_SPI
181
wdenk15ef8a52003-06-18 20:22:24 +0000182#define CONFIG_RTC_DS12887
183
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200184#define RTC_BASE_ADDR 0xF5000000
185#define RTC_PORT_ADDR RTC_BASE_ADDR + 0x800
186#define RTC_PORT_DATA RTC_BASE_ADDR + 0x808
wdenk15ef8a52003-06-18 20:22:24 +0000187
188#define CONFIG_MISC_INIT_R
189
wdenk7aa78612003-05-03 15:50:43 +0000190/*
191 * For booting Linux, the board info and command line data
192 * have to be in the first 8 MB of memory, since this is
193 * the maximum mapped by the Linux kernel during initialization.
194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk7aa78612003-05-03 15:50:43 +0000196
197/*-----------------------------------------------------------------------
198 * Flash configuration
199 */
200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_FLASH_BASE 0xFF000000
202#define CONFIG_SYS_FLASH_SIZE 0x00800000
wdenk7aa78612003-05-03 15:50:43 +0000203
204/*-----------------------------------------------------------------------
205 * FLASH organization
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
208#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk7aa78612003-05-03 15:50:43 +0000209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
211#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk7aa78612003-05-03 15:50:43 +0000212
213#define CONFIG_FLASH_16BIT
214
215/*-----------------------------------------------------------------------
216 * Hard Reset Configuration Words
217 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk7aa78612003-05-03 15:50:43 +0000219 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk7aa78612003-05-03 15:50:43 +0000221 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
wdenk9a0e21a2003-06-22 10:30:54 +0000223 HRCW_BPS10 |\
wdenk7aa78612003-05-03 15:50:43 +0000224 HRCW_APPC10)
225
226/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_HRCW_SLAVE1 0
228#define CONFIG_SYS_HRCW_SLAVE2 0
229#define CONFIG_SYS_HRCW_SLAVE3 0
230#define CONFIG_SYS_HRCW_SLAVE4 0
231#define CONFIG_SYS_HRCW_SLAVE5 0
232#define CONFIG_SYS_HRCW_SLAVE6 0
233#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk7aa78612003-05-03 15:50:43 +0000234
235/*-----------------------------------------------------------------------
236 * Internal Memory Mapped Register
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_IMMR 0xF0000000
wdenk7aa78612003-05-03 15:50:43 +0000239
240/*-----------------------------------------------------------------------
241 * Definitions for initial stack pointer and data area (in DPRAM)
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200244#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200245#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk7aa78612003-05-03 15:50:43 +0000247
248/*-----------------------------------------------------------------------
249 * Start addresses for the final memory configuration
250 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk7aa78612003-05-03 15:50:43 +0000252 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
wdenk7aa78612003-05-03 15:50:43 +0000254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_SDRAM_BASE 0x00000000
256#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200257#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
259#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk7aa78612003-05-03 15:50:43 +0000260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
262# define CONFIG_SYS_RAMBOOT
wdenk7aa78612003-05-03 15:50:43 +0000263#endif
264
wdenk66fd3d12003-05-18 11:30:09 +0000265#define CONFIG_PCI
266#define CONFIG_PCI_PNP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
wdenk66fd3d12003-05-18 11:30:09 +0000268
wdenk7aa78612003-05-03 15:50:43 +0000269#if 1
270/* environment is in Flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200271#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x30000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200273# define CONFIG_ENV_SIZE 0x10000
274# define CONFIG_ENV_SECT_SIZE 0x10000
wdenk7aa78612003-05-03 15:50:43 +0000275#else
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200276#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200277#define CONFIG_ENV_OFFSET 0
278#define CONFIG_ENV_SIZE 2048
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */
wdenk7aa78612003-05-03 15:50:43 +0000280#endif
wdenk7aa78612003-05-03 15:50:43 +0000281
282/*-----------------------------------------------------------------------
283 * Cache Configuration
284 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500286#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk7aa78612003-05-03 15:50:43 +0000288#endif
289
290/*-----------------------------------------------------------------------
291 * HIDx - Hardware Implementation-dependent Registers 2-11
292 *-----------------------------------------------------------------------
293 * HID0 also contains cache control - initially enable both caches and
294 * invalidate contents, then the final state leaves only the instruction
295 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
296 * but Soft reset does not.
297 *
298 * HID1 has only read-only information - nothing to set.
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
wdenk8bde7f72003-06-27 21:31:46 +0000301 HID0_DCI|HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
303#define CONFIG_SYS_HID2 0
wdenk7aa78612003-05-03 15:50:43 +0000304
305/*-----------------------------------------------------------------------
306 * RMR - Reset Mode Register 5-5
307 *-----------------------------------------------------------------------
308 * turn on Checkstop Reset Enable
309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_RMR RMR_CSRE
wdenk7aa78612003-05-03 15:50:43 +0000311
312/*-----------------------------------------------------------------------
313 * BCR - Bus Configuration 4-25
314 *-----------------------------------------------------------------------
315 */
316#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
wdenk7aa78612003-05-03 15:50:43 +0000318
319/*-----------------------------------------------------------------------
320 * SIUMCR - SIU Module Configuration 4-31
321 *-----------------------------------------------------------------------
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_APPC10|\
wdenk7aa78612003-05-03 15:50:43 +0000324 SIUMCR_CS10PC00|SIUMCR_BCTLC10)
325
326/*-----------------------------------------------------------------------
327 * SYPCR - System Protection Control 4-35
328 * SYPCR can only be written once after reset!
329 *-----------------------------------------------------------------------
330 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
331 */
332#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000334 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk7aa78612003-05-03 15:50:43 +0000335#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000337 SYPCR_SWRI|SYPCR_SWP)
wdenk7aa78612003-05-03 15:50:43 +0000338#endif /* CONFIG_WATCHDOG */
339
340/*-----------------------------------------------------------------------
341 * TMCNTSC - Time Counter Status and Control 4-40
342 *-----------------------------------------------------------------------
343 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
344 * and enable Time Counter
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk7aa78612003-05-03 15:50:43 +0000347
348/*-----------------------------------------------------------------------
349 * PISCR - Periodic Interrupt Status and Control 4-42
350 *-----------------------------------------------------------------------
351 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
352 * Periodic timer
353 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk7aa78612003-05-03 15:50:43 +0000355
356/*-----------------------------------------------------------------------
357 * SCCR - System Clock Control 9-8
358 *-----------------------------------------------------------------------
359 * Ensure DFBRG is Divide by 16
360 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk7aa78612003-05-03 15:50:43 +0000362
363/*-----------------------------------------------------------------------
364 * RCCR - RISC Controller Configuration 13-7
365 *-----------------------------------------------------------------------
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_RCCR 0
wdenk7aa78612003-05-03 15:50:43 +0000368
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
wdenk7aa78612003-05-03 15:50:43 +0000370/*-----------------------------------------------------------------------
371 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
372 *-----------------------------------------------------------------------
373 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374#define CONFIG_SYS_MPTPR 0x1F00
wdenk7aa78612003-05-03 15:50:43 +0000375
376/*-----------------------------------------------------------------------
377 * PSRT - Refresh Timer Register 10-16
378 *-----------------------------------------------------------------------
379 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PSRT 0x0f
wdenk7aa78612003-05-03 15:50:43 +0000381
382/*-----------------------------------------------------------------------
383 * PSRT - SDRAM Mode Register 10-10
384 *-----------------------------------------------------------------------
385 */
386
387 /* SDRAM initialization values for 8-column chips
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
wdenk7aa78612003-05-03 15:50:43 +0000390 ORxS_BPD_4 |\
wdenkf7de16a2003-05-12 09:51:52 +0000391 ORxS_ROWST_PBI1_A7 |\
392 ORxS_NUMR_12)
wdenk7aa78612003-05-03 15:50:43 +0000393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
wdenkf7de16a2003-05-12 09:51:52 +0000395 PSDMR_SDAM_A15_IS_A5 |\
396 PSDMR_BSMA_A15_A17 |\
397 PSDMR_SDA10_PBI1_A7 |\
wdenk7aa78612003-05-03 15:50:43 +0000398 PSDMR_RFRC_7_CLK |\
wdenkf7de16a2003-05-12 09:51:52 +0000399 PSDMR_PRETOACT_3W |\
400 PSDMR_ACTTORW_2W |\
wdenk7aa78612003-05-03 15:50:43 +0000401 PSDMR_LDOTOPRE_1C |\
402 PSDMR_WRC_1C |\
403 PSDMR_CL_2)
404
405 /* SDRAM initialization values for 9-column chips
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
wdenk7aa78612003-05-03 15:50:43 +0000408 ORxS_BPD_4 |\
wdenkf7de16a2003-05-12 09:51:52 +0000409 ORxS_ROWST_PBI1_A6 |\
410 ORxS_NUMR_12)
wdenk7aa78612003-05-03 15:50:43 +0000411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
wdenkf7de16a2003-05-12 09:51:52 +0000413 PSDMR_SDAM_A16_IS_A5 |\
414 PSDMR_BSMA_A15_A17 |\
415 PSDMR_SDA10_PBI1_A6 |\
wdenk7aa78612003-05-03 15:50:43 +0000416 PSDMR_RFRC_7_CLK |\
wdenkf7de16a2003-05-12 09:51:52 +0000417 PSDMR_PRETOACT_3W |\
418 PSDMR_ACTTORW_2W |\
wdenk7aa78612003-05-03 15:50:43 +0000419 PSDMR_LDOTOPRE_1C |\
420 PSDMR_WRC_1C |\
421 PSDMR_CL_2)
422
423/*
424 * Init Memory Controller:
425 *
426 * Bank Bus Machine PortSz Device
427 * ---- --- ------- ------ ------
428 * 0 60x GPCM 8 bit Boot ROM
429 * 1 60x GPCM 64 bit FLASH
430 * 2 60x SDRAM 64 bit SDRAM
431 *
432 */
433
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434#define CONFIG_SYS_MRS_OFFS 0x00000000
wdenk7aa78612003-05-03 15:50:43 +0000435
436/* Bank 0 - FLASH
437 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000439 BRx_PS_16 |\
440 BRx_MS_GPCM_P |\
441 BRx_V)
wdenk7aa78612003-05-03 15:50:43 +0000442
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000444 ORxG_CSNT |\
445 ORxG_ACS_DIV1 |\
446 ORxG_SCY_3_CLK |\
447 ORxU_EHTR_8IDLE)
wdenk7aa78612003-05-03 15:50:43 +0000448
449
450/* Bank 2 - 60x bus SDRAM
451 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#ifndef CONFIG_SYS_RAMBOOT
453#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000454 BRx_PS_64 |\
455 BRx_MS_SDRAM_P |\
456 BRx_V)
wdenk7aa78612003-05-03 15:50:43 +0000457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
wdenk7aa78612003-05-03 15:50:43 +0000459
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
461#endif /* CONFIG_SYS_RAMBOOT */
wdenk7aa78612003-05-03 15:50:43 +0000462
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_BR4_PRELIM ((RTC_BASE_ADDR & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000464 BRx_PS_8 |\
465 BRx_MS_UPMA |\
466 BRx_V)
wdenk15ef8a52003-06-18 20:22:24 +0000467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_OR4_PRELIM (ORxU_AM_MSK | ORxU_BI)
wdenk8bde7f72003-06-27 21:31:46 +0000469
wdenk66fd3d12003-05-18 11:30:09 +0000470/*-----------------------------------------------------------------------
471 * PCMCIA stuff
472 *-----------------------------------------------------------------------
473 *
474 */
475#define CONFIG_I82365
476
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x81000000
478#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
wdenk66fd3d12003-05-18 11:30:09 +0000479
480/*-----------------------------------------------------------------------
481 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
482 *-----------------------------------------------------------------------
483 */
484
485#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
486
487#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
488#undef CONFIG_IDE_LED /* LED for ide not supported */
489#undef CONFIG_IDE_RESET /* reset for ide not supported */
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
492#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenk66fd3d12003-05-18 11:30:09 +0000493
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenk66fd3d12003-05-18 11:30:09 +0000495
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_ATA_BASE_ADDR 0xa0000000
wdenk66fd3d12003-05-18 11:30:09 +0000497
498/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_ATA_DATA_OFFSET 0x100
wdenk66fd3d12003-05-18 11:30:09 +0000500
501/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200502#define CONFIG_SYS_ATA_REG_OFFSET 0x100
wdenk66fd3d12003-05-18 11:30:09 +0000503
504/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_ATA_ALT_OFFSET 0x108
wdenk66fd3d12003-05-18 11:30:09 +0000506
wdenk7aa78612003-05-03 15:50:43 +0000507#endif /* __CONFIG_H */