blob: 19da1337e7fb239bc12d34989afc8d38387a9db3 [file] [log] [blame]
Heiko Schocherde044362008-11-20 09:57:47 +01001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * (C) Copyright 2008
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 */
26#define CONFIG_E300 1 /* E300 family */
27#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050028#define CONFIG_MPC83xx 1 /* MPC83xx family */
Heiko Schocherde044362008-11-20 09:57:47 +010029#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
30#define CONFIG_KMETER1 1 /* KMETER1 board specific */
Heiko Schocher605f78e2009-02-24 11:30:44 +010031#define CONFIG_HOSTNAME kmeter1
Heiko Schocherde044362008-11-20 09:57:47 +010032
Heiko Schocher1e8f4e72008-11-20 09:59:09 +010033/* include common defines/options for all Keymile boards */
34#include "keymile-common.h"
35
Heiko Schocher364123d2009-03-12 07:37:18 +010036#undef CONFIG_SYS_I2C_INIT_BOARD
Heiko Schocher19f0e932009-02-24 11:30:34 +010037#define CONFIG_MISC_INIT_R 1
Heiko Schocherde044362008-11-20 09:57:47 +010038/*
39 * System Clock Setup
40 */
41#define CONFIG_83XX_CLKIN 66000000
42#define CONFIG_SYS_CLK_FREQ 66000000
43#define CONFIG_83XX_PCICLK 66000000
44
45/*
46 * Hardware Reset Configuration Word
47 */
48#define CONFIG_SYS_HRCW_LOW (\
49 HRCWL_CSB_TO_CLKIN_4X1 | \
50 HRCWL_CORE_TO_CSB_2X1 | \
51 HRCWL_CE_PLL_VCO_DIV_2 | \
52 HRCWL_CE_TO_PLL_1X6 )
53
54#define CONFIG_SYS_HRCW_HIGH (\
55 HRCWH_CORE_ENABLE | \
56 HRCWH_FROM_0X00000100 | \
Heiko Schocher605f78e2009-02-24 11:30:44 +010057 HRCWH_BOOTSEQ_DISABLE | \
Heiko Schocherde044362008-11-20 09:57:47 +010058 HRCWH_SW_WATCHDOG_DISABLE | \
59 HRCWH_ROM_LOC_LOCAL_16BIT | \
60 HRCWH_BIG_ENDIAN | \
Heiko Schocher605f78e2009-02-24 11:30:44 +010061 HRCWH_LALE_EARLY | \
Heiko Schocherde044362008-11-20 09:57:47 +010062 HRCWH_LDP_CLEAR )
63
64/*
65 * System IO Config
66 */
67#define CONFIG_SYS_SICRH 0x00000006
68#define CONFIG_SYS_SICRL 0x00000000
69
Heiko Schocherde044362008-11-20 09:57:47 +010070/*
71 * IMMR new address
72 */
73#define CONFIG_SYS_IMMR 0xE0000000
74
75/*
76 * DDR Setup
77 */
78#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
79#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
80#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
81#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
82 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
83
84#define CFG_83XX_DDR_USES_CS0
85
86#undef CONFIG_DDR_ECC
87
88/*
89 * DDRCDR - DDR Control Driver Register
90 */
91
92#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
93
94/*
95 * Manually set up DDR parameters
96 */
97#define CONFIG_DDR_II
Heiko Schocher118cbe32009-02-24 11:30:40 +010098#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
99#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
Heiko Schocherde044362008-11-20 09:57:47 +0100100#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
101 CSCONFIG_ROW_BIT_13 | \
102 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
103
104#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
105 SDRAM_CFG_SREN)
106#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
107#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100108#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
109 (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100110
Heiko Schocher605f78e2009-02-24 11:30:44 +0100111#define CONFIG_SYS_DDRCDR 0x40000001
112#define CONFIG_SYS_DDR_MODE 0x47860452
113#define CONFIG_SYS_DDR_MODE2 0x8080c000
Heiko Schocherde044362008-11-20 09:57:47 +0100114
115#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
116 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
117 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
118 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
119 (0 << TIMING_CFG0_WWT_SHIFT) | \
120 (0 << TIMING_CFG0_RRT_SHIFT) | \
121 (0 << TIMING_CFG0_WRT_SHIFT) | \
122 (0 << TIMING_CFG0_RWT_SHIFT))
123
Heiko Schocher605f78e2009-02-24 11:30:44 +0100124#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100125 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100126 ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
127 ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
128 ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
129 ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
130 ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
131 ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100132
Heiko Schocher605f78e2009-02-24 11:30:44 +0100133#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100134 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
135 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100136 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
137 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
Heiko Schocherde044362008-11-20 09:57:47 +0100138 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100139 (5 << TIMING_CFG2_CPO_SHIFT))
Heiko Schocherde044362008-11-20 09:57:47 +0100140
141#define CONFIG_SYS_DDR_TIMING_3 0x00000000
142
143/*
Heiko Schocherde044362008-11-20 09:57:47 +0100144 * The reserved memory
145 */
146#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
147#define CONFIG_SYS_FLASH_BASE 0xF0000000
148#define CONFIG_SYS_FLASH_BASE_1 0xF2000000
Heiko Schocher605f78e2009-02-24 11:30:44 +0100149#define CONFIG_SYS_PIGGY_BASE 0xE8000000
150#define CONFIG_SYS_PIGGY_SIZE 128
Heiko Schocherde044362008-11-20 09:57:47 +0100151#define CONFIG_SYS_PAXE_BASE 0xA0000000
Heiko Schocher605f78e2009-02-24 11:30:44 +0100152#define CONFIG_SYS_PAXE_SIZE 512
Heiko Schocherde044362008-11-20 09:57:47 +0100153
154#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
155#define CONFIG_SYS_RAMBOOT
156#else
157#undef CONFIG_SYS_RAMBOOT
158#endif
159
Heiko Schocher605f78e2009-02-24 11:30:44 +0100160#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 256 kB for Mon */
Heiko Schocherde044362008-11-20 09:57:47 +0100161#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
162
163/*
164 * Initial RAM Base Address Setup
165 */
166#define CONFIG_SYS_INIT_RAM_LOCK 1
167#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
168#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
169#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
170#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
171
172/*
173 * Local Bus Configuration & Clock Setup
174 */
175#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
176
177/*
178 * Init Local Bus Memory Controller:
179 *
180 * Bank Bus Machine PortSz Size Device
181 * ---- --- ------- ------ ----- ------
182 * 0 Local GPCM 16 bit 256MB FLASH
Heiko Schocher605f78e2009-02-24 11:30:44 +0100183 * 1 Local GPCM 8 bit 128MB GPIO/PIGGY
184 * 3 Local GPCM 8 bit 512MB PAXE
Heiko Schocherde044362008-11-20 09:57:47 +0100185 *
186 */
187/*
188 * FLASH on the Local Bus
189 */
190#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
191#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
192#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
193#define CONFIG_SYS_FLASH_PROTECTION 1
194#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
195
196#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
197#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
198
199#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
200 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
201 BR_V)
202
203#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
204 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
205 OR_GPCM_SCY_5 | \
206 OR_GPCM_TRLX | OR_GPCM_EAD)
207
208#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
209#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
210#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
211
212#undef CONFIG_SYS_FLASH_CHECKSUM
213
214/*
215 * PRIO1/PIGGY on the local bus CS1
216 */
217#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
Heiko Schocher605f78e2009-02-24 11:30:44 +0100218#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
Heiko Schocherde044362008-11-20 09:57:47 +0100219
220#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
221 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
222 BR_V)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100223#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
Heiko Schocherde044362008-11-20 09:57:47 +0100224 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
225 OR_GPCM_SCY_2 | \
226 OR_GPCM_TRLX | OR_GPCM_EAD)
227
228/*
229 * PAXE on the local bus CS3
230 */
231#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
Heiko Schocher605f78e2009-02-24 11:30:44 +0100232#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
Heiko Schocherde044362008-11-20 09:57:47 +0100233
234#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
235 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
236 BR_V)
237#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
238 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
239 OR_GPCM_SCY_2 | \
240 OR_GPCM_TRLX | OR_GPCM_EAD)
241
242/*
243 * Serial Port
244 */
245#define CONFIG_CONS_INDEX 1
246#undef CONFIG_SERIAL_SOFTWARE_FIFO
247#define CONFIG_SYS_NS16550
248#define CONFIG_SYS_NS16550_SERIAL
249#define CONFIG_SYS_NS16550_REG_SIZE 1
250#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
251
Heiko Schocherde044362008-11-20 09:57:47 +0100252#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
253#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
254
255/* Pass open firmware flat tree */
256#define CONFIG_OF_LIBFDT 1
257#define CONFIG_OF_BOARD_SETUP 1
258#define CONFIG_OF_STDOUT_VIA_ALIAS
259
260/*
261 * General PCI
262 * Addresses are mapped 1-1.
263 */
264#undef CONFIG_PCI /* No PCI */
265
266#ifndef CONFIG_NET_MULTI
267#define CONFIG_NET_MULTI 1
268#endif
Heiko Schocherde044362008-11-20 09:57:47 +0100269/*
270 * QE UEC ethernet configuration
271 */
272#define CONFIG_UEC_ETH
273#define CONFIG_ETHPRIME "FSL UEC0"
274
275#define CONFIG_UEC_ETH1 /* GETH1 */
276#define UEC_VERBOSE_DEBUG 1
277
278#ifdef CONFIG_UEC_ETH1
279#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
280#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
281#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
282#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
283#define CONFIG_SYS_UEC1_PHY_ADDR 0
284#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
285#endif
286
287/*
288 * Environment
289 */
290
291#ifndef CONFIG_SYS_RAMBOOT
292#define CONFIG_ENV_IS_IN_FLASH 1
293#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
294#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
295#define CONFIG_ENV_SIZE 0x20000
296#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
297
298/* Address and size of Redundant Environment Sector */
299#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
300#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
301
302#else /* CFG_RAMBOOT */
303#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
304#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Heiko Schocher605f78e2009-02-24 11:30:44 +0100305#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Heiko Schocherde044362008-11-20 09:57:47 +0100306#define CONFIG_ENV_SIZE 0x2000
307#endif /* CFG_RAMBOOT */
308
Heiko Schocher19f0e932009-02-24 11:30:34 +0100309/* I2C */
310#define CONFIG_HARD_I2C /* I2C with hardware support */
311#undef CONFIG_SOFT_I2C /* I2C bit-banged */
312#define CONFIG_FSL_I2C
313#define CONFIG_SYS_I2C_SPEED 200000 /* I2C speed and slave address */
314#define CONFIG_SYS_I2C_SLAVE 0x7F
315#define CONFIG_SYS_I2C_OFFSET 0x3000
316#define CONFIG_I2C_MULTI_BUS 1
Heiko Schocher19f0e932009-02-24 11:30:34 +0100317#define CONFIG_SYS_MAX_I2C_BUS 2
318#define CONFIG_I2C_MUX 1
319
320/* EEprom support */
321#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Heiko Schocher19f0e932009-02-24 11:30:34 +0100322
323/* I2C SYSMON (LM75, AD7414 is almost compatible) */
324#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
325#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
326#define CONFIG_SYS_DTT_MAX_TEMP 70
327#define CONFIG_SYS_DTT_LOW_TEMP -30
328#define CONFIG_SYS_DTT_HYSTERESIS 3
329#define CONFIG_SYS_DTT_BUS_NUM (2)
330
Heiko Schocherde044362008-11-20 09:57:47 +0100331#if defined(CONFIG_PCI)
332#define CONFIG_CMD_PCI
333#endif
334
335#if defined(CFG_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500336#undef CONFIG_CMD_SAVEENV
Heiko Schocherde044362008-11-20 09:57:47 +0100337#undef CONFIG_CMD_LOADS
338#endif
339
Heiko Schocherde044362008-11-20 09:57:47 +0100340/*
341 * For booting Linux, the board info and command line data
342 * have to be in the first 8 MB of memory, since this is
343 * the maximum mapped by the Linux kernel during initialization.
344 */
345#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
346
347/*
348 * Core HID Setup
349 */
350#define CONFIG_SYS_HID0_INIT 0x000000000
351#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
352#define CONFIG_SYS_HID2 HID2_HBE
353
354/*
355 * MMU Setup
356 */
357
358#define CONFIG_HIGH_BATS 1 /* High BATs supported */
359
360/* DDR: cache cacheable */
361#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
362 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
363#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
364#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
365#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
366
367/* IMMRBAR & PCI IO: cache-inhibit and guarded */
368#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
369 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
370#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
371#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
372#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
373
374/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
375#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100376#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
Heiko Schocherde044362008-11-20 09:57:47 +0100377#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
378 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
379#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
380
381/* FLASH: icache cacheable, but dcache-inhibit and guarded */
382#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
383#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
384#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
385 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
386#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
387
388/* Stack in dcache: cacheable, no memory coherence */
389#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
390#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
391#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
392#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
393
394/* PAXE: icache cacheable, but dcache-inhibit and guarded */
395#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
Heiko Schocher605f78e2009-02-24 11:30:44 +0100396#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Heiko Schocherde044362008-11-20 09:57:47 +0100397#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
398 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
399#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
400
401#ifdef CONFIG_PCI
402/* PCI MEM space: cacheable */
403#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
404#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
405#define CFG_DBAT6L CFG_IBAT6L
406#define CFG_DBAT6U CFG_IBAT6U
407/* PCI MMIO space: cache-inhibit and guarded */
408#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
409 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
410#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
411#define CFG_DBAT7L CFG_IBAT7L
412#define CFG_DBAT7U CFG_IBAT7U
413#else /* CONFIG_PCI */
414#define CONFIG_SYS_IBAT6L (0)
415#define CONFIG_SYS_IBAT6U (0)
416#define CONFIG_SYS_IBAT7L (0)
417#define CONFIG_SYS_IBAT7U (0)
418#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
419#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
420#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
421#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
422#endif /* CONFIG_PCI */
423
424/*
425 * Internal Definitions
426 *
427 * Boot Flags
428 */
429#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
430#define BOOTFLAG_WARM 0x02 /* Software reboot */
431
Heiko Schocher605f78e2009-02-24 11:30:44 +0100432#define BOOTFLASH_START F0000000
433
434#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
435
436#define MTDIDS_DEFAULT "nor0=app"
437#define MTDPARTS_DEFAULT \
438 "mtdparts=app:256k(u-boot),128k(env),128k(envred)," \
439 "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
440
Heiko Schocherde044362008-11-20 09:57:47 +0100441/*
442 * Environment Configuration
443 */
444#define CONFIG_ENV_OVERWRITE
Heiko Schocher605f78e2009-02-24 11:30:44 +0100445#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */
446#define CONFIG_KM_DEF_ENV "km-common=empty\0"
Heiko Schocherde044362008-11-20 09:57:47 +0100447#endif
448
Heiko Schocherde044362008-11-20 09:57:47 +0100449#define CONFIG_EXTRA_ENV_SETTINGS \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100450 CONFIG_KM_DEF_ENV \
Heiko Schocherde044362008-11-20 09:57:47 +0100451 "rootpath=/opt/eldk/ppc_82xx\0" \
Heiko Schocher364123d2009-03-12 07:37:18 +0100452 "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Heiko Schocherde044362008-11-20 09:57:47 +0100453 "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
Heiko Schocherde044362008-11-20 09:57:47 +0100454 "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
455 "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
Heiko Schocher364123d2009-03-12 07:37:18 +0100456 "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0" \
Heiko Schocherde044362008-11-20 09:57:47 +0100457 "unlock=yes\0" \
Heiko Schocher364123d2009-03-12 07:37:18 +0100458 "fdt_addr=F0080000\0" \
459 "kernel_addr=F00a0000\0" \
460 "ramdisk_addr=F03a0000\0" \
461 "ramdisk_addr_r=F10000\0" \
Heiko Schocher19f0e932009-02-24 11:30:34 +0100462 "EEprom_ivm=pca9547:70:9\0" \
463 "dtt_bus=pca9547:70:a\0" \
Heiko Schocher605f78e2009-02-24 11:30:44 +0100464 "mtdids=nor0=app \0" \
465 "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0" \
Heiko Schocherde044362008-11-20 09:57:47 +0100466 ""
467
Heiko Schocher605f78e2009-02-24 11:30:44 +0100468#if defined(CONFIG_UEC_ETH)
469#define CONFIG_HAS_ETH0
470#endif
471
Heiko Schocherde044362008-11-20 09:57:47 +0100472#endif /* __CONFIG_H */