blob: 25b1c172e6c7367441f102df6bd59b75fff0c73e [file] [log] [blame]
Heiko Schocherde044362008-11-20 09:57:47 +01001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * (C) Copyright 2008
12 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 */
26#define CONFIG_E300 1 /* E300 family */
27#define CONFIG_QE 1 /* Has QE */
28#define CONFIG_MPC83XX 1 /* MPC83XX family */
29#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
30#define CONFIG_KMETER1 1 /* KMETER1 board specific */
31
Heiko Schocher1e8f4e72008-11-20 09:59:09 +010032/* include common defines/options for all Keymile boards */
33#include "keymile-common.h"
34
Heiko Schocherde044362008-11-20 09:57:47 +010035/*
36 * System Clock Setup
37 */
38#define CONFIG_83XX_CLKIN 66000000
39#define CONFIG_SYS_CLK_FREQ 66000000
40#define CONFIG_83XX_PCICLK 66000000
41
42/*
43 * Hardware Reset Configuration Word
44 */
45#define CONFIG_SYS_HRCW_LOW (\
46 HRCWL_CSB_TO_CLKIN_4X1 | \
47 HRCWL_CORE_TO_CSB_2X1 | \
48 HRCWL_CE_PLL_VCO_DIV_2 | \
49 HRCWL_CE_TO_PLL_1X6 )
50
51#define CONFIG_SYS_HRCW_HIGH (\
52 HRCWH_CORE_ENABLE | \
53 HRCWH_FROM_0X00000100 | \
54 HRCWH_BOOTSEQ_NORMAL | \
55 HRCWH_SW_WATCHDOG_DISABLE | \
56 HRCWH_ROM_LOC_LOCAL_16BIT | \
57 HRCWH_BIG_ENDIAN | \
58 HRCWH_LDP_CLEAR )
59
60/*
61 * System IO Config
62 */
63#define CONFIG_SYS_SICRH 0x00000006
64#define CONFIG_SYS_SICRL 0x00000000
65
Heiko Schocherde044362008-11-20 09:57:47 +010066/*
67 * IMMR new address
68 */
69#define CONFIG_SYS_IMMR 0xE0000000
70
71/*
72 * DDR Setup
73 */
74#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
75#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
76#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
77#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
78 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
79
80#define CFG_83XX_DDR_USES_CS0
81
82#undef CONFIG_DDR_ECC
83
84/*
85 * DDRCDR - DDR Control Driver Register
86 */
87
88#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
89
90/*
91 * Manually set up DDR parameters
92 */
93#define CONFIG_DDR_II
94#define CONFIG_SYS_DDR_SIZE 256 /* MB */
95#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
96#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
97 CSCONFIG_ROW_BIT_13 | \
98 CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
99
100#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
101 SDRAM_CFG_SREN)
102#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
103#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
104#define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
105 (0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
106
107#define CONFIG_SYS_DDR_MODE 0x04440242
108#define CONFIG_SYS_DDR_MODE2 0x00800000
109
110#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
111 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
112 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
113 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
114 (0 << TIMING_CFG0_WWT_SHIFT) | \
115 (0 << TIMING_CFG0_RRT_SHIFT) | \
116 (0 << TIMING_CFG0_WRT_SHIFT) | \
117 (0 << TIMING_CFG0_RWT_SHIFT))
118
119#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_40) | \
120 ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
121 ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
122 ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
123 ( 2 << TIMING_CFG1_REFREC_SHIFT) | \
124 ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
125 ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
126 ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
127
128#define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
129 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
130 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
131 (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
132 (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
133 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
134 (4 << TIMING_CFG2_CPO_SHIFT))
135
136#define CONFIG_SYS_DDR_TIMING_3 0x00000000
137
138/*
Heiko Schocherde044362008-11-20 09:57:47 +0100139 * The reserved memory
140 */
141#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
142#define CONFIG_SYS_FLASH_BASE 0xF0000000
143#define CONFIG_SYS_FLASH_BASE_1 0xF2000000
144#define CONFIG_SYS_PIGGY_BASE 0x80000000
145#define CONFIG_SYS_PAXE_BASE 0xA0000000
146#define CONFIG_SYS_PAXE_SIZE 256
147
148#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
149#define CONFIG_SYS_RAMBOOT
150#else
151#undef CONFIG_SYS_RAMBOOT
152#endif
153
154#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
155#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
156
157/*
158 * Initial RAM Base Address Setup
159 */
160#define CONFIG_SYS_INIT_RAM_LOCK 1
161#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
162#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
163#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
164#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
165
166/*
167 * Local Bus Configuration & Clock Setup
168 */
169#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
170
171/*
172 * Init Local Bus Memory Controller:
173 *
174 * Bank Bus Machine PortSz Size Device
175 * ---- --- ------- ------ ----- ------
176 * 0 Local GPCM 16 bit 256MB FLASH
177 * 1 Local GPCM 8 bit 256KB GPIO/PIGGY
178 * 3 Local GPCM 8 bit 256MB PAXE
179 *
180 */
181/*
182 * FLASH on the Local Bus
183 */
184#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
185#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
186#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */
187#define CONFIG_SYS_FLASH_PROTECTION 1
188#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
189
190#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
191#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
192
193#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
194 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
195 BR_V)
196
197#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
198 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
199 OR_GPCM_SCY_5 | \
200 OR_GPCM_TRLX | OR_GPCM_EAD)
201
202#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
203#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
204#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
205
206#undef CONFIG_SYS_FLASH_CHECKSUM
207
208/*
209 * PRIO1/PIGGY on the local bus CS1
210 */
211#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
212#define CONFIG_SYS_LBLAWAR1_PRELIM 0x80000011 /* 256KB window size */
213
214#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
215 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
216 BR_V)
217#define CONFIG_SYS_OR1_PRELIM (0xfffc0000 | /* 256KB */ \
218 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
219 OR_GPCM_SCY_2 | \
220 OR_GPCM_TRLX | OR_GPCM_EAD)
221
222/*
223 * PAXE on the local bus CS3
224 */
225#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
226#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001b /* 256MB window size */
227
228#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
229 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
230 BR_V)
231#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
232 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
233 OR_GPCM_SCY_2 | \
234 OR_GPCM_TRLX | OR_GPCM_EAD)
235
236/*
237 * Serial Port
238 */
239#define CONFIG_CONS_INDEX 1
240#undef CONFIG_SERIAL_SOFTWARE_FIFO
241#define CONFIG_SYS_NS16550
242#define CONFIG_SYS_NS16550_SERIAL
243#define CONFIG_SYS_NS16550_REG_SIZE 1
244#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
245
Heiko Schocherde044362008-11-20 09:57:47 +0100246#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
247#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
248
249/* Pass open firmware flat tree */
250#define CONFIG_OF_LIBFDT 1
251#define CONFIG_OF_BOARD_SETUP 1
252#define CONFIG_OF_STDOUT_VIA_ALIAS
253
254/*
255 * General PCI
256 * Addresses are mapped 1-1.
257 */
258#undef CONFIG_PCI /* No PCI */
259
260#ifndef CONFIG_NET_MULTI
261#define CONFIG_NET_MULTI 1
262#endif
Heiko Schocherde044362008-11-20 09:57:47 +0100263/*
264 * QE UEC ethernet configuration
265 */
266#define CONFIG_UEC_ETH
267#define CONFIG_ETHPRIME "FSL UEC0"
268
269#define CONFIG_UEC_ETH1 /* GETH1 */
270#define UEC_VERBOSE_DEBUG 1
271
272#ifdef CONFIG_UEC_ETH1
273#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
274#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
275#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
276#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
277#define CONFIG_SYS_UEC1_PHY_ADDR 0
278#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
279#endif
280
281/*
282 * Environment
283 */
284
285#ifndef CONFIG_SYS_RAMBOOT
286#define CONFIG_ENV_IS_IN_FLASH 1
287#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
288#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
289#define CONFIG_ENV_SIZE 0x20000
290#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
291
292/* Address and size of Redundant Environment Sector */
293#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
294#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
295
296#else /* CFG_RAMBOOT */
297#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
298#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
299#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
300#define CONFIG_ENV_SIZE 0x2000
301#endif /* CFG_RAMBOOT */
302
Heiko Schocherde044362008-11-20 09:57:47 +0100303#if defined(CONFIG_PCI)
304#define CONFIG_CMD_PCI
305#endif
306
307#if defined(CFG_RAMBOOT)
308#undef CONFIG_CMD_ENV
309#undef CONFIG_CMD_LOADS
310#endif
311
Heiko Schocherde044362008-11-20 09:57:47 +0100312/*
313 * For booting Linux, the board info and command line data
314 * have to be in the first 8 MB of memory, since this is
315 * the maximum mapped by the Linux kernel during initialization.
316 */
317#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
318
319/*
320 * Core HID Setup
321 */
322#define CONFIG_SYS_HID0_INIT 0x000000000
323#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
324#define CONFIG_SYS_HID2 HID2_HBE
325
326/*
327 * MMU Setup
328 */
329
330#define CONFIG_HIGH_BATS 1 /* High BATs supported */
331
332/* DDR: cache cacheable */
333#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
334 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
335#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
336#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
337#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
338
339/* IMMRBAR & PCI IO: cache-inhibit and guarded */
340#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
341 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
342#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
343#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
344#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
345
346/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
347#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
348#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
349#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
350 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
351#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
352
353/* FLASH: icache cacheable, but dcache-inhibit and guarded */
354#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
355#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
356#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
357 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
358#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
359
360/* Stack in dcache: cacheable, no memory coherence */
361#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
362#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
363#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
364#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
365
366/* PAXE: icache cacheable, but dcache-inhibit and guarded */
367#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
368#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
369#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
370 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
371#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
372
373#ifdef CONFIG_PCI
374/* PCI MEM space: cacheable */
375#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
376#define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
377#define CFG_DBAT6L CFG_IBAT6L
378#define CFG_DBAT6U CFG_IBAT6U
379/* PCI MMIO space: cache-inhibit and guarded */
380#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
381 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
382#define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
383#define CFG_DBAT7L CFG_IBAT7L
384#define CFG_DBAT7U CFG_IBAT7U
385#else /* CONFIG_PCI */
386#define CONFIG_SYS_IBAT6L (0)
387#define CONFIG_SYS_IBAT6U (0)
388#define CONFIG_SYS_IBAT7L (0)
389#define CONFIG_SYS_IBAT7U (0)
390#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
391#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
392#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
393#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
394#endif /* CONFIG_PCI */
395
396/*
397 * Internal Definitions
398 *
399 * Boot Flags
400 */
401#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
402#define BOOTFLAG_WARM 0x02 /* Software reboot */
403
Heiko Schocherde044362008-11-20 09:57:47 +0100404/*
405 * Environment Configuration
406 */
407#define CONFIG_ENV_OVERWRITE
408
409#if defined(CONFIG_UEC_ETH)
410#define CONFIG_HAS_ETH0
411#endif
412
Heiko Schocherde044362008-11-20 09:57:47 +0100413#define CONFIG_EXTRA_ENV_SETTINGS \
414 "netdev=eth0\0" \
415 "rootpath=/opt/eldk/ppc_82xx\0" \
416 "nfsargs=setenv bootargs root=/dev/nfs rw " \
417 "nfsroot=${serverip}:${rootpath}\0" \
418 "ramargs=setenv bootargs root=/dev/ram rw\0" \
419 "addip=setenv bootargs ${bootargs} " \
420 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
421 ":${hostname}:${netdev}:off panic=1\0" \
422 "addtty=setenv bootargs ${bootargs}" \
423 " console=ttyS0,${baudrate}\0" \
424 "fdt_addr=f0080000\0" \
425 "kernel_addr=f00a0000\0" \
426 "ramdisk_addr=f03a0000\0" \
427 "kernel_addr_r=400000\0" \
428 "fdt_addr_r=800000\0" \
429 "ramdisk_addr_r=810000\0" \
430 "flash_self=run ramargs addip addtty;" \
431 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
432 "flash_nfs=run nfsargs addip addtty;" \
433 "bootm ${kernel_addr} - ${fdt_addr}\0" \
434 "net_nfs=tftp ${kernel_addr_r} ${boot_file}; " \
435 "tftp ${fdt_addr_r} ${fdt_file}; " \
436 "run nfsargs addip addtty;" \
437 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
438 "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0" \
439 "boot_file=/tftpboot/kmeter1/uImage\0" \
440 "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0" \
441 "u-boot=/tftpboot/kmeter1/u-boot.bin\0" \
442 "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
443 "load=tftp $loadaddr ${u-boot}\0" \
444 "update=protect off " MK_STR(TEXT_BASE) " +$filesize;" \
445 "erase " MK_STR(TEXT_BASE) " +$filesize;" \
446 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
447 "protect on " MK_STR(TEXT_BASE) " +$filesize;" \
448 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;" \
449 "setenv filesize;saveenv\0" \
450 "upd=run load update\0" \
451 "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0" \
452 "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
453 "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0" \
454 "unlock=yes\0" \
455 ""
456
Heiko Schocherde044362008-11-20 09:57:47 +0100457#endif /* __CONFIG_H */