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Michal Simekf22651c2012-09-28 09:56:37 +00001/*
2 * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
3 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Michal Simekf22651c2012-09-28 09:56:37 +00005 */
6
7#include <common.h>
Michal Simek9e0e37a2014-02-24 11:16:32 +01008#include <fdtdec.h>
Michal Simek5b73caf2014-04-25 13:51:17 +02009#include <fpga.h>
10#include <mmc.h>
Michal Simekf22651c2012-09-28 09:56:37 +000011#include <netdev.h>
Michal Simekd5dae852013-04-22 15:43:02 +020012#include <zynqpl.h>
Michal Simek71936532013-04-12 16:33:08 +020013#include <asm/arch/hardware.h>
14#include <asm/arch/sys_proto.h>
Michal Simekf22651c2012-09-28 09:56:37 +000015
16DECLARE_GLOBAL_DATA_PTR;
17
Michal Simek0b680202014-03-04 12:41:05 +010018#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
19 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
Michal Simek5b73caf2014-04-25 13:51:17 +020020static xilinx_desc fpga;
Michal Simekd5dae852013-04-22 15:43:02 +020021
22/* It can be done differently */
Michal Simek5b73caf2014-04-25 13:51:17 +020023static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
24static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
25static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
26static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
Siva Durga Prasad Paladugub9103802014-11-25 15:29:54 +053027static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
Michal Simek5b73caf2014-04-25 13:51:17 +020028static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
29static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
Michal Simekd5dae852013-04-22 15:43:02 +020030#endif
31
Michal Simekf22651c2012-09-28 09:56:37 +000032int board_init(void)
33{
Michal Simek0b680202014-03-04 12:41:05 +010034#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
35 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
Michal Simekd5dae852013-04-22 15:43:02 +020036 u32 idcode;
37
38 idcode = zynq_slcr_get_idcode();
39
40 switch (idcode) {
41 case XILINX_ZYNQ_7010:
42 fpga = fpga010;
43 break;
Michal Simek31993d62013-09-26 16:39:03 +020044 case XILINX_ZYNQ_7015:
45 fpga = fpga015;
46 break;
Michal Simekd5dae852013-04-22 15:43:02 +020047 case XILINX_ZYNQ_7020:
48 fpga = fpga020;
49 break;
50 case XILINX_ZYNQ_7030:
51 fpga = fpga030;
52 break;
Siva Durga Prasad Paladugub9103802014-11-25 15:29:54 +053053 case XILINX_ZYNQ_7035:
54 fpga = fpga035;
55 break;
Michal Simekd5dae852013-04-22 15:43:02 +020056 case XILINX_ZYNQ_7045:
57 fpga = fpga045;
58 break;
Michal Simekfd2b10b2013-06-17 13:54:07 +020059 case XILINX_ZYNQ_7100:
60 fpga = fpga100;
61 break;
Michal Simekd5dae852013-04-22 15:43:02 +020062 }
63#endif
64
Michal Simek0b680202014-03-04 12:41:05 +010065#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
66 (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
Michal Simekd5dae852013-04-22 15:43:02 +020067 fpga_init();
68 fpga_add(fpga_xilinx, &fpga);
69#endif
70
Michal Simekf22651c2012-09-28 09:56:37 +000071 return 0;
72}
73
Jagannadha Sutradharudu Tekib3de9242014-01-09 01:48:21 +053074int board_late_init(void)
75{
76 switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
77 case ZYNQ_BM_NOR:
78 setenv("modeboot", "norboot");
79 break;
80 case ZYNQ_BM_SD:
81 setenv("modeboot", "sdboot");
82 break;
83 case ZYNQ_BM_JTAG:
84 setenv("modeboot", "jtagboot");
85 break;
86 default:
87 setenv("modeboot", "");
88 break;
89 }
90
91 return 0;
92}
Michal Simekf22651c2012-09-28 09:56:37 +000093
Michal Simekf22651c2012-09-28 09:56:37 +000094int board_eth_init(bd_t *bis)
95{
96 u32 ret = 0;
97
Michal Simek2d83d332013-07-25 15:47:16 +020098#ifdef CONFIG_XILINX_AXIEMAC
99 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
100 XILINX_AXIDMA_BASEADDR);
101#endif
102#ifdef CONFIG_XILINX_EMACLITE
103 u32 txpp = 0;
104 u32 rxpp = 0;
105# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
106 txpp = 1;
107# endif
108# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
109 rxpp = 1;
110# endif
111 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
112 txpp, rxpp);
113#endif
114
Michal Simek71936532013-04-12 16:33:08 +0200115#if defined(CONFIG_ZYNQ_GEM)
116# if defined(CONFIG_ZYNQ_GEM0)
David Andrey117cd4c2013-04-04 19:13:07 +0200117 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
David Andrey01fbf312013-04-05 17:24:24 +0200118 CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
Michal Simek71936532013-04-12 16:33:08 +0200119# endif
120# if defined(CONFIG_ZYNQ_GEM1)
David Andrey117cd4c2013-04-04 19:13:07 +0200121 ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
David Andrey01fbf312013-04-05 17:24:24 +0200122 CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
Michal Simek71936532013-04-12 16:33:08 +0200123# endif
Michal Simekf22651c2012-09-28 09:56:37 +0000124#endif
Michal Simekf22651c2012-09-28 09:56:37 +0000125 return ret;
126}
Michal Simekf22651c2012-09-28 09:56:37 +0000127
Michal Simek293eb332013-04-22 14:56:49 +0200128#ifdef CONFIG_CMD_MMC
129int board_mmc_init(bd_t *bd)
130{
131 int ret = 0;
132
133#if defined(CONFIG_ZYNQ_SDHCI)
134# if defined(CONFIG_ZYNQ_SDHCI0)
135 ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
136# endif
137# if defined(CONFIG_ZYNQ_SDHCI1)
138 ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
139# endif
140#endif
141 return ret;
142}
143#endif
144
Michal Simekf22651c2012-09-28 09:56:37 +0000145int dram_init(void)
146{
Michal Simek9e0e37a2014-02-24 11:16:32 +0100147#ifdef CONFIG_OF_CONTROL
148 int node;
149 fdt_addr_t addr;
150 fdt_size_t size;
151 const void *blob = gd->fdt_blob;
Michal Simekf22651c2012-09-28 09:56:37 +0000152
Michal Simek9e0e37a2014-02-24 11:16:32 +0100153 node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
154 "memory", 7);
155 if (node == -FDT_ERR_NOTFOUND) {
156 debug("ZYNQ DRAM: Can't get memory node\n");
157 return -1;
158 }
159 addr = fdtdec_get_addr_size(blob, node, "reg", &size);
160 if (addr == FDT_ADDR_T_NONE || size == 0) {
161 debug("ZYNQ DRAM: Can't get base address or size\n");
162 return -1;
163 }
164 gd->ram_size = size;
165#else
166 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
167#endif
Michal Simek148ba552013-06-17 14:37:01 +0200168 zynq_ddrc_init();
169
Michal Simekf22651c2012-09-28 09:56:37 +0000170 return 0;
171}