commit 2d83d33a51926d6471eb9282d03d83783850d565
author Michal Simek <michal.simek@xilinx.com> Thu Jul 25 15:47:16 2013 +0200
committer Michal Simek <michal.simek@xilinx.com> Mon Aug 12 08:59:56 2013 +0200
tree b7259f261c9eef38bc14ca115d55e843405a9b88
parent 39523bef29f71967247ca00fe4b2c7e0831bb8a2

zynq: Enable axi ethernet and emaclite driver initialization

Zynq can have axi ethernet and emaclite IPs in programmable
logic.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

board/xilinx/zynq/board.c

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index ca159b0..decdce5 100644
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -61,6 +61,23 @@
 {
 	u32 ret = 0;
 
+#ifdef CONFIG_XILINX_AXIEMAC
+	ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
+						XILINX_AXIDMA_BASEADDR);
+#endif
+#ifdef CONFIG_XILINX_EMACLITE
+	u32 txpp = 0;
+	u32 rxpp = 0;
+# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
+	txpp = 1;
+# endif
+# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
+	rxpp = 1;
+# endif
+	ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
+			txpp, rxpp);
+#endif
+
 #if defined(CONFIG_ZYNQ_GEM)
 # if defined(CONFIG_ZYNQ_GEM0)
 	ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,