blob: 26406072482f202a8ca6e2fa6cd8a54c87fbea4c [file] [log] [blame]
Andy Fleming50586ef2008-10-30 16:47:16 -05001/*
Jerry Huangd621da02011-01-06 23:42:19 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
Andy Fleming50586ef2008-10-30 16:47:16 -05003 * Andy Fleming
4 *
5 * Based vaguely on the pxa mmc code:
6 * (C) Copyright 2003
7 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming50586ef2008-10-30 16:47:16 -050010 */
11
12#include <config.h>
13#include <common.h>
14#include <command.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040015#include <hwconfig.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050016#include <mmc.h>
17#include <part.h>
18#include <malloc.h>
19#include <mmc.h>
20#include <fsl_esdhc.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040021#include <fdt_support.h>
Andy Fleming50586ef2008-10-30 16:47:16 -050022#include <asm/io.h>
23
Andy Fleming50586ef2008-10-30 16:47:16 -050024DECLARE_GLOBAL_DATA_PTR;
25
26struct fsl_esdhc {
Haijun.Zhang511948b2013-10-30 11:37:55 +080027 uint dsaddr; /* SDMA system address register */
28 uint blkattr; /* Block attributes register */
29 uint cmdarg; /* Command argument register */
30 uint xfertyp; /* Transfer type register */
31 uint cmdrsp0; /* Command response 0 register */
32 uint cmdrsp1; /* Command response 1 register */
33 uint cmdrsp2; /* Command response 2 register */
34 uint cmdrsp3; /* Command response 3 register */
35 uint datport; /* Buffer data port register */
36 uint prsstat; /* Present state register */
37 uint proctl; /* Protocol control register */
38 uint sysctl; /* System Control Register */
39 uint irqstat; /* Interrupt status register */
40 uint irqstaten; /* Interrupt status enable register */
41 uint irqsigen; /* Interrupt signal enable register */
42 uint autoc12err; /* Auto CMD error status register */
43 uint hostcapblt; /* Host controller capabilities register */
44 uint wml; /* Watermark level register */
45 uint mixctrl; /* For USDHC */
46 char reserved1[4]; /* reserved */
47 uint fevt; /* Force event register */
48 uint admaes; /* ADMA error status register */
49 uint adsaddr; /* ADMA system address register */
50 char reserved2[160]; /* reserved */
51 uint hostver; /* Host controller version register */
52 char reserved3[4]; /* reserved */
53 uint dmaerraddr; /* DMA error address register */
54 char reserved4[4]; /* reserved */
55 uint dmaerrattr; /* DMA error attribute register */
56 char reserved5[4]; /* reserved */
57 uint hostcapblt2; /* Host controller capabilities register 2 */
58 char reserved6[8]; /* reserved */
59 uint tcr; /* Tuning control register */
60 char reserved7[28]; /* reserved */
61 uint sddirctl; /* SD direction control register */
62 char reserved8[712]; /* reserved */
63 uint scr; /* eSDHC control register */
Andy Fleming50586ef2008-10-30 16:47:16 -050064};
65
66/* Return the XFERTYP flags for a given command and data packet */
Kim Phillipseafa90a2012-10-29 13:34:44 +000067static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
Andy Fleming50586ef2008-10-30 16:47:16 -050068{
69 uint xfertyp = 0;
70
71 if (data) {
Dipen Dudhat77c14582009-10-05 15:41:58 +053072 xfertyp |= XFERTYP_DPSEL;
73#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
74 xfertyp |= XFERTYP_DMAEN;
75#endif
Andy Fleming50586ef2008-10-30 16:47:16 -050076 if (data->blocks > 1) {
77 xfertyp |= XFERTYP_MSBSEL;
78 xfertyp |= XFERTYP_BCEN;
Jerry Huangd621da02011-01-06 23:42:19 -060079#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
80 xfertyp |= XFERTYP_AC12EN;
81#endif
Andy Fleming50586ef2008-10-30 16:47:16 -050082 }
83
84 if (data->flags & MMC_DATA_READ)
85 xfertyp |= XFERTYP_DTDSEL;
86 }
87
88 if (cmd->resp_type & MMC_RSP_CRC)
89 xfertyp |= XFERTYP_CCCEN;
90 if (cmd->resp_type & MMC_RSP_OPCODE)
91 xfertyp |= XFERTYP_CICEN;
92 if (cmd->resp_type & MMC_RSP_136)
93 xfertyp |= XFERTYP_RSPTYP_136;
94 else if (cmd->resp_type & MMC_RSP_BUSY)
95 xfertyp |= XFERTYP_RSPTYP_48_BUSY;
96 else if (cmd->resp_type & MMC_RSP_PRESENT)
97 xfertyp |= XFERTYP_RSPTYP_48;
98
Wang Huan19060bd2014-09-05 13:52:40 +080099#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
Jason Liu4571de32011-03-22 01:32:31 +0000100 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
101 xfertyp |= XFERTYP_CMDTYP_ABORT;
102#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500103 return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
104}
105
Dipen Dudhat77c14582009-10-05 15:41:58 +0530106#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
107/*
108 * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
109 */
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200110static void
Dipen Dudhat77c14582009-10-05 15:41:58 +0530111esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
112{
Ira Snyder8eee2bd2011-12-23 08:30:40 +0000113 struct fsl_esdhc_cfg *cfg = mmc->priv;
114 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530115 uint blocks;
116 char *buffer;
117 uint databuf;
118 uint size;
119 uint irqstat;
120 uint timeout;
121
122 if (data->flags & MMC_DATA_READ) {
123 blocks = data->blocks;
124 buffer = data->dest;
125 while (blocks) {
126 timeout = PIO_TIMEOUT;
127 size = data->blocksize;
128 irqstat = esdhc_read32(&regs->irqstat);
129 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
130 && --timeout);
131 if (timeout <= 0) {
132 printf("\nData Read Failed in PIO Mode.");
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200133 return;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530134 }
135 while (size && (!(irqstat & IRQSTAT_TC))) {
136 udelay(100); /* Wait before last byte transfer complete */
137 irqstat = esdhc_read32(&regs->irqstat);
138 databuf = in_le32(&regs->datport);
139 *((uint *)buffer) = databuf;
140 buffer += 4;
141 size -= 4;
142 }
143 blocks--;
144 }
145 } else {
146 blocks = data->blocks;
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200147 buffer = (char *)data->src;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530148 while (blocks) {
149 timeout = PIO_TIMEOUT;
150 size = data->blocksize;
151 irqstat = esdhc_read32(&regs->irqstat);
152 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
153 && --timeout);
154 if (timeout <= 0) {
155 printf("\nData Write Failed in PIO Mode.");
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200156 return;
Dipen Dudhat77c14582009-10-05 15:41:58 +0530157 }
158 while (size && (!(irqstat & IRQSTAT_TC))) {
159 udelay(100); /* Wait before last byte transfer complete */
160 databuf = *((uint *)buffer);
161 buffer += 4;
162 size -= 4;
163 irqstat = esdhc_read32(&regs->irqstat);
164 out_le32(&regs->datport, databuf);
165 }
166 blocks--;
167 }
168 }
169}
170#endif
171
Andy Fleming50586ef2008-10-30 16:47:16 -0500172static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
173{
Andy Fleming50586ef2008-10-30 16:47:16 -0500174 int timeout;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200175 struct fsl_esdhc_cfg *cfg = mmc->priv;
Stefano Babicc67bee12010-02-05 15:11:27 +0100176 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Ye.Li71689772014-02-20 18:00:57 +0800177
Wolfgang Denk7b43db92010-05-09 23:52:59 +0200178 uint wml_value;
Andy Fleming50586ef2008-10-30 16:47:16 -0500179
180 wml_value = data->blocksize/4;
181
182 if (data->flags & MMC_DATA_READ) {
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530183 if (wml_value > WML_RD_WML_MAX)
184 wml_value = WML_RD_WML_MAX_VAL;
Andy Fleming50586ef2008-10-30 16:47:16 -0500185
Roy Zangab467c52010-02-09 18:23:33 +0800186 esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
Ye.Li71689772014-02-20 18:00:57 +0800187#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Stefano Babicc67bee12010-02-05 15:11:27 +0100188 esdhc_write32(&regs->dsaddr, (u32)data->dest);
Ye.Li71689772014-02-20 18:00:57 +0800189#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500190 } else {
Ye.Li71689772014-02-20 18:00:57 +0800191#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eric Nelsone576bd92012-04-25 14:28:48 +0000192 flush_dcache_range((ulong)data->src,
193 (ulong)data->src+data->blocks
194 *data->blocksize);
Ye.Li71689772014-02-20 18:00:57 +0800195#endif
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530196 if (wml_value > WML_WR_WML_MAX)
197 wml_value = WML_WR_WML_MAX_VAL;
Stefano Babicc67bee12010-02-05 15:11:27 +0100198 if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
Andy Fleming50586ef2008-10-30 16:47:16 -0500199 printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
200 return TIMEOUT;
201 }
Roy Zangab467c52010-02-09 18:23:33 +0800202
203 esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
204 wml_value << 16);
Ye.Li71689772014-02-20 18:00:57 +0800205#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Stefano Babicc67bee12010-02-05 15:11:27 +0100206 esdhc_write32(&regs->dsaddr, (u32)data->src);
Ye.Li71689772014-02-20 18:00:57 +0800207#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500208 }
209
Stefano Babicc67bee12010-02-05 15:11:27 +0100210 esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
Andy Fleming50586ef2008-10-30 16:47:16 -0500211
212 /* Calculate the timeout period for data transactions */
Priyanka Jainb71ea332011-03-03 09:18:56 +0530213 /*
214 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
215 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
216 * So, Number of SD Clock cycles for 0.25sec should be minimum
217 * (SD Clock/sec * 0.25 sec) SD Clock cycles
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500218 * = (mmc->clock * 1/4) SD Clock cycles
Priyanka Jainb71ea332011-03-03 09:18:56 +0530219 * As 1) >= 2)
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500220 * => (2^(timeout+13)) >= mmc->clock * 1/4
Priyanka Jainb71ea332011-03-03 09:18:56 +0530221 * Taking log2 both the sides
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500222 * => timeout + 13 >= log2(mmc->clock/4)
Priyanka Jainb71ea332011-03-03 09:18:56 +0530223 * Rounding up to next power of 2
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500224 * => timeout + 13 = log2(mmc->clock/4) + 1
225 * => timeout + 13 = fls(mmc->clock/4)
Priyanka Jainb71ea332011-03-03 09:18:56 +0530226 */
Andrew Gabbasovfb823982014-03-24 02:40:41 -0500227 timeout = fls(mmc->clock/4);
Andy Fleming50586ef2008-10-30 16:47:16 -0500228 timeout -= 13;
229
230 if (timeout > 14)
231 timeout = 14;
232
233 if (timeout < 0)
234 timeout = 0;
235
Kumar Gala5103a032011-01-29 15:36:10 -0600236#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
237 if ((timeout == 4) || (timeout == 8) || (timeout == 12))
238 timeout++;
239#endif
240
Haijun.Zhang1336e2d2014-03-18 17:04:23 +0800241#ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
242 timeout = 0xE;
243#endif
Stefano Babicc67bee12010-02-05 15:11:27 +0100244 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
Andy Fleming50586ef2008-10-30 16:47:16 -0500245
246 return 0;
247}
248
Tom Rini10dc7772014-05-23 09:19:05 -0400249#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
Eric Nelsone576bd92012-04-25 14:28:48 +0000250static void check_and_invalidate_dcache_range
251 (struct mmc_cmd *cmd,
252 struct mmc_data *data) {
253 unsigned start = (unsigned)data->dest ;
254 unsigned size = roundup(ARCH_DMA_MINALIGN,
255 data->blocks*data->blocksize);
256 unsigned end = start+size ;
257 invalidate_dcache_range(start, end);
258}
Tom Rini10dc7772014-05-23 09:19:05 -0400259#endif
260
Andy Fleming50586ef2008-10-30 16:47:16 -0500261/*
262 * Sends a command out on the bus. Takes the mmc pointer,
263 * a command pointer, and an optional data pointer.
264 */
265static int
266esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
267{
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500268 int err = 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500269 uint xfertyp;
270 uint irqstat;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200271 struct fsl_esdhc_cfg *cfg = mmc->priv;
Stefano Babicc67bee12010-02-05 15:11:27 +0100272 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500273
Jerry Huangd621da02011-01-06 23:42:19 -0600274#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
275 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
276 return 0;
277#endif
278
Stefano Babicc67bee12010-02-05 15:11:27 +0100279 esdhc_write32(&regs->irqstat, -1);
Andy Fleming50586ef2008-10-30 16:47:16 -0500280
281 sync();
282
283 /* Wait for the bus to be idle */
Stefano Babicc67bee12010-02-05 15:11:27 +0100284 while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
285 (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
286 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500287
Stefano Babicc67bee12010-02-05 15:11:27 +0100288 while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
289 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500290
291 /* Wait at least 8 SD clock cycles before the next command */
292 /*
293 * Note: This is way more than 8 cycles, but 1ms seems to
294 * resolve timing issues with some cards
295 */
296 udelay(1000);
297
298 /* Set up for a data transfer if we have one */
299 if (data) {
Andy Fleming50586ef2008-10-30 16:47:16 -0500300 err = esdhc_setup_data(mmc, data);
301 if(err)
302 return err;
303 }
304
305 /* Figure out the transfer arguments */
306 xfertyp = esdhc_xfertyp(cmd, data);
307
Andrew Gabbasov01b77352013-06-11 10:34:22 -0500308 /* Mask all irqs */
309 esdhc_write32(&regs->irqsigen, 0);
310
Andy Fleming50586ef2008-10-30 16:47:16 -0500311 /* Send the command */
Stefano Babicc67bee12010-02-05 15:11:27 +0100312 esdhc_write32(&regs->cmdarg, cmd->cmdarg);
Jason Liu46927082011-11-25 00:18:04 +0000313#if defined(CONFIG_FSL_USDHC)
314 esdhc_write32(&regs->mixctrl,
315 (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F));
316 esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
317#else
Stefano Babicc67bee12010-02-05 15:11:27 +0100318 esdhc_write32(&regs->xfertyp, xfertyp);
Jason Liu46927082011-11-25 00:18:04 +0000319#endif
Dirk Behme7a5b8022012-03-26 03:13:05 +0000320
Andy Fleming50586ef2008-10-30 16:47:16 -0500321 /* Wait for the command to complete */
Dirk Behme7a5b8022012-03-26 03:13:05 +0000322 while (!(esdhc_read32(&regs->irqstat) & (IRQSTAT_CC | IRQSTAT_CTOE)))
Stefano Babicc67bee12010-02-05 15:11:27 +0100323 ;
Andy Fleming50586ef2008-10-30 16:47:16 -0500324
Stefano Babicc67bee12010-02-05 15:11:27 +0100325 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleming50586ef2008-10-30 16:47:16 -0500326
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500327 if (irqstat & CMD_ERR) {
328 err = COMM_ERR;
329 goto out;
Dirk Behme7a5b8022012-03-26 03:13:05 +0000330 }
331
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500332 if (irqstat & IRQSTAT_CTOE) {
333 err = TIMEOUT;
334 goto out;
335 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500336
Dirk Behme7a5b8022012-03-26 03:13:05 +0000337 /* Workaround for ESDHC errata ENGcm03648 */
338 if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
339 int timeout = 2500;
340
341 /* Poll on DATA0 line for cmd with busy signal for 250 ms */
342 while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
343 PRSSTAT_DAT0)) {
344 udelay(100);
345 timeout--;
346 }
347
348 if (timeout <= 0) {
349 printf("Timeout waiting for DAT0 to go high!\n");
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500350 err = TIMEOUT;
351 goto out;
Dirk Behme7a5b8022012-03-26 03:13:05 +0000352 }
353 }
354
Andy Fleming50586ef2008-10-30 16:47:16 -0500355 /* Copy the response to the response buffer */
356 if (cmd->resp_type & MMC_RSP_136) {
357 u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
358
Stefano Babicc67bee12010-02-05 15:11:27 +0100359 cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
360 cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
361 cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
362 cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
Rabin Vincent998be3d2009-04-05 13:30:56 +0530363 cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
364 cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
365 cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
366 cmd->response[3] = (cmdrsp0 << 8);
Andy Fleming50586ef2008-10-30 16:47:16 -0500367 } else
Stefano Babicc67bee12010-02-05 15:11:27 +0100368 cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
Andy Fleming50586ef2008-10-30 16:47:16 -0500369
370 /* Wait until all of the blocks are transferred */
371 if (data) {
Dipen Dudhat77c14582009-10-05 15:41:58 +0530372#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
373 esdhc_pio_read_write(mmc, data);
374#else
Andy Fleming50586ef2008-10-30 16:47:16 -0500375 do {
Stefano Babicc67bee12010-02-05 15:11:27 +0100376 irqstat = esdhc_read32(&regs->irqstat);
Andy Fleming50586ef2008-10-30 16:47:16 -0500377
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500378 if (irqstat & IRQSTAT_DTOE) {
379 err = TIMEOUT;
380 goto out;
381 }
Frans Meulenbroeks63fb5a72010-07-31 04:45:18 +0000382
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500383 if (irqstat & DATA_ERR) {
384 err = COMM_ERR;
385 goto out;
386 }
Andrew Gabbasov9b74dc52013-04-07 23:06:08 +0000387 } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE);
Ye.Li71689772014-02-20 18:00:57 +0800388
Eric Nelson54899fc2013-04-03 12:31:56 +0000389 if (data->flags & MMC_DATA_READ)
390 check_and_invalidate_dcache_range(cmd, data);
Ye.Li71689772014-02-20 18:00:57 +0800391#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500392 }
393
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500394out:
395 /* Reset CMD and DATA portions on error */
396 if (err) {
397 esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
398 SYSCTL_RSTC);
399 while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
400 ;
401
402 if (data) {
403 esdhc_write32(&regs->sysctl,
404 esdhc_read32(&regs->sysctl) |
405 SYSCTL_RSTD);
406 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
407 ;
408 }
409 }
410
Stefano Babicc67bee12010-02-05 15:11:27 +0100411 esdhc_write32(&regs->irqstat, -1);
Andy Fleming50586ef2008-10-30 16:47:16 -0500412
Andrew Gabbasov8a573022014-03-24 02:41:06 -0500413 return err;
Andy Fleming50586ef2008-10-30 16:47:16 -0500414}
415
Kim Phillipseafa90a2012-10-29 13:34:44 +0000416static void set_sysctl(struct mmc *mmc, uint clock)
Andy Fleming50586ef2008-10-30 16:47:16 -0500417{
Andy Fleming50586ef2008-10-30 16:47:16 -0500418 int div, pre_div;
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200419 struct fsl_esdhc_cfg *cfg = mmc->priv;
Stefano Babicc67bee12010-02-05 15:11:27 +0100420 volatile struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000421 int sdhc_clk = cfg->sdhc_clk;
Andy Fleming50586ef2008-10-30 16:47:16 -0500422 uint clk;
423
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200424 if (clock < mmc->cfg->f_min)
425 clock = mmc->cfg->f_min;
Stefano Babicc67bee12010-02-05 15:11:27 +0100426
Andy Fleming50586ef2008-10-30 16:47:16 -0500427 if (sdhc_clk / 16 > clock) {
428 for (pre_div = 2; pre_div < 256; pre_div *= 2)
429 if ((sdhc_clk / pre_div) <= (clock * 16))
430 break;
431 } else
432 pre_div = 2;
433
434 for (div = 1; div <= 16; div++)
435 if ((sdhc_clk / (div * pre_div)) <= clock)
436 break;
437
438 pre_div >>= 1;
439 div -= 1;
440
441 clk = (pre_div << 8) | (div << 4);
442
Kumar Galacc4d1222010-03-18 15:51:05 -0500443 esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
Stefano Babicc67bee12010-02-05 15:11:27 +0100444
445 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
Andy Fleming50586ef2008-10-30 16:47:16 -0500446
447 udelay(10000);
448
Kumar Galacc4d1222010-03-18 15:51:05 -0500449 clk = SYSCTL_PEREN | SYSCTL_CKEN;
Stefano Babicc67bee12010-02-05 15:11:27 +0100450
451 esdhc_setbits32(&regs->sysctl, clk);
Andy Fleming50586ef2008-10-30 16:47:16 -0500452}
453
454static void esdhc_set_ios(struct mmc *mmc)
455{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200456 struct fsl_esdhc_cfg *cfg = mmc->priv;
Stefano Babicc67bee12010-02-05 15:11:27 +0100457 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500458
459 /* Set the clock speed */
460 set_sysctl(mmc, mmc->clock);
461
462 /* Set the bus width */
Stefano Babicc67bee12010-02-05 15:11:27 +0100463 esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
Andy Fleming50586ef2008-10-30 16:47:16 -0500464
465 if (mmc->bus_width == 4)
Stefano Babicc67bee12010-02-05 15:11:27 +0100466 esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
Andy Fleming50586ef2008-10-30 16:47:16 -0500467 else if (mmc->bus_width == 8)
Stefano Babicc67bee12010-02-05 15:11:27 +0100468 esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
469
Andy Fleming50586ef2008-10-30 16:47:16 -0500470}
471
472static int esdhc_init(struct mmc *mmc)
473{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200474 struct fsl_esdhc_cfg *cfg = mmc->priv;
Stefano Babicc67bee12010-02-05 15:11:27 +0100475 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
Andy Fleming50586ef2008-10-30 16:47:16 -0500476 int timeout = 1000;
477
Stefano Babicc67bee12010-02-05 15:11:27 +0100478 /* Reset the entire host controller */
Dirk Behmea61da722013-07-15 15:44:29 +0200479 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Stefano Babicc67bee12010-02-05 15:11:27 +0100480
481 /* Wait until the controller is available */
482 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
483 udelay(1000);
484
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000485#ifndef ARCH_MXC
P.V.Suresh2c1764e2010-12-04 10:37:23 +0530486 /* Enable cache snooping */
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000487 esdhc_write32(&regs->scr, 0x00000040);
488#endif
P.V.Suresh2c1764e2010-12-04 10:37:23 +0530489
Dirk Behmea61da722013-07-15 15:44:29 +0200490 esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
Andy Fleming50586ef2008-10-30 16:47:16 -0500491
492 /* Set the initial clock speed */
Jerry Huang4a6ee172010-11-25 17:06:07 +0000493 mmc_set_clock(mmc, 400000);
Andy Fleming50586ef2008-10-30 16:47:16 -0500494
495 /* Disable the BRR and BWR bits in IRQSTAT */
Stefano Babicc67bee12010-02-05 15:11:27 +0100496 esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
Andy Fleming50586ef2008-10-30 16:47:16 -0500497
498 /* Put the PROCTL reg back to the default */
Stefano Babicc67bee12010-02-05 15:11:27 +0100499 esdhc_write32(&regs->proctl, PROCTL_INIT);
Andy Fleming50586ef2008-10-30 16:47:16 -0500500
Stefano Babicc67bee12010-02-05 15:11:27 +0100501 /* Set timout to the maximum value */
502 esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
Andy Fleming50586ef2008-10-30 16:47:16 -0500503
Thierry Redingd48d2e22012-01-02 01:15:38 +0000504 return 0;
505}
Andy Fleming50586ef2008-10-30 16:47:16 -0500506
Thierry Redingd48d2e22012-01-02 01:15:38 +0000507static int esdhc_getcd(struct mmc *mmc)
508{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200509 struct fsl_esdhc_cfg *cfg = mmc->priv;
Thierry Redingd48d2e22012-01-02 01:15:38 +0000510 struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
511 int timeout = 1000;
Stefano Babicc67bee12010-02-05 15:11:27 +0100512
Haijun.Zhangf7e27cc2014-01-10 13:52:17 +0800513#ifdef CONFIG_ESDHC_DETECT_QUIRK
514 if (CONFIG_ESDHC_DETECT_QUIRK)
515 return 1;
516#endif
Thierry Redingd48d2e22012-01-02 01:15:38 +0000517 while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
518 udelay(1000);
519
520 return timeout > 0;
Andy Fleming50586ef2008-10-30 16:47:16 -0500521}
522
Jerry Huang48bb3bb2010-03-18 15:57:06 -0500523static void esdhc_reset(struct fsl_esdhc *regs)
524{
525 unsigned long timeout = 100; /* wait max 100 ms */
526
527 /* reset the controller */
Dirk Behmea61da722013-07-15 15:44:29 +0200528 esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
Jerry Huang48bb3bb2010-03-18 15:57:06 -0500529
530 /* hardware clears the bit when it is done */
531 while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
532 udelay(1000);
533 if (!timeout)
534 printf("MMC/SD: Reset never completed.\n");
535}
536
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200537static const struct mmc_ops esdhc_ops = {
538 .send_cmd = esdhc_send_cmd,
539 .set_ios = esdhc_set_ios,
540 .init = esdhc_init,
541 .getcd = esdhc_getcd,
542};
543
Stefano Babicc67bee12010-02-05 15:11:27 +0100544int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
Andy Fleming50586ef2008-10-30 16:47:16 -0500545{
Stefano Babicc67bee12010-02-05 15:11:27 +0100546 struct fsl_esdhc *regs;
Andy Fleming50586ef2008-10-30 16:47:16 -0500547 struct mmc *mmc;
Li Yang030955c2010-11-25 17:06:09 +0000548 u32 caps, voltage_caps;
Andy Fleming50586ef2008-10-30 16:47:16 -0500549
Stefano Babicc67bee12010-02-05 15:11:27 +0100550 if (!cfg)
551 return -1;
552
Stefano Babicc67bee12010-02-05 15:11:27 +0100553 regs = (struct fsl_esdhc *)cfg->esdhc_base;
554
Jerry Huang48bb3bb2010-03-18 15:57:06 -0500555 /* First reset the eSDHC controller */
556 esdhc_reset(regs);
557
Jerry Huang975324a2012-05-17 23:57:02 +0000558 esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
559 | SYSCTL_IPGEN | SYSCTL_CKEN);
560
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200561 memset(&cfg->cfg, 0, sizeof(cfg->cfg));
562
Li Yang030955c2010-11-25 17:06:09 +0000563 voltage_caps = 0;
Wang Huan19060bd2014-09-05 13:52:40 +0800564 caps = esdhc_read32(&regs->hostcapblt);
Roy Zang3b4456e2011-01-07 00:06:47 -0600565
566#ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
567 caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
568 ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
569#endif
Haijun.Zhangef38f3f2013-10-31 09:38:19 +0800570
571/* T4240 host controller capabilities register should have VS33 bit */
572#ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
573 caps = caps | ESDHC_HOSTCAPBLT_VS33;
574#endif
575
Andy Fleming50586ef2008-10-30 16:47:16 -0500576 if (caps & ESDHC_HOSTCAPBLT_VS18)
Li Yang030955c2010-11-25 17:06:09 +0000577 voltage_caps |= MMC_VDD_165_195;
Andy Fleming50586ef2008-10-30 16:47:16 -0500578 if (caps & ESDHC_HOSTCAPBLT_VS30)
Li Yang030955c2010-11-25 17:06:09 +0000579 voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
Andy Fleming50586ef2008-10-30 16:47:16 -0500580 if (caps & ESDHC_HOSTCAPBLT_VS33)
Li Yang030955c2010-11-25 17:06:09 +0000581 voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
582
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200583 cfg->cfg.name = "FSL_SDHC";
584 cfg->cfg.ops = &esdhc_ops;
Li Yang030955c2010-11-25 17:06:09 +0000585#ifdef CONFIG_SYS_SD_VOLTAGE
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200586 cfg->cfg.voltages = CONFIG_SYS_SD_VOLTAGE;
Li Yang030955c2010-11-25 17:06:09 +0000587#else
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200588 cfg->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
Li Yang030955c2010-11-25 17:06:09 +0000589#endif
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200590 if ((cfg->cfg.voltages & voltage_caps) == 0) {
Li Yang030955c2010-11-25 17:06:09 +0000591 printf("voltage not supported by controller\n");
592 return -1;
593 }
Andy Fleming50586ef2008-10-30 16:47:16 -0500594
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200595 cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
Andy Fleming50586ef2008-10-30 16:47:16 -0500596
Abbas Razaaad46592013-03-25 09:13:34 +0000597 if (cfg->max_bus_width > 0) {
598 if (cfg->max_bus_width < 8)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200599 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
Abbas Razaaad46592013-03-25 09:13:34 +0000600 if (cfg->max_bus_width < 4)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200601 cfg->cfg.host_caps &= ~MMC_MODE_4BIT;
Abbas Razaaad46592013-03-25 09:13:34 +0000602 }
603
Andy Fleming50586ef2008-10-30 16:47:16 -0500604 if (caps & ESDHC_HOSTCAPBLT_HSS)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200605 cfg->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
Andy Fleming50586ef2008-10-30 16:47:16 -0500606
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800607#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
608 if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200609 cfg->cfg.host_caps &= ~MMC_MODE_8BIT;
Haijun.Zhangd47e3d22014-01-10 13:52:18 +0800610#endif
611
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200612 cfg->cfg.f_min = 400000;
Masahiro Yamadac79cba32014-09-18 13:28:06 +0900613 cfg->cfg.f_max = min(gd->arch.sdhc_clk, 52000000);
Andy Fleming50586ef2008-10-30 16:47:16 -0500614
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200615 cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
616
617 mmc = mmc_create(&cfg->cfg, cfg);
618 if (mmc == NULL)
619 return -1;
Andy Fleming50586ef2008-10-30 16:47:16 -0500620
621 return 0;
622}
623
624int fsl_esdhc_mmc_init(bd_t *bis)
625{
Stefano Babicc67bee12010-02-05 15:11:27 +0100626 struct fsl_esdhc_cfg *cfg;
627
Fabio Estevam88227a12012-12-27 08:51:08 +0000628 cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
Stefano Babicc67bee12010-02-05 15:11:27 +0100629 cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
Simon Glasse9adeca2012-12-13 20:49:05 +0000630 cfg->sdhc_clk = gd->arch.sdhc_clk;
Stefano Babicc67bee12010-02-05 15:11:27 +0100631 return fsl_esdhc_initialize(bis, cfg);
Andy Fleming50586ef2008-10-30 16:47:16 -0500632}
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400633
Stefano Babicc67bee12010-02-05 15:11:27 +0100634#ifdef CONFIG_OF_LIBFDT
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400635void fdt_fixup_esdhc(void *blob, bd_t *bd)
636{
637 const char *compat = "fsl,esdhc";
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400638
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800639#ifdef CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400640 if (!hwconfig("esdhc")) {
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800641 do_fixup_by_compat(blob, compat, "status", "disabled",
642 8 + 1, 1);
643 return;
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400644 }
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800645#endif
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400646
647 do_fixup_by_compat_u32(blob, compat, "clock-frequency",
Simon Glasse9adeca2012-12-13 20:49:05 +0000648 gd->arch.sdhc_clk, 1);
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800649
650 do_fixup_by_compat(blob, compat, "status", "okay",
651 4 + 1, 1);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400652}
Stefano Babicc67bee12010-02-05 15:11:27 +0100653#endif