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wdenk7a8e9bed2003-05-31 18:35:21 +00001NAND FLASH commands and notes
2
Wolfgang Denk4e3ccd22006-03-06 11:25:22 +01003See NOTE below!!!
4
wdenk7a8e9bed2003-05-31 18:35:21 +00005# (C) Copyright 2003
6# Dave Ellis, SIXNET, dge@sixnetio.com
7#
Wolfgang Denk1a459662013-07-08 09:37:19 +02008# SPDX-License-Identifier: GPL-2.0+
wdenk7a8e9bed2003-05-31 18:35:21 +00009
10Commands:
11
12 nand bad
13 Print a list of all of the bad blocks in the current device.
14
15 nand device
16 Print information about the current NAND device.
17
18 nand device num
19 Make device `num' the current device and print information about it.
20
Stefan Roese856f0542006-10-28 15:55:52 +020021 nand erase off|partition size
22 nand erase clean [off|partition size]
23 Erase `size' bytes starting at offset `off'. Alternatively partition
24 name can be specified, in this case size will be eventually limited
25 to not exceed partition size (this behaviour applies also to read
26 and write commands). Only complete erase blocks can be erased.
27
28 If `erase' is specified without an offset or size, the entire flash
29 is erased. If `erase' is specified with partition but without an
30 size, the entire partition is erased.
wdenk7a8e9bed2003-05-31 18:35:21 +000031
32 If `clean' is specified, a JFFS2-style clean marker is written to
Stefan Roese856f0542006-10-28 15:55:52 +020033 each block after it is erased.
wdenk7a8e9bed2003-05-31 18:35:21 +000034
35 This command will not erase blocks that are marked bad. There is
36 a debug option in cmd_nand.c to allow bad blocks to be erased.
37 Please read the warning there before using it, as blocks marked
38 bad by the manufacturer must _NEVER_ be erased.
39
40 nand info
41 Print information about all of the NAND devices found.
42
Stefan Roese856f0542006-10-28 15:55:52 +020043 nand read addr ofs|partition size
Scott Wood984e03c2008-06-12 13:13:23 -050044 Read `size' bytes from `ofs' in NAND flash to `addr'. Blocks that
45 are marked bad are skipped. If a page cannot be read because an
46 uncorrectable data error is found, the command stops with an error.
wdenk7a8e9bed2003-05-31 18:35:21 +000047
Stefan Roese856f0542006-10-28 15:55:52 +020048 nand read.oob addr ofs|partition size
wdenk7a8e9bed2003-05-31 18:35:21 +000049 Read `size' bytes from the out-of-band data area corresponding to
50 `ofs' in NAND flash to `addr'. This is limited to the 16 bytes of
51 data for one 512-byte page or 2 256-byte pages. There is no check
52 for bad blocks or ECC errors.
53
Stefan Roese856f0542006-10-28 15:55:52 +020054 nand write addr ofs|partition size
Scott Wood984e03c2008-06-12 13:13:23 -050055 Write `size' bytes from `addr' to `ofs' in NAND flash. Blocks that
56 are marked bad are skipped. If a page cannot be read because an
57 uncorrectable data error is found, the command stops with an error.
wdenk7a8e9bed2003-05-31 18:35:21 +000058
Scott Wood984e03c2008-06-12 13:13:23 -050059 As JFFS2 skips blocks similarly, this allows writing a JFFS2 image,
60 as long as the image is short enough to fit even after skipping the
61 bad blocks. Compact images, such as those produced by mkfs.jffs2
62 should work well, but loading an image copied from another flash is
63 going to be trouble if there are any bad blocks.
wdenk7a8e9bed2003-05-31 18:35:21 +000064
Ben Gardinerc9494862011-06-14 16:35:07 -040065 nand write.trimffs addr ofs|partition size
66 Enabled by the CONFIG_CMD_NAND_TRIMFFS macro. This command will write to
67 the NAND flash in a manner identical to the 'nand write' command
68 described above -- with the additional check that all pages at the end
69 of eraseblocks which contain only 0xff data will not be written to the
70 NAND flash. This behaviour is required when flashing UBI images
71 containing UBIFS volumes as per the UBI FAQ[1].
72
73 [1] http://www.linux-mtd.infradead.org/doc/ubi.html#L_flasher_algo
74
Stefan Roese856f0542006-10-28 15:55:52 +020075 nand write.oob addr ofs|partition size
wdenk7a8e9bed2003-05-31 18:35:21 +000076 Write `size' bytes from `addr' to the out-of-band data area
77 corresponding to `ofs' in NAND flash. This is limited to the 16 bytes
78 of data for one 512-byte page or 2 256-byte pages. There is no check
79 for bad blocks.
80
Scott Wood418396e2012-03-02 14:01:57 -060081 nand read.raw addr ofs|partition [count]
82 nand write.raw addr ofs|partition [count]
83 Read or write one or more pages at "ofs" in NAND flash, from or to
84 "addr" in memory. This is a raw access, so ECC is avoided and the
85 OOB area is transferred as well. If count is absent, it is assumed
86 to be one page. As with .yaffs2 accesses, the data is formatted as
87 a packed sequence of "data, oob, data, oob, ..." -- no alignment of
88 individual pages is maintained.
Marek Vasutfb3659a2011-09-23 15:43:10 +020089
wdenk7a8e9bed2003-05-31 18:35:21 +000090Configuration Options:
91
pekon gupta434f2cf2014-07-18 17:59:42 +053092 CONFIG_SYS_NAND_U_BOOT_OFFS
93 NAND Offset from where SPL will read u-boot image. This is the starting
94 address of u-boot MTD partition in NAND.
95
Jon Loeligerb5501f72007-07-09 19:10:03 -050096 CONFIG_CMD_NAND
Vagrant Cascadian3f42dc82015-11-24 14:45:02 -080097 Enables NAND support and commands.
wdenk7a8e9bed2003-05-31 18:35:21 +000098
Benoît Thébaudeau3287f6d2012-11-16 20:20:54 +010099 CONFIG_CMD_NAND_TORTURE
100 Enables the torture command (see description of this command below).
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 CONFIG_SYS_MAX_NAND_DEVICE
wdenk7a8e9bed2003-05-31 18:35:21 +0000103 The maximum number of NAND devices you want to support.
104
Prabhakar Kushwaha68ec9c82013-10-04 13:47:58 +0530105 CONFIG_SYS_NAND_MAX_ECCPOS
106 If specified, overrides the maximum number of ECC bytes
107 supported. Useful for reducing image size, especially with SPL.
108 This must be at least 48 if nand_base.c is used.
109
110 CONFIG_SYS_NAND_MAX_OOBFREE
111 If specified, overrides the maximum number of free OOB regions
112 supported. Useful for reducing image size, especially with SPL.
113 This must be at least 2 if nand_base.c is used.
114
Scott Wood99067b02009-04-01 15:33:24 -0500115 CONFIG_SYS_NAND_MAX_CHIPS
116 The maximum number of NAND chips per device to be supported.
wdenk7a8e9bed2003-05-31 18:35:21 +0000117
Scott Wood578931b2012-01-12 19:07:23 -0600118 CONFIG_SYS_NAND_SELF_INIT
119 Traditionally, glue code in drivers/mtd/nand/nand.c has driven
120 the initialization process -- it provides the mtd and nand
121 structs, calls a board init function for a specific device,
122 calls nand_scan(), and registers with mtd.
123
124 This arrangement does not provide drivers with the flexibility to
125 run code between nand_scan_ident() and nand_scan_tail(), or other
126 deviations from the "normal" flow.
127
128 If a board defines CONFIG_SYS_NAND_SELF_INIT, drivers/mtd/nand/nand.c
129 will make one call to board_nand_init(), with no arguments. That
130 function is responsible for calling a driver init function for
131 each NAND device on the board, that performs all initialization
132 tasks except setting mtd->name, and registering with the rest of
133 U-Boot. Those last tasks are accomplished by calling nand_register()
134 on the new mtd device.
135
136 Example of new init to be added to the end of an existing driver
137 init:
138
Scott Wood578931b2012-01-12 19:07:23 -0600139 /* chip is struct nand_chip, and is now provided by the driver. */
Scott Woodb616d9b2016-05-30 13:57:55 -0500140 mtd = &chip.mtd;
Scott Wood578931b2012-01-12 19:07:23 -0600141
142 /*
143 * Fill in appropriate values if this driver uses these fields,
144 * or uses the standard read_byte/write_buf/etc. functions from
145 * nand_base.c that use these fields.
146 */
147 chip.IO_ADDR_R = ...;
148 chip.IO_ADDR_W = ...;
149
150 if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL))
151 error out
152
153 /*
154 * Insert here any code you wish to run after the chip has been
155 * identified, but before any other I/O is done.
156 */
157
158 if (nand_scan_tail(mtd))
159 error out
160
Scott Woodb616d9b2016-05-30 13:57:55 -0500161 /*
162 * devnum is the device number to be used in nand commands
163 * and in mtd->name. Must be less than CONFIG_SYS_NAND_MAX_DEVICE.
164 */
165 if (nand_register(devnum, mtd))
Scott Wood578931b2012-01-12 19:07:23 -0600166 error out
167
168 In addition to providing more flexibility to the driver, it reduces
169 the difference between a U-Boot driver and its Linux counterpart.
170 nand_init() is now reduced to calling board_nand_init() once, and
171 printing a size summary. This should also make it easier to
172 transition to delayed NAND initialization.
173
174 Please convert your driver even if you don't need the extra
175 flexibility, so that one day we can eliminate the old mechanism.
176
pekon guptabeba5f02013-11-18 19:02:59 +0530177
pekon guptad016dc42013-11-18 19:03:00 +0530178 CONFIG_SYS_NAND_ONFI_DETECTION
179 Enables detection of ONFI compliant devices during probe.
180 And fetching device parameters flashed on device, by parsing
181 ONFI parameter page.
182
183 CONFIG_BCH
184 Enables software based BCH ECC algorithm present in lib/bch.c
185 This is used by SoC platforms which do not have built-in ELM
186 hardware engine required for BCH ECC correction.
187
188
pekon guptabeba5f02013-11-18 19:02:59 +0530189Platform specific options
190=========================
191 CONFIG_NAND_OMAP_GPMC
192 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
193 GPMC controller is used for parallel NAND flash devices, and can
194 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
195 and BCH16 ECC algorithms.
196
197 CONFIG_NAND_OMAP_ELM
198 Enables omap_elm.c driver for OMAPx and AMxxxx platforms.
199 ELM controller is used for ECC error detection (not ECC calculation)
200 of BCH4, BCH8 and BCH16 ECC algorithms.
201 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
202 thus such SoC platforms need to depend on software library for ECC error
203 detection. However ECC calculation on such plaforms would still be
204 done by GPMC controller.
205
pekon gupta434f2cf2014-07-18 17:59:42 +0530206 CONFIG_SPL_NAND_AM33XX_BCH
207 Enables SPL-NAND driver (am335x_spl_bch.c) which supports ELM based
208 hardware ECC correction. This is useful for platforms which have ELM
209 hardware engine and use NAND boot mode.
210 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
211 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
212 SPL-NAND driver with software ECC correction support.
213
pekon gupta3f719062013-11-18 19:03:01 +0530214 CONFIG_NAND_OMAP_ECCSCHEME
215 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
216 It can take following values:
217 OMAP_ECC_HAM1_CODE_SW
218 1-bit Hamming code using software lib.
219 (for legacy devices only)
220 OMAP_ECC_HAM1_CODE_HW
221 1-bit Hamming code using GPMC hardware.
222 (for legacy devices only)
223 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
224 4-bit BCH code (unsupported)
225 OMAP_ECC_BCH4_CODE_HW
226 4-bit BCH code (unsupported)
227 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
228 8-bit BCH code with
229 - ecc calculation using GPMC hardware engine,
230 - error detection using software library.
231 - requires CONFIG_BCH to enable software BCH library
232 (For legacy device which do not have ELM h/w engine)
233 OMAP_ECC_BCH8_CODE_HW
234 8-bit BCH code with
235 - ecc calculation using GPMC hardware engine,
236 - error detection using ELM hardware engine.
pekon gupta867f0302014-06-02 17:14:43 +0530237 OMAP_ECC_BCH16_CODE_HW
238 16-bit BCH code with
239 - ecc calculation using GPMC hardware engine,
240 - error detection using ELM hardware engine.
241
242 How to select ECC scheme on OMAP and AMxx platforms ?
243 -----------------------------------------------------
244 Though higher ECC schemes have more capability to detect and correct
245 bit-flips, but still selection of ECC scheme is dependent on following
246 - hardware engines present in SoC.
247 Some legacy OMAP SoC do not have ELM h/w engine thus such
248 SoC cannot support BCHx_HW ECC schemes.
249 - size of OOB/Spare region
250 With higher ECC schemes, more OOB/Spare area is required to
251 store ECC. So choice of ECC scheme is limited by NAND oobsize.
252
253 In general following expression can help:
254 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
255 where
256 NAND_OOBSIZE = number of bytes available in
257 OOB/spare area per NAND page.
258 NAND_PAGESIZE = bytes in main-area of NAND page.
259 ECC_BYTES = number of ECC bytes generated to
260 protect 512 bytes of data, which is:
261 3 for HAM1_xx ecc schemes
262 7 for BCH4_xx ecc schemes
263 14 for BCH8_xx ecc schemes
264 26 for BCH16_xx ecc schemes
265
266 example to check for BCH16 on 2K page NAND
267 NAND_PAGESIZE = 2048
268 NAND_OOBSIZE = 64
269 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
270 Thus BCH16 cannot be supported on 2K page NAND.
271
272 However, for 4K pagesize NAND
273 NAND_PAGESIZE = 4096
274 NAND_OOBSIZE = 64
275 ECC_BYTES = 26
276 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
277 Thus BCH16 can be supported on 4K page NAND.
278
pekon guptabeba5f02013-11-18 19:02:59 +0530279
Daniel Mackc316f572014-06-25 14:43:32 +0200280 CONFIG_NAND_OMAP_GPMC_PREFETCH
281 On OMAP platforms that use the GPMC controller
282 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
283 uses the prefetch mode to speed up read operations.
284
Wolfgang Denk4e3ccd22006-03-06 11:25:22 +0100285NOTE:
286=====
287
Scott Wood99067b02009-04-01 15:33:24 -0500288The Disk On Chip driver is currently broken and has been for some time.
289There is a driver in drivers/mtd/nand, taken from Linux, that works with
290the current NAND system but has not yet been adapted to the u-boot
291environment.
Stefan Roese2255b2d2006-10-10 12:36:02 +0200292
Stefan Roese2255b2d2006-10-10 12:36:02 +0200293Additional improvements to the NAND subsystem by Guido Classen, 10-10-2006
294
295JFFS2 related commands:
296
297 implement "nand erase clean" and old "nand erase"
298 using both the new code which is able to skip bad blocks
299 "nand erase clean" additionally writes JFFS2-cleanmarkers in the oob.
300
Stefan Roese2255b2d2006-10-10 12:36:02 +0200301Miscellaneous and testing commands:
302 "markbad [offset]"
303 create an artificial bad block (for testing bad block handling)
304
305 "scrub [offset length]"
306 like "erase" but don't skip bad block. Instead erase them.
307 DANGEROUS!!! Factory set bad blocks will be lost. Use only
308 to remove artificial bad blocks created with the "markbad" command.
309
Benoît Thébaudeau3287f6d2012-11-16 20:20:54 +0100310 "torture offset"
311 Torture block to determine if it is still reliable.
312 Enabled by the CONFIG_CMD_NAND_TORTURE configuration option.
313 This command returns 0 if the block is still reliable, else 1.
314 If the block is detected as unreliable, it is up to the user to decide to
315 mark this block as bad.
316 The analyzed block is put through 3 erase / write cycles (or less if the block
317 is detected as unreliable earlier).
318 This command can be used in scripts, e.g. together with the markbad command to
319 automate retries and handling of possibly newly detected bad blocks if the
320 nand write command fails.
321 It can also be used manually by users having seen some NAND errors in logs to
322 search the root cause of these errors.
323 The underlying nand_torture() function is also useful for code willing to
324 automate actions following a nand->write() error. This would e.g. be required
325 in order to program or update safely firmware to NAND, especially for the UBI
326 part of such firmware.
327
Stefan Roese2255b2d2006-10-10 12:36:02 +0200328
329NAND locking command (for chips with active LOCKPRE pin)
330
331 "nand lock"
332 set NAND chip to lock state (all pages locked)
333
334 "nand lock tight"
335 set NAND chip to lock tight state (software can't change locking anymore)
336
337 "nand lock status"
338 displays current locking status of all pages
339
340 "nand unlock [offset] [size]"
341 unlock consecutive area (can be called multiple times for different areas)
342
Joe Hershbergereee623a2012-08-22 16:49:42 -0500343 "nand unlock.allexcept [offset] [size]"
344 unlock all except specified consecutive area
Stefan Roese2255b2d2006-10-10 12:36:02 +0200345
346I have tested the code with board containing 128MiB NAND large page chips
347and 32MiB small page chips.