blob: 041f8e37476538f0fe63b8dee892b66e7bb17a88 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Andreas Heppel <aheppel@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
wdenkc6097192002-11-03 00:24:07 +00008 */
9
10#ifndef _PCI_H
11#define _PCI_H
12
Minghuan Lianed5b5802015-07-10 11:35:08 +080013#define PCI_CFG_SPACE_SIZE 256
14#define PCI_CFG_SPACE_EXP_SIZE 4096
15
wdenkc6097192002-11-03 00:24:07 +000016/*
17 * Under PCI, each device has 256 bytes of configuration address space,
18 * of which the first 64 bytes are standardized as follows:
19 */
Bin Mengdac01fd2018-08-03 01:14:52 -070020#define PCI_STD_HEADER_SIZEOF 64
wdenkc6097192002-11-03 00:24:07 +000021#define PCI_VENDOR_ID 0x00 /* 16 bits */
22#define PCI_DEVICE_ID 0x02 /* 16 bits */
23#define PCI_COMMAND 0x04 /* 16 bits */
24#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
25#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
26#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
27#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
28#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
29#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
30#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
31#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
32#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
33#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
34
35#define PCI_STATUS 0x06 /* 16 bits */
36#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
37#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
38#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
39#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
40#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
41#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
42#define PCI_STATUS_DEVSEL_FAST 0x000
43#define PCI_STATUS_DEVSEL_MEDIUM 0x200
44#define PCI_STATUS_DEVSEL_SLOW 0x400
45#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
46#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
47#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
48#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
49#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
50
51#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
52 revision */
53#define PCI_REVISION_ID 0x08 /* Revision ID */
54#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
55#define PCI_CLASS_DEVICE 0x0a /* Device class */
56#define PCI_CLASS_CODE 0x0b /* Device class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000057#define PCI_CLASS_CODE_TOO_OLD 0x00
58#define PCI_CLASS_CODE_STORAGE 0x01
59#define PCI_CLASS_CODE_NETWORK 0x02
60#define PCI_CLASS_CODE_DISPLAY 0x03
61#define PCI_CLASS_CODE_MULTIMEDIA 0x04
62#define PCI_CLASS_CODE_MEMORY 0x05
63#define PCI_CLASS_CODE_BRIDGE 0x06
64#define PCI_CLASS_CODE_COMM 0x07
65#define PCI_CLASS_CODE_PERIPHERAL 0x08
66#define PCI_CLASS_CODE_INPUT 0x09
67#define PCI_CLASS_CODE_DOCKING 0x0A
68#define PCI_CLASS_CODE_PROCESSOR 0x0B
69#define PCI_CLASS_CODE_SERIAL 0x0C
70#define PCI_CLASS_CODE_WIRELESS 0x0D
71#define PCI_CLASS_CODE_I2O 0x0E
72#define PCI_CLASS_CODE_SATELLITE 0x0F
73#define PCI_CLASS_CODE_CRYPTO 0x10
74#define PCI_CLASS_CODE_DATA 0x11
75/* Base Class 0x12 - 0xFE is reserved */
76#define PCI_CLASS_CODE_OTHER 0xFF
77
wdenkc6097192002-11-03 00:24:07 +000078#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000079#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
80#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
81#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
82#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
83#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
84#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
85#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
86#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
87#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
88#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
89#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
90#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
91#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
92#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
93#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
94#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
95#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
96#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
97#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
98#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
99#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
100#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
101#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
102#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
103#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
104#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
105#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
106#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
107#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
108#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
109#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
110#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
111#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
112#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
113#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
114#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
115#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
116#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
117#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
118#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
119#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
120#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
121#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
122#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
123#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
124#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
125#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
126#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
127#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
128#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
129#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
130#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
131#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
132#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
133#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
134#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
135#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
136#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
137#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
138#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
139#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
140#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
142#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
143#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
144#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
145#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
146#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
147#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
148#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
149#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
150#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
151#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
152#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
153#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
154#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
155#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
156#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
157#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
158#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
159#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
160#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
161#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
162#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
163#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
164#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
165#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
166#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
167#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
168#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
169#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
170#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
171#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
172#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
173#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
174#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
175#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
176#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
177#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
178#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
179#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
180#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
wdenkc6097192002-11-03 00:24:07 +0000181
182#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
183#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
184#define PCI_HEADER_TYPE 0x0e /* 8 bits */
185#define PCI_HEADER_TYPE_NORMAL 0
186#define PCI_HEADER_TYPE_BRIDGE 1
187#define PCI_HEADER_TYPE_CARDBUS 2
188
189#define PCI_BIST 0x0f /* 8 bits */
190#define PCI_BIST_CODE_MASK 0x0f /* Return result */
191#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
192#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
193
194/*
195 * Base addresses specify locations in memory or I/O space.
196 * Decoded size can be determined by writing a value of
197 * 0xffffffff to the register, and reading it back. Only
198 * 1 bits are decoded.
199 */
200#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
201#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
202#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
203#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
204#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
205#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
206#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
207#define PCI_BASE_ADDRESS_SPACE_IO 0x01
208#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
209#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
210#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
211#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
212#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
213#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
Kumar Gala30e76d52008-10-21 08:36:08 -0500214#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
215#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
wdenkc6097192002-11-03 00:24:07 +0000216/* bit 1 is reserved if address_space = 1 */
217
218/* Header type 0 (normal devices) */
219#define PCI_CARDBUS_CIS 0x28
220#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
221#define PCI_SUBSYSTEM_ID 0x2e
222#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
223#define PCI_ROM_ADDRESS_ENABLE 0x01
Kumar Gala30e76d52008-10-21 08:36:08 -0500224#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
wdenkc6097192002-11-03 00:24:07 +0000225
226#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
227
228/* 0x35-0x3b are reserved */
229#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
230#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
231#define PCI_MIN_GNT 0x3e /* 8 bits */
232#define PCI_MAX_LAT 0x3f /* 8 bits */
233
Simon Glass5f48d792015-07-27 15:47:17 -0600234#define PCI_INTERRUPT_LINE_DISABLE 0xff
235
wdenkc6097192002-11-03 00:24:07 +0000236/* Header type 1 (PCI-to-PCI bridges) */
237#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
238#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
239#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
240#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
241#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
242#define PCI_IO_LIMIT 0x1d
243#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
244#define PCI_IO_RANGE_TYPE_16 0x00
245#define PCI_IO_RANGE_TYPE_32 0x01
246#define PCI_IO_RANGE_MASK ~0x0f
247#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
248#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
249#define PCI_MEMORY_LIMIT 0x22
250#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
251#define PCI_MEMORY_RANGE_MASK ~0x0f
252#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
253#define PCI_PREF_MEMORY_LIMIT 0x26
254#define PCI_PREF_RANGE_TYPE_MASK 0x0f
255#define PCI_PREF_RANGE_TYPE_32 0x00
256#define PCI_PREF_RANGE_TYPE_64 0x01
257#define PCI_PREF_RANGE_MASK ~0x0f
258#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
259#define PCI_PREF_LIMIT_UPPER32 0x2c
260#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
261#define PCI_IO_LIMIT_UPPER16 0x32
262/* 0x34 same as for htype 0 */
263/* 0x35-0x3b is reserved */
264#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
265/* 0x3c-0x3d are same as for htype 0 */
266#define PCI_BRIDGE_CONTROL 0x3e
267#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
268#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
269#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
270#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
271#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
272#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
273#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
274
275/* Header type 2 (CardBus bridges) */
276#define PCI_CB_CAPABILITY_LIST 0x14
277/* 0x15 reserved */
278#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
279#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
280#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
281#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
282#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
283#define PCI_CB_MEMORY_BASE_0 0x1c
284#define PCI_CB_MEMORY_LIMIT_0 0x20
285#define PCI_CB_MEMORY_BASE_1 0x24
286#define PCI_CB_MEMORY_LIMIT_1 0x28
287#define PCI_CB_IO_BASE_0 0x2c
288#define PCI_CB_IO_BASE_0_HI 0x2e
289#define PCI_CB_IO_LIMIT_0 0x30
290#define PCI_CB_IO_LIMIT_0_HI 0x32
291#define PCI_CB_IO_BASE_1 0x34
292#define PCI_CB_IO_BASE_1_HI 0x36
293#define PCI_CB_IO_LIMIT_1 0x38
294#define PCI_CB_IO_LIMIT_1_HI 0x3a
295#define PCI_CB_IO_RANGE_MASK ~0x03
296/* 0x3c-0x3d are same as for htype 0 */
297#define PCI_CB_BRIDGE_CONTROL 0x3e
298#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
299#define PCI_CB_BRIDGE_CTL_SERR 0x02
300#define PCI_CB_BRIDGE_CTL_ISA 0x04
301#define PCI_CB_BRIDGE_CTL_VGA 0x08
302#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
303#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
304#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
305#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
306#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
307#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
308#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
309#define PCI_CB_SUBSYSTEM_ID 0x42
310#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
311/* 0x48-0x7f reserved */
312
313/* Capability lists */
314
315#define PCI_CAP_LIST_ID 0 /* Capability ID */
316#define PCI_CAP_ID_PM 0x01 /* Power Management */
317#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
318#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
319#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
320#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
321#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
Bin Meng5d544f92018-08-03 01:14:51 -0700322#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
323#define PCI_CAP_ID_HT 0x08 /* HyperTransport */
324#define PCI_CAP_ID_VNDR 0x09 /* Vendor-Specific */
325#define PCI_CAP_ID_DBG 0x0A /* Debug port */
326#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */
327#define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
328#define PCI_CAP_ID_SSVID 0x0D /* Bridge subsystem vendor/device ID */
329#define PCI_CAP_ID_AGP3 0x0E /* AGP Target PCI-PCI bridge */
330#define PCI_CAP_ID_SECDEV 0x0F /* Secure Device */
331#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
332#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
333#define PCI_CAP_ID_SATA 0x12 /* SATA Data/Index Conf. */
334#define PCI_CAP_ID_AF 0x13 /* PCI Advanced Features */
335#define PCI_CAP_ID_EA 0x14 /* PCI Enhanced Allocation */
336#define PCI_CAP_ID_MAX PCI_CAP_ID_EA
wdenkc6097192002-11-03 00:24:07 +0000337#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
338#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
339#define PCI_CAP_SIZEOF 4
340
341/* Power Management Registers */
342
343#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
344#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
345#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
346#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
347#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
348#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
349#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
350#define PCI_PM_CTRL 4 /* PM control and status register */
351#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
352#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
353#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
354#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
355#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
356#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
357#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
358#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
359#define PCI_PM_DATA_REGISTER 7 /* (??) */
360#define PCI_PM_SIZEOF 8
361
362/* AGP registers */
363
364#define PCI_AGP_VERSION 2 /* BCD version number */
365#define PCI_AGP_RFU 3 /* Rest of capability flags */
366#define PCI_AGP_STATUS 4 /* Status register */
367#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
368#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
369#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
370#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
371#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
372#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
373#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
374#define PCI_AGP_COMMAND 8 /* Control register */
375#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
376#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
377#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
378#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
379#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
380#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
381#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
382#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
383#define PCI_AGP_SIZEOF 12
384
Matthew McClintockf0e6f572006-06-28 10:44:49 -0500385/* PCI-X registers */
386
387#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
388#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
389#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
390#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
391#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
392
393
wdenkc6097192002-11-03 00:24:07 +0000394/* Slot Identification */
395
396#define PCI_SID_ESR 2 /* Expansion Slot Register */
397#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
398#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
399#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
400
401/* Message Signalled Interrupts registers */
402
403#define PCI_MSI_FLAGS 2 /* Various flags */
404#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
405#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
406#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
407#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
408#define PCI_MSI_RFU 3 /* Rest of capability flags */
409#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
410#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
411#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
412#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
413
414#define PCI_MAX_PCI_DEVICES 32
415#define PCI_MAX_PCI_FUNCTIONS 8
416
Zhao Qiang287df012013-10-12 13:46:33 +0800417#define PCI_FIND_CAP_TTL 0x48
418#define CAP_START_POS 0x40
419
Minghuan Lianed5b5802015-07-10 11:35:08 +0800420/* Extended Capabilities (PCI-X 2.0 and Express) */
421#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
422#define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
423#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
424
425#define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
426#define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
427#define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
428#define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
429#define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
430#define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
431#define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
432#define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
433#define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
434#define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
435#define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
436#define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
437#define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
438#define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
439#define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
440#define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
441#define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
442#define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
443#define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
444#define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
445#define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
446#define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
447#define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
448#define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
449#define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
450#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
451#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
Bin Meng5d544f92018-08-03 01:14:51 -0700452#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
453#define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */
454#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
455#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
Minghuan Lianed5b5802015-07-10 11:35:08 +0800456
wdenkc6097192002-11-03 00:24:07 +0000457/* Include the ID list */
458
459#include <pci_ids.h>
460
Paul Burtonfa5cec02013-11-08 11:18:47 +0000461#ifndef __ASSEMBLY__
462
Kumar Gala30e76d52008-10-21 08:36:08 -0500463#ifdef CONFIG_SYS_PCI_64BIT
464typedef u64 pci_addr_t;
465typedef u64 pci_size_t;
466#else
467typedef u32 pci_addr_t;
468typedef u32 pci_size_t;
469#endif
wdenkc6097192002-11-03 00:24:07 +0000470
Kumar Gala30e76d52008-10-21 08:36:08 -0500471struct pci_region {
472 pci_addr_t bus_start; /* Start on the bus */
473 phys_addr_t phys_start; /* Start in physical address space */
474 pci_size_t size; /* Size */
475 unsigned long flags; /* Resource flags */
476
477 pci_addr_t bus_lower;
wdenkc6097192002-11-03 00:24:07 +0000478};
479
480#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
481#define PCI_REGION_IO 0x00000001 /* PCI IO space */
482#define PCI_REGION_TYPE 0x00000001
Kumar Galaa1790122006-01-11 13:24:15 -0600483#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
wdenkc6097192002-11-03 00:24:07 +0000484
Kumar Galaff4e66e2009-02-06 09:49:31 -0600485#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
wdenkc6097192002-11-03 00:24:07 +0000486#define PCI_REGION_RO 0x00000200 /* Read-only memory */
487
Simon Glassbc3442a2013-06-11 11:14:33 -0700488static inline void pci_set_region(struct pci_region *reg,
Kumar Gala30e76d52008-10-21 08:36:08 -0500489 pci_addr_t bus_start,
Becky Bruce36f32672008-05-07 13:24:57 -0500490 phys_addr_t phys_start,
Kumar Gala30e76d52008-10-21 08:36:08 -0500491 pci_size_t size,
wdenkc6097192002-11-03 00:24:07 +0000492 unsigned long flags) {
493 reg->bus_start = bus_start;
494 reg->phys_start = phys_start;
495 reg->size = size;
496 reg->flags = flags;
497}
498
499typedef int pci_dev_t;
500
Simon Glassff3e0772015-03-05 12:25:25 -0700501#define PCI_BUS(d) (((d) >> 16) & 0xff)
502#define PCI_DEV(d) (((d) >> 11) & 0x1f)
503#define PCI_FUNC(d) (((d) >> 8) & 0x7)
504#define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
505#define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
506#define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
507#define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
508#define PCI_VENDEV(v, d) (((v) << 16) | (d))
509#define PCI_ANY_ID (~0)
wdenkc6097192002-11-03 00:24:07 +0000510
511struct pci_device_id {
Simon Glassaba92962015-07-06 16:47:44 -0600512 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
513 unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
514 unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
515 unsigned long driver_data; /* Data private to the driver */
wdenkc6097192002-11-03 00:24:07 +0000516};
517
518struct pci_controller;
519
520struct pci_config_table {
521 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
522 unsigned int class; /* Class ID, or PCI_ANY_ID */
523 unsigned int bus; /* Bus number, or PCI_ANY_ID */
524 unsigned int dev; /* Device number, or PCI_ANY_ID */
525 unsigned int func; /* Function number, or PCI_ANY_ID */
526
527 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
528 struct pci_config_table *);
529 unsigned long priv[3];
530};
531
Wolfgang Denk993a2272006-03-12 16:54:11 +0100532extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
533 struct pci_config_table *);
wdenkc6097192002-11-03 00:24:07 +0000534extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
535 struct pci_config_table *);
536
537#define MAX_PCI_REGIONS 7
538
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300539#define INDIRECT_TYPE_NO_PCIE_LINK 1
540
wdenkc6097192002-11-03 00:24:07 +0000541/*
542 * Structure of a PCI controller (host bridge)
Simon Glass54fe7b12015-11-26 19:51:21 -0700543 *
544 * With driver model this is dev_get_uclass_priv(bus)
wdenkc6097192002-11-03 00:24:07 +0000545 */
546struct pci_controller {
Simon Glassff3e0772015-03-05 12:25:25 -0700547#ifdef CONFIG_DM_PCI
548 struct udevice *bus;
549 struct udevice *ctlr;
550#else
wdenkc6097192002-11-03 00:24:07 +0000551 struct pci_controller *next;
Simon Glassff3e0772015-03-05 12:25:25 -0700552#endif
wdenkc6097192002-11-03 00:24:07 +0000553
554 int first_busno;
555 int last_busno;
556
557 volatile unsigned int *cfg_addr;
558 volatile unsigned char *cfg_data;
559
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300560 int indirect_type;
561
Simon Glassaec241d2015-06-07 08:50:40 -0600562 /*
563 * TODO(sjg@chromium.org): With driver model we use struct
564 * pci_controller for both the controller and any bridge devices
565 * attached to it. But there is only one region list and it is in the
566 * top-level controller.
567 *
568 * This could be changed so that struct pci_controller is only used
569 * for PCI controllers and a separate UCLASS (or perhaps
570 * UCLASS_PCI_GENERIC) is used for bridges.
571 */
wdenkc6097192002-11-03 00:24:07 +0000572 struct pci_region regions[MAX_PCI_REGIONS];
573 int region_count;
574
575 struct pci_config_table *config_table;
576
577 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
Simon Glassff3e0772015-03-05 12:25:25 -0700578#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000579 /* Low-level architecture-dependent routines */
580 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
581 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
582 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
583 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
584 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
585 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
Simon Glassff3e0772015-03-05 12:25:25 -0700586#endif
wdenkc6097192002-11-03 00:24:07 +0000587
588 /* Used by auto config */
Kumar Galaa1790122006-01-11 13:24:15 -0600589 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000590
Simon Glassff3e0772015-03-05 12:25:25 -0700591#ifndef CONFIG_DM_PCI
wdenkc7de8292002-11-19 11:04:11 +0000592 int current_busno;
Leo Liu10fa8d72011-01-19 19:50:47 +0800593
594 void *priv_data;
Simon Glassff3e0772015-03-05 12:25:25 -0700595#endif
wdenkc6097192002-11-03 00:24:07 +0000596};
597
Simon Glassff3e0772015-03-05 12:25:25 -0700598#ifndef CONFIG_DM_PCI
Simon Glassbc3442a2013-06-11 11:14:33 -0700599static inline void pci_set_ops(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000600 int (*read_byte)(struct pci_controller*,
601 pci_dev_t, int where, u8 *),
602 int (*read_word)(struct pci_controller*,
603 pci_dev_t, int where, u16 *),
604 int (*read_dword)(struct pci_controller*,
605 pci_dev_t, int where, u32 *),
606 int (*write_byte)(struct pci_controller*,
607 pci_dev_t, int where, u8),
608 int (*write_word)(struct pci_controller*,
609 pci_dev_t, int where, u16),
610 int (*write_dword)(struct pci_controller*,
611 pci_dev_t, int where, u32)) {
612 hose->read_byte = read_byte;
613 hose->read_word = read_word;
614 hose->read_dword = read_dword;
615 hose->write_byte = write_byte;
616 hose->write_word = write_word;
617 hose->write_dword = write_dword;
618}
Simon Glassff3e0772015-03-05 12:25:25 -0700619#endif
wdenkc6097192002-11-03 00:24:07 +0000620
Gabor Juhos842033e2013-05-30 07:06:12 +0000621#ifdef CONFIG_PCI_INDIRECT_BRIDGE
wdenkc6097192002-11-03 00:24:07 +0000622extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
Gabor Juhos842033e2013-05-30 07:06:12 +0000623#endif
wdenkc6097192002-11-03 00:24:07 +0000624
Simon Glass7e78b9e2015-11-29 13:18:05 -0700625#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Becky Bruce36f32672008-05-07 13:24:57 -0500626extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
Kumar Gala30e76d52008-10-21 08:36:08 -0500627 pci_addr_t addr, unsigned long flags);
628extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
629 phys_addr_t addr, unsigned long flags);
wdenkc6097192002-11-03 00:24:07 +0000630
631#define pci_phys_to_bus(dev, addr, flags) \
632 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
633#define pci_bus_to_phys(dev, addr, flags) \
634 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
635
Becky Bruce6e61fae2009-02-03 18:10:50 -0600636#define pci_virt_to_bus(dev, addr, flags) \
637 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
638 (virt_to_phys(addr)), (flags))
639#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
640 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
641 (addr), (flags)), \
642 (len), (map_flags))
643
644#define pci_phys_to_mem(dev, addr) \
645 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
646#define pci_mem_to_phys(dev, addr) \
647 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
648#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
649#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
650
651#define pci_virt_to_mem(dev, addr) \
652 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
653#define pci_mem_to_virt(dev, addr, len, map_flags) \
654 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
655#define pci_virt_to_io(dev, addr) \
656 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
657#define pci_io_to_virt(dev, addr, len, map_flags) \
658 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
wdenkc6097192002-11-03 00:24:07 +0000659
Simon Glassdc5740d2015-08-22 15:58:55 -0600660/* For driver model these are defined in macros in pci_compat.c */
wdenkc6097192002-11-03 00:24:07 +0000661extern int pci_hose_read_config_byte(struct pci_controller *hose,
662 pci_dev_t dev, int where, u8 *val);
663extern int pci_hose_read_config_word(struct pci_controller *hose,
664 pci_dev_t dev, int where, u16 *val);
665extern int pci_hose_read_config_dword(struct pci_controller *hose,
666 pci_dev_t dev, int where, u32 *val);
667extern int pci_hose_write_config_byte(struct pci_controller *hose,
668 pci_dev_t dev, int where, u8 val);
669extern int pci_hose_write_config_word(struct pci_controller *hose,
670 pci_dev_t dev, int where, u16 val);
671extern int pci_hose_write_config_dword(struct pci_controller *hose,
672 pci_dev_t dev, int where, u32 val);
Simon Glass3ba5f742015-11-26 19:51:30 -0700673#endif
wdenkc6097192002-11-03 00:24:07 +0000674
Simon Glassff3e0772015-03-05 12:25:25 -0700675#ifndef CONFIG_DM_PCI
wdenkc6097192002-11-03 00:24:07 +0000676extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
677extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
678extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
679extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
680extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
681extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
Simon Glassff3e0772015-03-05 12:25:25 -0700682#endif
wdenkc6097192002-11-03 00:24:07 +0000683
Simon Glass3ba5f742015-11-26 19:51:30 -0700684void pciauto_region_init(struct pci_region *res);
685void pciauto_region_align(struct pci_region *res, pci_size_t size);
686void pciauto_config_init(struct pci_controller *hose);
Tuomas Tynkkynen5ce9aca2018-05-14 23:50:05 +0300687
688/**
689 * pciauto_region_allocate() - Allocate resources from a PCI resource region
690 *
691 * Allocates @size bytes from the PCI resource @res. If @supports_64bit is
692 * false, the result will be guaranteed to fit in 32 bits.
693 *
694 * @res: PCI region to allocate from
695 * @size: Amount of bytes to allocate
696 * @bar: Returns the PCI bus address of the allocated resource
697 * @supports_64bit: Whether to allow allocations above the 32-bit boundary
698 * @return 0 if successful, -1 on failure
699 */
Simon Glass3ba5f742015-11-26 19:51:30 -0700700int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
Tuomas Tynkkynend71975a2018-05-14 19:38:13 +0300701 pci_addr_t *bar, bool supports_64bit);
Simon Glass3ba5f742015-11-26 19:51:30 -0700702
703#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
wdenkc6097192002-11-03 00:24:07 +0000704extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
705 pci_dev_t dev, int where, u8 *val);
706extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
707 pci_dev_t dev, int where, u16 *val);
708extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
709 pci_dev_t dev, int where, u8 val);
710extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
711 pci_dev_t dev, int where, u16 val);
712
Becky Bruce6e61fae2009-02-03 18:10:50 -0600713extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
wdenkc6097192002-11-03 00:24:07 +0000714extern void pci_register_hose(struct pci_controller* hose);
715extern struct pci_controller* pci_bus_to_hose(int bus);
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600716extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
Stuart Yodereeb5b1a2016-03-10 10:52:18 -0600717extern struct pci_controller *pci_get_hose_head(void);
wdenkc6097192002-11-03 00:24:07 +0000718
Thierry Reding4efe52b2014-11-12 18:26:49 -0700719extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000720extern int pci_hose_scan(struct pci_controller *hose);
721extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
722
wdenkc6097192002-11-03 00:24:07 +0000723extern void pciauto_setup_device(struct pci_controller *hose,
724 pci_dev_t dev, int bars_num,
725 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -0600726 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +0000727 struct pci_region *io);
Linus Walleija3a70722012-03-25 12:13:15 +0000728extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
729 pci_dev_t dev, int sub_bus);
730extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
731 pci_dev_t dev, int sub_bus);
Linus Walleija3a70722012-03-25 12:13:15 +0000732extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000733
734extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
735extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
Simon Glass250e0392015-01-27 22:13:27 -0700736pci_dev_t pci_find_class(unsigned int find_class, int index);
wdenkc6097192002-11-03 00:24:07 +0000737
738extern int pci_hose_config_device(struct pci_controller *hose,
739 pci_dev_t dev,
740 unsigned long io,
Kumar Gala30e76d52008-10-21 08:36:08 -0500741 pci_addr_t mem,
wdenkc6097192002-11-03 00:24:07 +0000742 unsigned long command);
743
Zhao Qiang287df012013-10-12 13:46:33 +0800744extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
745 int cap);
746extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
747 u8 hdr_type);
748extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
749 int cap);
750
Minghuan Lianed5b5802015-07-10 11:35:08 +0800751int pci_find_next_ext_capability(struct pci_controller *hose,
752 pci_dev_t dev, int start, int cap);
753int pci_hose_find_ext_capability(struct pci_controller *hose,
754 pci_dev_t dev, int cap);
755
Tim Harvey09918662014-08-07 22:49:56 -0700756#ifdef CONFIG_PCI_FIXUP_DEV
757extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
758 unsigned short vendor,
759 unsigned short device,
760 unsigned short class);
761#endif
Simon Glass3ba5f742015-11-26 19:51:30 -0700762#endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
Tim Harvey09918662014-08-07 22:49:56 -0700763
Peter Tyser983eb9d2010-10-29 17:59:27 -0500764const char * pci_class_str(u8 class);
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300765int pci_last_busno(void);
766
Jon Loeliger13a7fcd2006-10-19 11:33:52 -0500767#ifdef CONFIG_MPC85xx
768extern void pci_mpc85xx_init (struct pci_controller *hose);
769#endif
Paul Burtonfa5cec02013-11-08 11:18:47 +0000770
Tim Harvey6ecbe132017-05-12 12:58:41 -0700771#ifdef CONFIG_PCIE_IMX
772extern void imx_pcie_remove(void);
773#endif
774
Simon Glass3ba5f742015-11-26 19:51:30 -0700775#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
Simon Glasse8a552e2014-11-14 18:18:30 -0700776/**
777 * pci_write_bar32() - Write the address of a BAR including control bits
778 *
Simon Glass9d731c82016-01-18 20:19:15 -0700779 * This writes a raw address (with control bits) to a bar. This can be used
780 * with devices which require hard-coded addresses, not part of the normal
781 * PCI enumeration process.
Simon Glasse8a552e2014-11-14 18:18:30 -0700782 *
783 * @hose: PCI hose to use
784 * @dev: PCI device to update
785 * @barnum: BAR number (0-5)
786 * @addr: BAR address with control bits
787 */
788void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
Simon Glass9d731c82016-01-18 20:19:15 -0700789 u32 addr);
Simon Glasse8a552e2014-11-14 18:18:30 -0700790
791/**
792 * pci_read_bar32() - read the address of a bar
793 *
794 * @hose: PCI hose to use
795 * @dev: PCI device to inspect
796 * @barnum: BAR number (0-5)
797 * @return address of the bar, masking out any control bits
798 * */
799u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
800
Simon Glass4a2708a2015-01-14 21:37:04 -0700801/**
Simon Glassaab67242015-03-05 12:25:24 -0700802 * pci_hose_find_devices() - Find devices by vendor/device ID
803 *
804 * @hose: PCI hose to search
805 * @busnum: Bus number to search
806 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
807 * @indexp: Pointer to device index to find. To find the first matching
808 * device, pass 0; to find the second, pass 1, etc. This
809 * parameter is decremented for each non-matching device so
810 * can be called repeatedly.
811 */
812pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
813 struct pci_device_id *ids, int *indexp);
Simon Glass3ba5f742015-11-26 19:51:30 -0700814#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
Simon Glassaab67242015-03-05 12:25:24 -0700815
Simon Glassff3e0772015-03-05 12:25:25 -0700816/* Access sizes for PCI reads and writes */
817enum pci_size_t {
818 PCI_SIZE_8,
819 PCI_SIZE_16,
820 PCI_SIZE_32,
821};
822
823struct udevice;
824
825#ifdef CONFIG_DM_PCI
826/**
827 * struct pci_child_platdata - information stored about each PCI device
828 *
829 * Every device on a PCI bus has this per-child data.
830 *
Simon Glassbcbe3d12015-09-28 23:32:01 -0600831 * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
Simon Glassff3e0772015-03-05 12:25:25 -0700832 * PCI bus (i.e. UCLASS_PCI)
833 *
834 * @devfn: Encoded device and function index - see PCI_DEVFN()
835 * @vendor: PCI vendor ID (see pci_ids.h)
836 * @device: PCI device ID (see pci_ids.h)
837 * @class: PCI class, 3 bytes: (base, sub, prog-if)
838 */
839struct pci_child_platdata {
840 int devfn;
841 unsigned short vendor;
842 unsigned short device;
843 unsigned int class;
844};
845
846/* PCI bus operations */
847struct dm_pci_ops {
848 /**
849 * read_config() - Read a PCI configuration value
850 *
851 * PCI buses must support reading and writing configuration values
852 * so that the bus can be scanned and its devices configured.
853 *
854 * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
855 * If bridges exist it is possible to use the top-level bus to
856 * access a sub-bus. In that case @bus will be the top-level bus
857 * and PCI_BUS(bdf) will be a different (higher) value
858 *
859 * @bus: Bus to read from
860 * @bdf: Bus, device and function to read
861 * @offset: Byte offset within the device's configuration space
862 * @valuep: Place to put the returned value
863 * @size: Access size
864 * @return 0 if OK, -ve on error
865 */
866 int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
867 ulong *valuep, enum pci_size_t size);
868 /**
869 * write_config() - Write a PCI configuration value
870 *
871 * @bus: Bus to write to
872 * @bdf: Bus, device and function to write
873 * @offset: Byte offset within the device's configuration space
874 * @value: Value to write
875 * @size: Access size
876 * @return 0 if OK, -ve on error
877 */
878 int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
879 ulong value, enum pci_size_t size);
880};
881
882/* Get access to a PCI bus' operations */
883#define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
884
885/**
Simon Glass21ccce12015-11-29 13:17:47 -0700886 * dm_pci_get_bdf() - Get the BDF value for a device
Simon Glass4b515e42015-07-06 16:47:46 -0600887 *
888 * @dev: Device to check
889 * @return bus/device/function value (see PCI_BDF())
890 */
Simon Glass21ccce12015-11-29 13:17:47 -0700891pci_dev_t dm_pci_get_bdf(struct udevice *dev);
Simon Glass4b515e42015-07-06 16:47:46 -0600892
893/**
Simon Glassff3e0772015-03-05 12:25:25 -0700894 * pci_bind_bus_devices() - scan a PCI bus and bind devices
895 *
896 * Scan a PCI bus looking for devices. Bind each one that is found. If
897 * devices are already bound that match the scanned devices, just update the
898 * child data so that the device can be used correctly (this happens when
899 * the device tree describes devices we expect to see on the bus).
900 *
901 * Devices that are bound in this way will use a generic PCI driver which
902 * does nothing. The device can still be accessed but will not provide any
903 * driver interface.
904 *
905 * @bus: Bus containing devices to bind
906 * @return 0 if OK, -ve on error
907 */
908int pci_bind_bus_devices(struct udevice *bus);
909
910/**
911 * pci_auto_config_devices() - configure bus devices ready for use
912 *
913 * This works through all devices on a bus by scanning the driver model
914 * data structures (normally these have been set up by pci_bind_bus_devices()
915 * earlier).
916 *
917 * Space is allocated for each PCI base address register (BAR) so that the
918 * devices are mapped into memory and I/O space ready for use.
919 *
920 * @bus: Bus containing devices to bind
921 * @return 0 if OK, -ve on error
922 */
923int pci_auto_config_devices(struct udevice *bus);
924
925/**
Simon Glassf3f1fae2015-11-29 13:17:48 -0700926 * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
Simon Glassff3e0772015-03-05 12:25:25 -0700927 *
928 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
929 * @devp: Returns the device for this address, if found
930 * @return 0 if OK, -ENODEV if not found
931 */
Simon Glassf3f1fae2015-11-29 13:17:48 -0700932int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
Simon Glassff3e0772015-03-05 12:25:25 -0700933
934/**
935 * pci_bus_find_devfn() - Find a device on a bus
936 *
937 * @find_devfn: PCI device address (device and function only)
938 * @devp: Returns the device for this address, if found
939 * @return 0 if OK, -ENODEV if not found
940 */
941int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
942 struct udevice **devp);
943
944/**
Simon Glass76c3fbc2015-08-10 07:05:04 -0600945 * pci_find_first_device() - return the first available PCI device
946 *
947 * This function and pci_find_first_device() allow iteration through all
948 * available PCI devices on all buses. Assuming there are any, this will
949 * return the first one.
950 *
951 * @devp: Set to the first available device, or NULL if no more are left
952 * or we got an error
953 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
954 */
955int pci_find_first_device(struct udevice **devp);
956
957/**
958 * pci_find_next_device() - return the next available PCI device
959 *
960 * Finds the next available PCI device after the one supplied, or sets @devp
961 * to NULL if there are no more.
962 *
963 * @devp: On entry, the last device returned. Set to the next available
964 * device, or NULL if no more are left or we got an error
965 * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
966 */
967int pci_find_next_device(struct udevice **devp);
968
969/**
Simon Glassff3e0772015-03-05 12:25:25 -0700970 * pci_get_ff() - Returns a mask for the given access size
971 *
972 * @size: Access size
973 * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
974 * PCI_SIZE_32
975 */
976int pci_get_ff(enum pci_size_t size);
977
978/**
979 * pci_bus_find_devices () - Find devices on a bus
980 *
981 * @bus: Bus to search
982 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
983 * @indexp: Pointer to device index to find. To find the first matching
984 * device, pass 0; to find the second, pass 1, etc. This
985 * parameter is decremented for each non-matching device so
986 * can be called repeatedly.
987 * @devp: Returns matching device if found
988 * @return 0 if found, -ENODEV if not
989 */
990int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
991 int *indexp, struct udevice **devp);
992
993/**
994 * pci_find_device_id() - Find a device on any bus
995 *
996 * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
997 * @index: Index number of device to find, 0 for the first match, 1 for
998 * the second, etc.
999 * @devp: Returns matching device if found
1000 * @return 0 if found, -ENODEV if not
1001 */
1002int pci_find_device_id(struct pci_device_id *ids, int index,
1003 struct udevice **devp);
1004
1005/**
1006 * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
1007 *
1008 * This probes the given bus which causes it to be scanned for devices. The
1009 * devices will be bound but not probed.
1010 *
1011 * @hose specifies the PCI hose that will be used for the scan. This is
1012 * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
1013 * in @bdf, and is a subordinate bus reachable from @hose.
1014 *
1015 * @hose: PCI hose to scan
1016 * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
1017 * @return 0 if OK, -ve on error
1018 */
Simon Glass5e23b8b2015-11-29 13:17:49 -07001019int dm_pci_hose_probe_bus(struct udevice *bus);
Simon Glassff3e0772015-03-05 12:25:25 -07001020
1021/**
1022 * pci_bus_read_config() - Read a configuration value from a device
1023 *
1024 * TODO(sjg@chromium.org): We should be able to pass just a device and have
1025 * it do the right thing. It would be good to have that function also.
1026 *
1027 * @bus: Bus to read from
1028 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001029 * @offset: Register offset to read
Simon Glassff3e0772015-03-05 12:25:25 -07001030 * @valuep: Place to put the returned value
1031 * @size: Access size
1032 * @return 0 if OK, -ve on error
1033 */
1034int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
1035 unsigned long *valuep, enum pci_size_t size);
1036
1037/**
1038 * pci_bus_write_config() - Write a configuration value to a device
1039 *
1040 * @bus: Bus to write from
1041 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
Simon Glass4974a6f2016-03-06 19:27:53 -07001042 * @offset: Register offset to write
Simon Glassff3e0772015-03-05 12:25:25 -07001043 * @value: Value to write
1044 * @size: Access size
1045 * @return 0 if OK, -ve on error
1046 */
1047int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
1048 unsigned long value, enum pci_size_t size);
1049
Simon Glass66afb4e2015-08-10 07:05:03 -06001050/**
Simon Glass319dba12016-03-06 19:27:52 -07001051 * pci_bus_clrset_config32() - Update a configuration value for a device
1052 *
1053 * The register at @offset is updated to (oldvalue & ~clr) | set.
1054 *
1055 * @bus: Bus to access
1056 * @bdf: PCI device address: bus, device and function -see PCI_BDF()
1057 * @offset: Register offset to update
1058 * @clr: Bits to clear
1059 * @set: Bits to set
1060 * @return 0 if OK, -ve on error
1061 */
1062int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
1063 u32 clr, u32 set);
1064
1065/**
Simon Glass66afb4e2015-08-10 07:05:03 -06001066 * Driver model PCI config access functions. Use these in preference to others
1067 * when you have a valid device
1068 */
1069int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
1070 enum pci_size_t size);
1071
1072int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
1073int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
1074int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
1075
1076int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
1077 enum pci_size_t size);
1078
1079int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
1080int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
1081int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
1082
Simon Glass319dba12016-03-06 19:27:52 -07001083/**
1084 * These permit convenient read/modify/write on PCI configuration. The
1085 * register is updated to (oldvalue & ~clr) | set.
1086 */
1087int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
1088int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
1089int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
1090
Simon Glassff3e0772015-03-05 12:25:25 -07001091/*
1092 * The following functions provide access to the above without needing the
1093 * size parameter. We are trying to encourage the use of the 8/16/32-style
1094 * functions, rather than byte/word/dword. But both are supported.
1095 */
1096int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
Bin Meng308143e2016-02-02 05:58:07 -08001097int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
1098int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
1099int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
1100int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
1101int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
Simon Glassff3e0772015-03-05 12:25:25 -07001102
Tuomas Tynkkynenbadb9922017-09-19 23:18:03 +03001103/**
1104 * pci_generic_mmap_write_config() - Generic helper for writing to
1105 * memory-mapped PCI configuration space.
1106 * @bus: Pointer to the PCI bus
1107 * @addr_f: Callback for calculating the config space address
1108 * @bdf: Identifies the PCI device to access
1109 * @offset: The offset into the device's configuration space
1110 * @value: The value to write
1111 * @size: Indicates the size of access to perform
1112 *
1113 * Write the value @value of size @size from offset @offset within the
1114 * configuration space of the device identified by the bus, device & function
1115 * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
1116 * responsible for calculating the CPU address of the respective configuration
1117 * space offset.
1118 *
1119 * Return: 0 on success, else -EINVAL
1120 */
1121int pci_generic_mmap_write_config(
1122 struct udevice *bus,
1123 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1124 pci_dev_t bdf,
1125 uint offset,
1126 ulong value,
1127 enum pci_size_t size);
1128
1129/**
1130 * pci_generic_mmap_read_config() - Generic helper for reading from
1131 * memory-mapped PCI configuration space.
1132 * @bus: Pointer to the PCI bus
1133 * @addr_f: Callback for calculating the config space address
1134 * @bdf: Identifies the PCI device to access
1135 * @offset: The offset into the device's configuration space
1136 * @valuep: A pointer at which to store the read value
1137 * @size: Indicates the size of access to perform
1138 *
1139 * Read a value of size @size from offset @offset within the configuration
1140 * space of the device identified by the bus, device & function numbers in @bdf
1141 * on the PCI bus @bus. The callback function @addr_f is responsible for
1142 * calculating the CPU address of the respective configuration space offset.
1143 *
1144 * Return: 0 on success, else -EINVAL
1145 */
1146int pci_generic_mmap_read_config(
1147 struct udevice *bus,
1148 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
1149 pci_dev_t bdf,
1150 uint offset,
1151 ulong *valuep,
1152 enum pci_size_t size);
1153
Simon Glass3ba5f742015-11-26 19:51:30 -07001154#ifdef CONFIG_DM_PCI_COMPAT
Simon Glassff3e0772015-03-05 12:25:25 -07001155/* Compatibility with old naming */
1156static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
1157 u32 value)
1158{
1159 return pci_write_config32(pcidev, offset, value);
1160}
1161
Simon Glassff3e0772015-03-05 12:25:25 -07001162/* Compatibility with old naming */
1163static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
1164 u16 value)
1165{
1166 return pci_write_config16(pcidev, offset, value);
1167}
1168
Simon Glassff3e0772015-03-05 12:25:25 -07001169/* Compatibility with old naming */
1170static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
1171 u8 value)
1172{
1173 return pci_write_config8(pcidev, offset, value);
1174}
1175
Simon Glassff3e0772015-03-05 12:25:25 -07001176/* Compatibility with old naming */
1177static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
1178 u32 *valuep)
1179{
1180 return pci_read_config32(pcidev, offset, valuep);
1181}
1182
Simon Glassff3e0772015-03-05 12:25:25 -07001183/* Compatibility with old naming */
1184static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
1185 u16 *valuep)
1186{
1187 return pci_read_config16(pcidev, offset, valuep);
1188}
1189
Simon Glassff3e0772015-03-05 12:25:25 -07001190/* Compatibility with old naming */
1191static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
1192 u8 *valuep)
1193{
1194 return pci_read_config8(pcidev, offset, valuep);
1195}
Simon Glass3ba5f742015-11-26 19:51:30 -07001196#endif /* CONFIG_DM_PCI_COMPAT */
1197
1198/**
1199 * dm_pciauto_config_device() - configure a device ready for use
1200 *
1201 * Space is allocated for each PCI base address register (BAR) so that the
1202 * devices are mapped into memory and I/O space ready for use.
1203 *
1204 * @dev: Device to configure
1205 * @return 0 if OK, -ve on error
1206 */
1207int dm_pciauto_config_device(struct udevice *dev);
1208
Simon Glass36d0d3b2015-03-05 12:25:28 -07001209/**
Simon Glass9289db62015-11-19 20:26:59 -07001210 * pci_conv_32_to_size() - convert a 32-bit read value to the given size
1211 *
1212 * Some PCI buses must always perform 32-bit reads. The data must then be
1213 * shifted and masked to reflect the required access size and offset. This
1214 * function performs this transformation.
1215 *
1216 * @value: Value to transform (32-bit value read from @offset & ~3)
1217 * @offset: Register offset that was read
1218 * @size: Required size of the result
1219 * @return the value that would have been obtained if the read had been
1220 * performed at the given offset with the correct size
1221 */
1222ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
1223
1224/**
1225 * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
1226 *
1227 * Some PCI buses must always perform 32-bit writes. To emulate a smaller
1228 * write the old 32-bit data must be read, updated with the required new data
1229 * and written back as a 32-bit value. This function performs the
1230 * transformation from the old value to the new value.
1231 *
1232 * @value: Value to transform (32-bit value read from @offset & ~3)
1233 * @offset: Register offset that should be written
1234 * @size: Required size of the write
1235 * @return the value that should be written as a 32-bit access to @offset & ~3.
1236 */
1237ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1238 enum pci_size_t size);
1239
1240/**
Simon Glass9f60fb02015-11-19 20:27:00 -07001241 * pci_get_controller() - obtain the controller to use for a bus
1242 *
1243 * @dev: Device to check
1244 * @return pointer to the controller device for this bus
1245 */
1246struct udevice *pci_get_controller(struct udevice *dev);
1247
1248/**
Simon Glassf9260332015-11-19 20:27:01 -07001249 * pci_get_regions() - obtain pointers to all the region types
1250 *
1251 * @dev: Device to check
1252 * @iop: Returns a pointer to the I/O region, or NULL if none
1253 * @memp: Returns a pointer to the memory region, or NULL if none
1254 * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
1255 * @return the number of non-NULL regions returned, normally 3
1256 */
1257int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1258 struct pci_region **memp, struct pci_region **prefp);
1259
1260/**
Simon Glass9d731c82016-01-18 20:19:15 -07001261 * dm_pci_write_bar32() - Write the address of a BAR
1262 *
1263 * This writes a raw address to a bar
1264 *
1265 * @dev: PCI device to update
1266 * @barnum: BAR number (0-5)
1267 * @addr: BAR address
1268 */
1269void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
1270
1271/**
Simon Glassbab17cf2015-11-29 13:17:53 -07001272 * dm_pci_read_bar32() - read a base address register from a device
1273 *
1274 * @dev: Device to check
1275 * @barnum: Bar number to read (numbered from 0)
1276 * @return: value of BAR
1277 */
1278u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
1279
1280/**
Simon Glass21d1fe72015-11-29 13:18:03 -07001281 * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
1282 *
1283 * @dev: Device containing the PCI address
1284 * @addr: PCI address to convert
1285 * @flags: Flags for the region type (PCI_REGION_...)
1286 * @return physical address corresponding to that PCI bus address
1287 */
1288phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
1289 unsigned long flags);
1290
1291/**
1292 * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
1293 *
1294 * @dev: Device containing the bus address
1295 * @addr: Physical address to convert
1296 * @flags: Flags for the region type (PCI_REGION_...)
1297 * @return PCI bus address corresponding to that physical address
1298 */
1299pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
1300 unsigned long flags);
1301
1302/**
1303 * dm_pci_map_bar() - get a virtual address associated with a BAR region
1304 *
1305 * Looks up a base address register and finds the physical memory address
1306 * that corresponds to it
1307 *
1308 * @dev: Device to check
1309 * @bar: Bar number to read (numbered from 0)
1310 * @flags: Flags for the region type (PCI_REGION_...)
1311 * @return: pointer to the virtual address to use
1312 */
1313void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
1314
Bin Mengdac01fd2018-08-03 01:14:52 -07001315/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001316 * dm_pci_find_next_capability() - find a capability starting from an offset
1317 *
1318 * Tell if a device supports a given PCI capability. Returns the
1319 * address of the requested capability structure within the device's
1320 * PCI configuration space or 0 in case the device does not support it.
1321 *
1322 * Possible values for @cap:
1323 *
1324 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1325 * %PCI_CAP_ID_PCIX PCI-X
1326 * %PCI_CAP_ID_EXP PCI Express
1327 * %PCI_CAP_ID_MSIX MSI-X
1328 *
1329 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1330 *
1331 * @dev: PCI device to query
1332 * @start: offset to start from
1333 * @cap: capability code
1334 * @return: capability address or 0 if not supported
1335 */
1336int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap);
1337
1338/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001339 * dm_pci_find_capability() - find a capability
1340 *
1341 * Tell if a device supports a given PCI capability. Returns the
1342 * address of the requested capability structure within the device's
1343 * PCI configuration space or 0 in case the device does not support it.
1344 *
1345 * Possible values for @cap:
1346 *
1347 * %PCI_CAP_ID_MSI Message Signalled Interrupts
1348 * %PCI_CAP_ID_PCIX PCI-X
1349 * %PCI_CAP_ID_EXP PCI Express
1350 * %PCI_CAP_ID_MSIX MSI-X
1351 *
1352 * See PCI_CAP_ID_xxx for the complete capability ID codes.
1353 *
1354 * @dev: PCI device to query
1355 * @cap: capability code
1356 * @return: capability address or 0 if not supported
1357 */
1358int dm_pci_find_capability(struct udevice *dev, int cap);
1359
1360/**
Bin Menga8c5f8d2018-10-15 02:21:21 -07001361 * dm_pci_find_next_ext_capability() - find an extended capability
1362 * starting from an offset
1363 *
1364 * Tell if a device supports a given PCI express extended capability.
1365 * Returns the address of the requested extended capability structure
1366 * within the device's PCI configuration space or 0 in case the device
1367 * does not support it.
1368 *
1369 * Possible values for @cap:
1370 *
1371 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1372 * %PCI_EXT_CAP_ID_VC Virtual Channel
1373 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1374 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1375 *
1376 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1377 *
1378 * @dev: PCI device to query
1379 * @start: offset to start from
1380 * @cap: extended capability code
1381 * @return: extended capability address or 0 if not supported
1382 */
1383int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap);
1384
1385/**
Bin Mengdac01fd2018-08-03 01:14:52 -07001386 * dm_pci_find_ext_capability() - find an extended capability
1387 *
1388 * Tell if a device supports a given PCI express extended capability.
1389 * Returns the address of the requested extended capability structure
1390 * within the device's PCI configuration space or 0 in case the device
1391 * does not support it.
1392 *
1393 * Possible values for @cap:
1394 *
1395 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
1396 * %PCI_EXT_CAP_ID_VC Virtual Channel
1397 * %PCI_EXT_CAP_ID_DSN Device Serial Number
1398 * %PCI_EXT_CAP_ID_PWR Power Budgeting
1399 *
1400 * See PCI_EXT_CAP_ID_xxx for the complete extended capability ID codes.
1401 *
1402 * @dev: PCI device to query
1403 * @cap: extended capability code
1404 * @return: extended capability address or 0 if not supported
1405 */
1406int dm_pci_find_ext_capability(struct udevice *dev, int cap);
1407
Simon Glass21d1fe72015-11-29 13:18:03 -07001408#define dm_pci_virt_to_bus(dev, addr, flags) \
1409 dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
1410#define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
1411 map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
1412 (len), (map_flags))
1413
1414#define dm_pci_phys_to_mem(dev, addr) \
1415 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
1416#define dm_pci_mem_to_phys(dev, addr) \
1417 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
1418#define dm_pci_phys_to_io(dev, addr) \
1419 dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
1420#define dm_pci_io_to_phys(dev, addr) \
1421 dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
1422
1423#define dm_pci_virt_to_mem(dev, addr) \
1424 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
1425#define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
1426 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
1427#define dm_pci_virt_to_io(dev, addr) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001428 dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
Simon Glass21d1fe72015-11-29 13:18:03 -07001429#define dm_pci_io_to_virt(dev, addr, len, map_flags) \
Simon Glass4974a6f2016-03-06 19:27:53 -07001430 dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
Simon Glass21d1fe72015-11-29 13:18:03 -07001431
1432/**
Simon Glass5c0bf642015-11-29 13:17:50 -07001433 * dm_pci_find_device() - find a device by vendor/device ID
1434 *
1435 * @vendor: Vendor ID
1436 * @device: Device ID
1437 * @index: 0 to find the first match, 1 for second, etc.
1438 * @devp: Returns pointer to the device, if found
1439 * @return 0 if found, -ve on error
1440 */
1441int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
1442 struct udevice **devp);
1443
1444/**
Simon Glassa0eb8352015-11-29 13:17:52 -07001445 * dm_pci_find_class() - find a device by class
1446 *
1447 * @find_class: 3-byte (24-bit) class value to find
1448 * @index: 0 to find the first match, 1 for second, etc.
1449 * @devp: Returns pointer to the device, if found
1450 * @return 0 if found, -ve on error
1451 */
1452int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
1453
1454/**
Simon Glass36d0d3b2015-03-05 12:25:28 -07001455 * struct dm_pci_emul_ops - PCI device emulator operations
1456 */
1457struct dm_pci_emul_ops {
1458 /**
1459 * get_devfn(): Check which device and function this emulators
1460 *
1461 * @dev: device to check
1462 * @return the device and function this emulates, or -ve on error
1463 */
1464 int (*get_devfn)(struct udevice *dev);
1465 /**
1466 * read_config() - Read a PCI configuration value
1467 *
1468 * @dev: Emulated device to read from
1469 * @offset: Byte offset within the device's configuration space
1470 * @valuep: Place to put the returned value
1471 * @size: Access size
1472 * @return 0 if OK, -ve on error
1473 */
1474 int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
1475 enum pci_size_t size);
1476 /**
1477 * write_config() - Write a PCI configuration value
1478 *
1479 * @dev: Emulated device to write to
1480 * @offset: Byte offset within the device's configuration space
1481 * @value: Value to write
1482 * @size: Access size
1483 * @return 0 if OK, -ve on error
1484 */
1485 int (*write_config)(struct udevice *dev, uint offset, ulong value,
1486 enum pci_size_t size);
1487 /**
1488 * read_io() - Read a PCI I/O value
1489 *
1490 * @dev: Emulated device to read from
1491 * @addr: I/O address to read
1492 * @valuep: Place to put the returned value
1493 * @size: Access size
1494 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1495 * other -ve value on error
1496 */
1497 int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
1498 enum pci_size_t size);
1499 /**
1500 * write_io() - Write a PCI I/O value
1501 *
1502 * @dev: Emulated device to write from
1503 * @addr: I/O address to write
1504 * @value: Value to write
1505 * @size: Access size
1506 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1507 * other -ve value on error
1508 */
1509 int (*write_io)(struct udevice *dev, unsigned int addr,
1510 ulong value, enum pci_size_t size);
1511 /**
1512 * map_physmem() - Map a device into sandbox memory
1513 *
1514 * @dev: Emulated device to map
1515 * @addr: Memory address, normally corresponding to a PCI BAR.
1516 * The device should have been configured to have a BAR
1517 * at this address.
1518 * @lenp: On entry, the size of the area to map, On exit it is
1519 * updated to the size actually mapped, which may be less
1520 * if the device has less space
1521 * @ptrp: Returns a pointer to the mapped address. The device's
1522 * space can be accessed as @lenp bytes starting here
1523 * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
1524 * other -ve value on error
1525 */
1526 int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
1527 unsigned long *lenp, void **ptrp);
1528 /**
1529 * unmap_physmem() - undo a memory mapping
1530 *
1531 * This must be called after map_physmem() to undo the mapping.
1532 * Some devices can use this to check what has been written into
1533 * their mapped memory and perform an operations they require on it.
1534 * In this way, map/unmap can be used as a sort of handshake between
1535 * the emulated device and its users.
1536 *
1537 * @dev: Emuated device to unmap
1538 * @vaddr: Mapped memory address, as passed to map_physmem()
1539 * @len: Size of area mapped, as returned by map_physmem()
1540 * @return 0 if OK, -ve on error
1541 */
1542 int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
1543 unsigned long len);
1544};
1545
1546/* Get access to a PCI device emulator's operations */
1547#define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
1548
1549/**
1550 * sandbox_pci_get_emul() - Get the emulation device for a PCI device
1551 *
1552 * Searches for a suitable emulator for the given PCI bus device
1553 *
1554 * @bus: PCI bus to search
1555 * @find_devfn: PCI device and function address (PCI_DEVFN())
Bin Meng43459982018-08-03 01:14:45 -07001556 * @containerp: Returns container device if found
Simon Glass36d0d3b2015-03-05 12:25:28 -07001557 * @emulp: Returns emulated device if found
1558 * @return 0 if found, -ENODEV if not found
1559 */
1560int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
Bin Meng43459982018-08-03 01:14:45 -07001561 struct udevice **containerp, struct udevice **emulp);
Simon Glass36d0d3b2015-03-05 12:25:28 -07001562
Stefan Roeseb5214202019-01-25 11:52:42 +01001563/**
1564 * pci_get_devfn() - Extract the devfn from fdt_pci_addr of the device
1565 *
1566 * Get devfn from fdt_pci_addr of the specifified device
1567 *
1568 * @dev: PCI device
1569 * @return devfn in bits 15...8 if found, -ENODEV if not found
1570 */
1571int pci_get_devfn(struct udevice *dev);
1572
Simon Glassaba92962015-07-06 16:47:44 -06001573#endif /* CONFIG_DM_PCI */
1574
1575/**
1576 * PCI_DEVICE - macro used to describe a specific pci device
1577 * @vend: the 16 bit PCI Vendor ID
1578 * @dev: the 16 bit PCI Device ID
1579 *
1580 * This macro is used to create a struct pci_device_id that matches a
1581 * specific device. The subvendor and subdevice fields will be set to
1582 * PCI_ANY_ID.
1583 */
1584#define PCI_DEVICE(vend, dev) \
1585 .vendor = (vend), .device = (dev), \
1586 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1587
1588/**
1589 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
1590 * @vend: the 16 bit PCI Vendor ID
1591 * @dev: the 16 bit PCI Device ID
1592 * @subvend: the 16 bit PCI Subvendor ID
1593 * @subdev: the 16 bit PCI Subdevice ID
1594 *
1595 * This macro is used to create a struct pci_device_id that matches a
1596 * specific device with subsystem information.
1597 */
1598#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
1599 .vendor = (vend), .device = (dev), \
1600 .subvendor = (subvend), .subdevice = (subdev)
1601
1602/**
1603 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
1604 * @dev_class: the class, subclass, prog-if triple for this device
1605 * @dev_class_mask: the class mask for this device
1606 *
1607 * This macro is used to create a struct pci_device_id that matches a
1608 * specific PCI class. The vendor, device, subvendor, and subdevice
1609 * fields will be set to PCI_ANY_ID.
1610 */
1611#define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
1612 .class = (dev_class), .class_mask = (dev_class_mask), \
1613 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
1614 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
1615
1616/**
1617 * PCI_VDEVICE - macro used to describe a specific pci device in short form
1618 * @vend: the vendor name
1619 * @dev: the 16 bit PCI Device ID
1620 *
1621 * This macro is used to create a struct pci_device_id that matches a
1622 * specific PCI device. The subvendor, and subdevice fields will be set
1623 * to PCI_ANY_ID. The macro allows the next field to follow as the device
1624 * private data.
1625 */
1626
1627#define PCI_VDEVICE(vend, dev) \
1628 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
1629 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
1630
1631/**
1632 * struct pci_driver_entry - Matches a driver to its pci_device_id list
1633 * @driver: Driver to use
1634 * @match: List of match records for this driver, terminated by {}
1635 */
1636struct pci_driver_entry {
1637 struct driver *driver;
1638 const struct pci_device_id *match;
1639};
1640
1641#define U_BOOT_PCI_DEVICE(__name, __match) \
1642 ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
1643 .driver = llsym(struct driver, __name, driver), \
1644 .match = __match, \
1645 }
Simon Glassff3e0772015-03-05 12:25:25 -07001646
Paul Burtonfa5cec02013-11-08 11:18:47 +00001647#endif /* __ASSEMBLY__ */
1648#endif /* _PCI_H */