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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * aloong with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef _PCI_H
28#define _PCI_H
29
30/*
31 * Under PCI, each device has 256 bytes of configuration address space,
32 * of which the first 64 bytes are standardized as follows:
33 */
34#define PCI_VENDOR_ID 0x00 /* 16 bits */
35#define PCI_DEVICE_ID 0x02 /* 16 bits */
36#define PCI_COMMAND 0x04 /* 16 bits */
37#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
38#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
39#define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
40#define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
41#define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
42#define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
43#define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
44#define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
45#define PCI_COMMAND_SERR 0x100 /* Enable SERR */
46#define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
47
48#define PCI_STATUS 0x06 /* 16 bits */
49#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
50#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
51#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
52#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
53#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
54#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
55#define PCI_STATUS_DEVSEL_FAST 0x000
56#define PCI_STATUS_DEVSEL_MEDIUM 0x200
57#define PCI_STATUS_DEVSEL_SLOW 0x400
58#define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
59#define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
60#define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
61#define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
62#define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
63
64#define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
65 revision */
66#define PCI_REVISION_ID 0x08 /* Revision ID */
67#define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
68#define PCI_CLASS_DEVICE 0x0a /* Device class */
69#define PCI_CLASS_CODE 0x0b /* Device class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000070#define PCI_CLASS_CODE_TOO_OLD 0x00
71#define PCI_CLASS_CODE_STORAGE 0x01
72#define PCI_CLASS_CODE_NETWORK 0x02
73#define PCI_CLASS_CODE_DISPLAY 0x03
74#define PCI_CLASS_CODE_MULTIMEDIA 0x04
75#define PCI_CLASS_CODE_MEMORY 0x05
76#define PCI_CLASS_CODE_BRIDGE 0x06
77#define PCI_CLASS_CODE_COMM 0x07
78#define PCI_CLASS_CODE_PERIPHERAL 0x08
79#define PCI_CLASS_CODE_INPUT 0x09
80#define PCI_CLASS_CODE_DOCKING 0x0A
81#define PCI_CLASS_CODE_PROCESSOR 0x0B
82#define PCI_CLASS_CODE_SERIAL 0x0C
83#define PCI_CLASS_CODE_WIRELESS 0x0D
84#define PCI_CLASS_CODE_I2O 0x0E
85#define PCI_CLASS_CODE_SATELLITE 0x0F
86#define PCI_CLASS_CODE_CRYPTO 0x10
87#define PCI_CLASS_CODE_DATA 0x11
88/* Base Class 0x12 - 0xFE is reserved */
89#define PCI_CLASS_CODE_OTHER 0xFF
90
wdenkc6097192002-11-03 00:24:07 +000091#define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
Bill Richardson55ae10f2012-10-20 11:44:34 +000092#define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
93#define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
94#define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
95#define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
96#define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
97#define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
98#define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
99#define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
100#define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
101#define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
102#define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
103#define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
104#define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
105#define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
106#define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
107#define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
108#define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
109#define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
110#define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
111#define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
112#define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
113#define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
114#define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
115#define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
116#define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
117#define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
118#define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
119#define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
120#define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
121#define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
122#define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
123#define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
124#define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
125#define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
126#define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
127#define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
128#define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
129#define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
130#define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
131#define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
132#define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
133#define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
134#define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
135#define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
136#define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
137#define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
138#define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
139#define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
140#define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
141#define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
142#define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
143#define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
144#define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
145#define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
146#define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
147#define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
148#define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
149#define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
150#define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
151#define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
152#define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
153#define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
154#define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
155#define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
156#define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
157#define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
158#define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
159#define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
160#define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
161#define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
162#define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
163#define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
164#define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
165#define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
166#define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
167#define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
168#define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
169#define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
170#define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
171#define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
172#define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
173#define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
174#define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
175#define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
176#define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
177#define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
178#define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
179#define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
180#define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
181#define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
182#define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
183#define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
184#define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
185#define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
186#define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
187#define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
188#define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
189#define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
190#define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
191#define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
192#define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
193#define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
wdenkc6097192002-11-03 00:24:07 +0000194
195#define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
196#define PCI_LATENCY_TIMER 0x0d /* 8 bits */
197#define PCI_HEADER_TYPE 0x0e /* 8 bits */
198#define PCI_HEADER_TYPE_NORMAL 0
199#define PCI_HEADER_TYPE_BRIDGE 1
200#define PCI_HEADER_TYPE_CARDBUS 2
201
202#define PCI_BIST 0x0f /* 8 bits */
203#define PCI_BIST_CODE_MASK 0x0f /* Return result */
204#define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
205#define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
206
207/*
208 * Base addresses specify locations in memory or I/O space.
209 * Decoded size can be determined by writing a value of
210 * 0xffffffff to the register, and reading it back. Only
211 * 1 bits are decoded.
212 */
213#define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
214#define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
215#define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
216#define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
217#define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
218#define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
219#define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
220#define PCI_BASE_ADDRESS_SPACE_IO 0x01
221#define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
222#define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
223#define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
224#define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
225#define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
226#define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
Kumar Gala30e76d52008-10-21 08:36:08 -0500227#define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
228#define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
wdenkc6097192002-11-03 00:24:07 +0000229/* bit 1 is reserved if address_space = 1 */
230
231/* Header type 0 (normal devices) */
232#define PCI_CARDBUS_CIS 0x28
233#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
234#define PCI_SUBSYSTEM_ID 0x2e
235#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
236#define PCI_ROM_ADDRESS_ENABLE 0x01
Kumar Gala30e76d52008-10-21 08:36:08 -0500237#define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
wdenkc6097192002-11-03 00:24:07 +0000238
239#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
240
241/* 0x35-0x3b are reserved */
242#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
243#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
244#define PCI_MIN_GNT 0x3e /* 8 bits */
245#define PCI_MAX_LAT 0x3f /* 8 bits */
246
247/* Header type 1 (PCI-to-PCI bridges) */
248#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
249#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
250#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
251#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
252#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
253#define PCI_IO_LIMIT 0x1d
254#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
255#define PCI_IO_RANGE_TYPE_16 0x00
256#define PCI_IO_RANGE_TYPE_32 0x01
257#define PCI_IO_RANGE_MASK ~0x0f
258#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
259#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
260#define PCI_MEMORY_LIMIT 0x22
261#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
262#define PCI_MEMORY_RANGE_MASK ~0x0f
263#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
264#define PCI_PREF_MEMORY_LIMIT 0x26
265#define PCI_PREF_RANGE_TYPE_MASK 0x0f
266#define PCI_PREF_RANGE_TYPE_32 0x00
267#define PCI_PREF_RANGE_TYPE_64 0x01
268#define PCI_PREF_RANGE_MASK ~0x0f
269#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
270#define PCI_PREF_LIMIT_UPPER32 0x2c
271#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
272#define PCI_IO_LIMIT_UPPER16 0x32
273/* 0x34 same as for htype 0 */
274/* 0x35-0x3b is reserved */
275#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
276/* 0x3c-0x3d are same as for htype 0 */
277#define PCI_BRIDGE_CONTROL 0x3e
278#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
279#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
280#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
281#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
282#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
283#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
284#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
285
Stefan Roesec157d8e2005-08-01 16:41:48 +0200286/* From 440ep */
287#define PCI_ERREN 0x48 /* Error Enable */
288#define PCI_ERRSTS 0x49 /* Error Status */
289#define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
290#define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
291#define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
292#define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
293#define PCI_CAPID 0x58 /* Capability Identifier */
294#define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
295#define PCI_PMC 0x5A /* Power Management Capabilities */
296#define PCI_PMCSR 0x5C /* Power Management Control Status */
297#define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
298#define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
299#define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
300
wdenkc6097192002-11-03 00:24:07 +0000301/* Header type 2 (CardBus bridges) */
302#define PCI_CB_CAPABILITY_LIST 0x14
303/* 0x15 reserved */
304#define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
305#define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
306#define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
307#define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
308#define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
309#define PCI_CB_MEMORY_BASE_0 0x1c
310#define PCI_CB_MEMORY_LIMIT_0 0x20
311#define PCI_CB_MEMORY_BASE_1 0x24
312#define PCI_CB_MEMORY_LIMIT_1 0x28
313#define PCI_CB_IO_BASE_0 0x2c
314#define PCI_CB_IO_BASE_0_HI 0x2e
315#define PCI_CB_IO_LIMIT_0 0x30
316#define PCI_CB_IO_LIMIT_0_HI 0x32
317#define PCI_CB_IO_BASE_1 0x34
318#define PCI_CB_IO_BASE_1_HI 0x36
319#define PCI_CB_IO_LIMIT_1 0x38
320#define PCI_CB_IO_LIMIT_1_HI 0x3a
321#define PCI_CB_IO_RANGE_MASK ~0x03
322/* 0x3c-0x3d are same as for htype 0 */
323#define PCI_CB_BRIDGE_CONTROL 0x3e
324#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
325#define PCI_CB_BRIDGE_CTL_SERR 0x02
326#define PCI_CB_BRIDGE_CTL_ISA 0x04
327#define PCI_CB_BRIDGE_CTL_VGA 0x08
328#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
329#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
330#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
331#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
332#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
333#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
334#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
335#define PCI_CB_SUBSYSTEM_ID 0x42
336#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
337/* 0x48-0x7f reserved */
338
339/* Capability lists */
340
341#define PCI_CAP_LIST_ID 0 /* Capability ID */
342#define PCI_CAP_ID_PM 0x01 /* Power Management */
343#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
344#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
345#define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
346#define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
347#define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
Kumar Gala8295b942009-08-05 07:49:27 -0500348#define PCI_CAP_ID_EXP 0x10 /* PCI Express */
wdenkc6097192002-11-03 00:24:07 +0000349#define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
350#define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
351#define PCI_CAP_SIZEOF 4
352
353/* Power Management Registers */
354
355#define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
356#define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
357#define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
358#define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
359#define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
360#define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
361#define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
362#define PCI_PM_CTRL 4 /* PM control and status register */
363#define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
364#define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
365#define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
366#define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
367#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
368#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
369#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
370#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
371#define PCI_PM_DATA_REGISTER 7 /* (??) */
372#define PCI_PM_SIZEOF 8
373
374/* AGP registers */
375
376#define PCI_AGP_VERSION 2 /* BCD version number */
377#define PCI_AGP_RFU 3 /* Rest of capability flags */
378#define PCI_AGP_STATUS 4 /* Status register */
379#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
380#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
381#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
382#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
383#define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
384#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
385#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
386#define PCI_AGP_COMMAND 8 /* Control register */
387#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
388#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
389#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
390#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
391#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
392#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
393#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
394#define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
395#define PCI_AGP_SIZEOF 12
396
Matthew McClintockf0e6f572006-06-28 10:44:49 -0500397/* PCI-X registers */
398
399#define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
400#define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
401#define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
402#define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
403#define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
404
405
wdenkc6097192002-11-03 00:24:07 +0000406/* Slot Identification */
407
408#define PCI_SID_ESR 2 /* Expansion Slot Register */
409#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
410#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
411#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
412
413/* Message Signalled Interrupts registers */
414
415#define PCI_MSI_FLAGS 2 /* Various flags */
416#define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
417#define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
418#define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
419#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
420#define PCI_MSI_RFU 3 /* Rest of capability flags */
421#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
422#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
423#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
424#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
425
426#define PCI_MAX_PCI_DEVICES 32
427#define PCI_MAX_PCI_FUNCTIONS 8
428
Ed Swarthout63cec582007-08-02 14:09:49 -0500429#define PCI_DCR 0x54 /* PCIe Device Control Register */
430#define PCI_DSR 0x56 /* PCIe Device Status Register */
431#define PCI_LSR 0x5e /* PCIe Link Status Register */
Prabhakar Kushwahab03a4662011-02-01 15:55:58 +0000432#define PCI_LCR 0x5c /* PCIe Link Control Register */
Ed Swarthout63cec582007-08-02 14:09:49 -0500433#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
434#define PCI_LTSSM_L0 0x16 /* L0 state */
435
wdenkc6097192002-11-03 00:24:07 +0000436/* Include the ID list */
437
438#include <pci_ids.h>
439
Kumar Gala30e76d52008-10-21 08:36:08 -0500440#ifdef CONFIG_SYS_PCI_64BIT
441typedef u64 pci_addr_t;
442typedef u64 pci_size_t;
443#else
444typedef u32 pci_addr_t;
445typedef u32 pci_size_t;
446#endif
wdenkc6097192002-11-03 00:24:07 +0000447
Kumar Gala30e76d52008-10-21 08:36:08 -0500448struct pci_region {
449 pci_addr_t bus_start; /* Start on the bus */
450 phys_addr_t phys_start; /* Start in physical address space */
451 pci_size_t size; /* Size */
452 unsigned long flags; /* Resource flags */
453
454 pci_addr_t bus_lower;
wdenkc6097192002-11-03 00:24:07 +0000455};
456
457#define PCI_REGION_MEM 0x00000000 /* PCI memory space */
458#define PCI_REGION_IO 0x00000001 /* PCI IO space */
459#define PCI_REGION_TYPE 0x00000001
Kumar Galaa1790122006-01-11 13:24:15 -0600460#define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
wdenkc6097192002-11-03 00:24:07 +0000461
Kumar Galaff4e66e2009-02-06 09:49:31 -0600462#define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
wdenkc6097192002-11-03 00:24:07 +0000463#define PCI_REGION_RO 0x00000200 /* Read-only memory */
464
Simon Glassbc3442a2013-06-11 11:14:33 -0700465static inline void pci_set_region(struct pci_region *reg,
Kumar Gala30e76d52008-10-21 08:36:08 -0500466 pci_addr_t bus_start,
Becky Bruce36f32672008-05-07 13:24:57 -0500467 phys_addr_t phys_start,
Kumar Gala30e76d52008-10-21 08:36:08 -0500468 pci_size_t size,
wdenkc6097192002-11-03 00:24:07 +0000469 unsigned long flags) {
470 reg->bus_start = bus_start;
471 reg->phys_start = phys_start;
472 reg->size = size;
473 reg->flags = flags;
474}
475
476typedef int pci_dev_t;
477
478#define PCI_BUS(d) (((d) >> 16) & 0xff)
479#define PCI_DEV(d) (((d) >> 11) & 0x1f)
480#define PCI_FUNC(d) (((d) >> 8) & 0x7)
481#define PCI_BDF(b,d,f) ((b) << 16 | (d) << 11 | (f) << 8)
482
483#define PCI_ANY_ID (~0)
484
485struct pci_device_id {
486 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
487};
488
489struct pci_controller;
490
491struct pci_config_table {
492 unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
493 unsigned int class; /* Class ID, or PCI_ANY_ID */
494 unsigned int bus; /* Bus number, or PCI_ANY_ID */
495 unsigned int dev; /* Device number, or PCI_ANY_ID */
496 unsigned int func; /* Function number, or PCI_ANY_ID */
497
498 void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
499 struct pci_config_table *);
500 unsigned long priv[3];
501};
502
Wolfgang Denk993a2272006-03-12 16:54:11 +0100503extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
504 struct pci_config_table *);
wdenkc6097192002-11-03 00:24:07 +0000505extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
506 struct pci_config_table *);
507
508#define MAX_PCI_REGIONS 7
509
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300510#define INDIRECT_TYPE_NO_PCIE_LINK 1
511
wdenkc6097192002-11-03 00:24:07 +0000512/*
513 * Structure of a PCI controller (host bridge)
514 */
515struct pci_controller {
516 struct pci_controller *next;
517
518 int first_busno;
519 int last_busno;
520
521 volatile unsigned int *cfg_addr;
522 volatile unsigned char *cfg_data;
523
Anton Vorontsovfd6646c2009-01-08 04:26:12 +0300524 int indirect_type;
525
wdenkc6097192002-11-03 00:24:07 +0000526 struct pci_region regions[MAX_PCI_REGIONS];
527 int region_count;
528
529 struct pci_config_table *config_table;
530
531 void (*fixup_irq)(struct pci_controller *, pci_dev_t);
532
533 /* Low-level architecture-dependent routines */
534 int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
535 int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
536 int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
537 int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
538 int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
539 int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
540
541 /* Used by auto config */
Kumar Galaa1790122006-01-11 13:24:15 -0600542 struct pci_region *pci_mem, *pci_io, *pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000543
544 /* Used by ppc405 autoconfig*/
545 struct pci_region *pci_fb;
wdenkc7de8292002-11-19 11:04:11 +0000546 int current_busno;
Leo Liu10fa8d72011-01-19 19:50:47 +0800547
548 void *priv_data;
wdenkc6097192002-11-03 00:24:07 +0000549};
550
Simon Glassbc3442a2013-06-11 11:14:33 -0700551static inline void pci_set_ops(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000552 int (*read_byte)(struct pci_controller*,
553 pci_dev_t, int where, u8 *),
554 int (*read_word)(struct pci_controller*,
555 pci_dev_t, int where, u16 *),
556 int (*read_dword)(struct pci_controller*,
557 pci_dev_t, int where, u32 *),
558 int (*write_byte)(struct pci_controller*,
559 pci_dev_t, int where, u8),
560 int (*write_word)(struct pci_controller*,
561 pci_dev_t, int where, u16),
562 int (*write_dword)(struct pci_controller*,
563 pci_dev_t, int where, u32)) {
564 hose->read_byte = read_byte;
565 hose->read_word = read_word;
566 hose->read_dword = read_dword;
567 hose->write_byte = write_byte;
568 hose->write_word = write_word;
569 hose->write_dword = write_dword;
570}
571
Gabor Juhos842033e2013-05-30 07:06:12 +0000572#ifdef CONFIG_PCI_INDIRECT_BRIDGE
wdenkc6097192002-11-03 00:24:07 +0000573extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
Gabor Juhos842033e2013-05-30 07:06:12 +0000574#endif
wdenkc6097192002-11-03 00:24:07 +0000575
Becky Bruce36f32672008-05-07 13:24:57 -0500576extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
Kumar Gala30e76d52008-10-21 08:36:08 -0500577 pci_addr_t addr, unsigned long flags);
578extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
579 phys_addr_t addr, unsigned long flags);
wdenkc6097192002-11-03 00:24:07 +0000580
581#define pci_phys_to_bus(dev, addr, flags) \
582 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
583#define pci_bus_to_phys(dev, addr, flags) \
584 pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
585
Becky Bruce6e61fae2009-02-03 18:10:50 -0600586#define pci_virt_to_bus(dev, addr, flags) \
587 pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
588 (virt_to_phys(addr)), (flags))
589#define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
590 map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
591 (addr), (flags)), \
592 (len), (map_flags))
593
594#define pci_phys_to_mem(dev, addr) \
595 pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
596#define pci_mem_to_phys(dev, addr) \
597 pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
598#define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
599#define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
600
601#define pci_virt_to_mem(dev, addr) \
602 pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
603#define pci_mem_to_virt(dev, addr, len, map_flags) \
604 pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
605#define pci_virt_to_io(dev, addr) \
606 pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
607#define pci_io_to_virt(dev, addr, len, map_flags) \
608 pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
wdenkc6097192002-11-03 00:24:07 +0000609
610extern int pci_hose_read_config_byte(struct pci_controller *hose,
611 pci_dev_t dev, int where, u8 *val);
612extern int pci_hose_read_config_word(struct pci_controller *hose,
613 pci_dev_t dev, int where, u16 *val);
614extern int pci_hose_read_config_dword(struct pci_controller *hose,
615 pci_dev_t dev, int where, u32 *val);
616extern int pci_hose_write_config_byte(struct pci_controller *hose,
617 pci_dev_t dev, int where, u8 val);
618extern int pci_hose_write_config_word(struct pci_controller *hose,
619 pci_dev_t dev, int where, u16 val);
620extern int pci_hose_write_config_dword(struct pci_controller *hose,
621 pci_dev_t dev, int where, u32 val);
622
623extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
624extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
625extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
626extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
627extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
628extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
629
630extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
631 pci_dev_t dev, int where, u8 *val);
632extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
633 pci_dev_t dev, int where, u16 *val);
634extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
635 pci_dev_t dev, int where, u8 val);
636extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
637 pci_dev_t dev, int where, u16 val);
638
Becky Bruce6e61fae2009-02-03 18:10:50 -0600639extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
wdenkc6097192002-11-03 00:24:07 +0000640extern void pci_register_hose(struct pci_controller* hose);
641extern struct pci_controller* pci_bus_to_hose(int bus);
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600642extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
wdenkc6097192002-11-03 00:24:07 +0000643
644extern int pci_hose_scan(struct pci_controller *hose);
645extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
646
647extern void pciauto_region_init(struct pci_region* res);
Kumar Gala30e76d52008-10-21 08:36:08 -0500648extern void pciauto_region_align(struct pci_region *res, pci_size_t size);
649extern int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar);
wdenkc6097192002-11-03 00:24:07 +0000650extern void pciauto_setup_device(struct pci_controller *hose,
651 pci_dev_t dev, int bars_num,
652 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -0600653 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +0000654 struct pci_region *io);
Linus Walleija3a70722012-03-25 12:13:15 +0000655extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
656 pci_dev_t dev, int sub_bus);
657extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
658 pci_dev_t dev, int sub_bus);
Linus Walleija1e47b62012-03-03 10:05:08 +0000659extern void pciauto_config_init(struct pci_controller *hose);
Linus Walleija3a70722012-03-25 12:13:15 +0000660extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000661
662extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
663extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
wdenk7a8e9bed2003-05-31 18:35:21 +0000664extern pci_dev_t pci_find_class(int wanted_class, int wanted_sub_code,
665 int wanted_prog_if, int index);
wdenkc6097192002-11-03 00:24:07 +0000666
667extern int pci_hose_config_device(struct pci_controller *hose,
668 pci_dev_t dev,
669 unsigned long io,
Kumar Gala30e76d52008-10-21 08:36:08 -0500670 pci_addr_t mem,
wdenkc6097192002-11-03 00:24:07 +0000671 unsigned long command);
672
Peter Tyser983eb9d2010-10-29 17:59:27 -0500673const char * pci_class_str(u8 class);
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300674int pci_last_busno(void);
675
wdenkc6097192002-11-03 00:24:07 +0000676#ifdef CONFIG_MPC824X
677extern void pci_mpc824x_init (struct pci_controller *hose);
678#endif
679
Jon Loeliger13a7fcd2006-10-19 11:33:52 -0500680#ifdef CONFIG_MPC85xx
681extern void pci_mpc85xx_init (struct pci_controller *hose);
682#endif
wdenkc6097192002-11-03 00:24:07 +0000683#endif /* _PCI_H */