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wdenk3bac3512003-03-12 10:41:04 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk3bac3512003-03-12 10:41:04 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk3bac3512003-03-12 10:41:04 +00006 */
7
8/*
9 *
10 * Configuration settings for the CPC45 board.
11 *
12 */
13
14/* ------------------------------------------------------------------------- */
15
16/*
17 * board/config.h - configuration options, board specific
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 * (easy to change)
26 */
27
wdenk3bac3512003-03-12 10:41:04 +000028#define CONFIG_MPC8245 1
29#define CONFIG_CPC45 1
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenk3bac3512003-03-12 10:41:04 +000032
33#define CONFIG_CONS_INDEX 1
34#define CONFIG_BAUDRATE 9600
wdenk3bac3512003-03-12 10:41:04 +000035
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010036#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk3bac3512003-03-12 10:41:04 +000037
38#define CONFIG_BOOTDELAY 5
39
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050040/*
41 * BOOTP options
42 */
43#define CONFIG_BOOTP_SUBNETMASK
44#define CONFIG_BOOTP_GATEWAY
45#define CONFIG_BOOTP_HOSTNAME
46#define CONFIG_BOOTP_BOOTPATH
47
48#define CONFIG_BOOTP_BOOTFILESIZE
wdenk3bac3512003-03-12 10:41:04 +000049
wdenk3bac3512003-03-12 10:41:04 +000050
Jon Loeliger49cf7e82007-07-05 19:52:35 -050051/*
52 * Command line configuration.
wdenk3bac3512003-03-12 10:41:04 +000053 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050054#include <config_cmd_default.h>
55
56#define CONFIG_CMD_BEDBUG
57#define CONFIG_CMD_DATE
58#define CONFIG_CMD_DHCP
59#define CONFIG_CMD_EEPROM
60#define CONFIG_CMD_EXT2
61#define CONFIG_CMD_FAT
62#define CONFIG_CMD_FLASH
63#define CONFIG_CMD_I2C
64#define CONFIG_CMD_IDE
65#define CONFIG_CMD_NFS
66#define CONFIG_CMD_PCI
67#define CONFIG_CMD_PING
68#define CONFIG_CMD_SDRAM
69#define CONFIG_CMD_SNTP
wdenk3bac3512003-03-12 10:41:04 +000070
71
72/*
73 * Miscellaneous configurable options
74 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3bac3512003-03-12 10:41:04 +000077
78#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenk3bac3512003-03-12 10:41:04 +000080#endif
wdenk3bac3512003-03-12 10:41:04 +000081
82/* Print Buffer Size
83 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenk3bac3512003-03-12 10:41:04 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
87#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
88#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenk3bac3512003-03-12 10:41:04 +000089
90/*-----------------------------------------------------------------------
91 * Start addresses for the final memory configuration
92 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk3bac3512003-03-12 10:41:04 +000094 */
95
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk3bac3512003-03-12 10:41:04 +000097
98#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenk3bac3512003-03-12 10:41:04 +0000100#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_BASE 0xFF800000
wdenk3bac3512003-03-12 10:41:04 +0000102#endif
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk3bac3512003-03-12 10:41:04 +0000105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
wdenk3bac3512003-03-12 10:41:04 +0000107
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200108#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenk3bac3512003-03-12 10:41:04 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
111#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bac3512003-03-12 10:41:04 +0000112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
114#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk3bac3512003-03-12 10:41:04 +0000115
wdenk49822e22004-06-19 21:19:10 +0000116/* Maximum amount of RAM.
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenk3bac3512003-03-12 10:41:04 +0000119
120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
122#undef CONFIG_SYS_RAMBOOT
wdenk3bac3512003-03-12 10:41:04 +0000123#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_RAMBOOT
wdenk3bac3512003-03-12 10:41:04 +0000125#endif
126
127
128/*-----------------------------------------------------------------------
129 * Definitions for initial stack pointer and data area
130 */
131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200133#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200134#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk3bac3512003-03-12 10:41:04 +0000135
136/*
137 * NS16550 Configuration
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_NS16550
140#define CONFIG_SYS_NS16550_SERIAL
wdenk3bac3512003-03-12 10:41:04 +0000141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk3bac3512003-03-12 10:41:04 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk3bac3512003-03-12 10:41:04 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
147#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
148#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511)
wdenk49822e22004-06-19 21:19:10 +0000149
150/*
151 * I2C configuration
152 */
153#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
156#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk49822e22004-06-19 21:19:10 +0000157
158/*
159 * RTC configuration
160 */
161#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk49822e22004-06-19 21:19:10 +0000163
164/*
165 * EEPROM configuration
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
168#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
169#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
170#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
171#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenk3bac3512003-03-12 10:41:04 +0000172
173/*
174 * Low Level Configuration Settings
175 * (address mappings, register initial values, etc.)
176 * You should know what you are doing if you make changes here.
177 * For the detail description refer to the MPC8240 user's manual.
178 */
179
wdenk49822e22004-06-19 21:19:10 +0000180#define CONFIG_SYS_CLK_FREQ 33000000
wdenk49822e22004-06-19 21:19:10 +0000181
182
183/* Bit-field values for MCCR1.
184 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_ROMNAL 0
186#define CONFIG_SYS_ROMFAL 8
wdenk49822e22004-06-19 21:19:10 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
189#define CONFIG_SYS_BANK1_ROW 0
190#define CONFIG_SYS_BANK2_ROW 0
191#define CONFIG_SYS_BANK3_ROW 0
192#define CONFIG_SYS_BANK4_ROW 0
193#define CONFIG_SYS_BANK5_ROW 0
194#define CONFIG_SYS_BANK6_ROW 0
195#define CONFIG_SYS_BANK7_ROW 0
wdenk49822e22004-06-19 21:19:10 +0000196
197/* Bit-field values for MCCR2.
wdenk3bac3512003-03-12 10:41:04 +0000198 */
stroese53cf9432003-06-05 15:39:44 +0000199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_REFINT 0x2ec
wdenk3bac3512003-03-12 10:41:04 +0000201
wdenk49822e22004-06-19 21:19:10 +0000202/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
203 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_BSTOPRE 160
wdenk3bac3512003-03-12 10:41:04 +0000205
wdenk49822e22004-06-19 21:19:10 +0000206/* Bit-field values for MCCR3.
207 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
209#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */
wdenk3bac3512003-03-12 10:41:04 +0000210
wdenk49822e22004-06-19 21:19:10 +0000211/* Bit-field values for MCCR4.
212 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
214#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
215#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
216#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
217#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
218#define CONFIG_SYS_ACTORW 2
219#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
220#define CONFIG_SYS_EXTROM 0
221#define CONFIG_SYS_REGDIMM 0
wdenk3bac3512003-03-12 10:41:04 +0000222
223/* Memory bank settings.
224 * Only bits 20-29 are actually used from these vales to set the
225 * start/end addresses. The upper two bits will always be 0, and the lower
226 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
227 * address. Refer to the MPC8240 book.
228 */
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BANK0_START 0x00000000
231#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
232#define CONFIG_SYS_BANK0_ENABLE 1
233#define CONFIG_SYS_BANK1_START 0x3ff00000
234#define CONFIG_SYS_BANK1_END 0x3fffffff
235#define CONFIG_SYS_BANK1_ENABLE 0
236#define CONFIG_SYS_BANK2_START 0x3ff00000
237#define CONFIG_SYS_BANK2_END 0x3fffffff
238#define CONFIG_SYS_BANK2_ENABLE 0
239#define CONFIG_SYS_BANK3_START 0x3ff00000
240#define CONFIG_SYS_BANK3_END 0x3fffffff
241#define CONFIG_SYS_BANK3_ENABLE 0
242#define CONFIG_SYS_BANK4_START 0x3ff00000
243#define CONFIG_SYS_BANK4_END 0x3fffffff
244#define CONFIG_SYS_BANK4_ENABLE 0
245#define CONFIG_SYS_BANK5_START 0x3ff00000
246#define CONFIG_SYS_BANK5_END 0x3fffffff
247#define CONFIG_SYS_BANK5_ENABLE 0
248#define CONFIG_SYS_BANK6_START 0x3ff00000
249#define CONFIG_SYS_BANK6_END 0x3fffffff
250#define CONFIG_SYS_BANK6_ENABLE 0
251#define CONFIG_SYS_BANK7_START 0x3ff00000
252#define CONFIG_SYS_BANK7_END 0x3fffffff
253#define CONFIG_SYS_BANK7_ENABLE 0
wdenk3bac3512003-03-12 10:41:04 +0000254
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_ODCR 0xff
256#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenk49822e22004-06-19 21:19:10 +0000257 /* currently accessed page in memory */
258 /* see 8240 book for details */
wdenk3bac3512003-03-12 10:41:04 +0000259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
261#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
264#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
267#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
270#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
273#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
274#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
275#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
276#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
277#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
278#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
279#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk3bac3512003-03-12 10:41:04 +0000280
281/*
282 * For booting Linux, the board info and command line data
283 * have to be in the first 8 MB of memory, since this is
284 * the maximum mapped by the Linux kernel during initialization.
285 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bac3512003-03-12 10:41:04 +0000287
288/*-----------------------------------------------------------------------
289 * FLASH organization
290 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
292#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
wdenk3bac3512003-03-12 10:41:04 +0000293#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
295#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk3bac3512003-03-12 10:41:04 +0000296
297 /* Warining: environment is not EMBEDDED in the ppcboot code.
298 * It's stored in flash separately.
299 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200300#define CONFIG_ENV_IS_IN_FLASH 1
wdenk3bac3512003-03-12 10:41:04 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200303#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
304#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
305#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
wdenk3bac3512003-03-12 10:41:04 +0000306
307/*-----------------------------------------------------------------------
308 * Cache Configuration
309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500311#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk3bac3512003-03-12 10:41:04 +0000313#endif
314
wdenk49822e22004-06-19 21:19:10 +0000315/*----------------------------------------------------------------------*/
316/* CPC45 Memory Map */
317/*----------------------------------------------------------------------*/
318#define SRAM_BASE 0x80000000 /* SRAM base address */
Wolfgang Denk36116652010-08-11 09:38:31 +0200319#define SRAM_END 0x801FFFFF
wdenk49822e22004-06-19 21:19:10 +0000320#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
321#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
322#define BCSR_BASE 0x80600000 /* board control / status registers */
323#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
wdenke2ffd592004-12-31 09:32:47 +0000324#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
wdenk49822e22004-06-19 21:19:10 +0000325#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
wdenk3bac3512003-03-12 10:41:04 +0000326
Wolfgang Denk36116652010-08-11 09:38:31 +0200327#define CONFIG_SYS_SRAM_BASE SRAM_BASE
328#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
wdenk3bac3512003-03-12 10:41:04 +0000329
330/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000331/* CPC45 Control/Status Registers */
wdenk3bac3512003-03-12 10:41:04 +0000332/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000333#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
334#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
335#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
336#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
337#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
338#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
339#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
340#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
341#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
342#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
wdenk3bac3512003-03-12 10:41:04 +0000343
344/* IRQ_ENA_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000345#define I_ENA_1_IERA 0x80 /* INTA enable */
346#define I_ENA_1_IERB 0x40 /* INTB enable */
347#define I_ENA_1_IERC 0x20 /* INTC enable */
348#define I_ENA_1_IERD 0x10 /* INTD enable */
wdenk3bac3512003-03-12 10:41:04 +0000349
350/* IRQ_STAT_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000351#define I_STAT_1_INTA 0x80 /* INTA status */
352#define I_STAT_1_INTB 0x40 /* INTB status */
353#define I_STAT_1_INTC 0x20 /* INTC status */
354#define I_STAT_1_INTD 0x10 /* INTD status */
wdenk3bac3512003-03-12 10:41:04 +0000355
356/* IRQ_ENA_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000357#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
358#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
359#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
360#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
361#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
362#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
363#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
364#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
wdenk3bac3512003-03-12 10:41:04 +0000365
366/* IRQ_STAT_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000367#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
368#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
369#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
370#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
371#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
372#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
373#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
374#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
wdenk3bac3512003-03-12 10:41:04 +0000375
376/* BOARD_CTRL bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000377#define USER_LEDS 2 /* 2 user LEDs */
wdenk3bac3512003-03-12 10:41:04 +0000378
379#if (USER_LEDS == 4)
wdenk49822e22004-06-19 21:19:10 +0000380#define B_CTRL_WRSE 0x80
381#define B_CTRL_KRSE 0x40
382#define B_CTRL_FWRE 0x20 /* Flash write enable */
383#define B_CTRL_FWPT 0x10 /* Flash write protect */
384#define B_CTRL_LED3 0x08 /* LED 3 control */
385#define B_CTRL_LED2 0x04 /* LED 2 control */
386#define B_CTRL_LED1 0x02 /* LED 1 control */
387#define B_CTRL_LED0 0x01 /* LED 0 control */
wdenk3bac3512003-03-12 10:41:04 +0000388#else
wdenk49822e22004-06-19 21:19:10 +0000389#define B_CTRL_WRSE 0x80
390#define B_CTRL_KRSE 0x40
391#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
392#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
393#define B_CTRL_LED1 0x08 /* LED 1 control */
394#define B_CTRL_LED0 0x04 /* LED 0 control */
395#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
396#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
wdenk3bac3512003-03-12 10:41:04 +0000397#endif
398
399/* BOARD_STAT bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000400#define B_STAT_WDGE 0x80
401#define B_STAT_WDGS 0x40
402#define B_STAT_WRST 0x20
403#define B_STAT_KRST 0x10
404#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
405#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
406#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
407#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
wdenk3bac3512003-03-12 10:41:04 +0000408
409/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000410/* Display addresses */
wdenk3bac3512003-03-12 10:41:04 +0000411/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000412#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
413#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
414#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
wdenk3bac3512003-03-12 10:41:04 +0000415
wdenk49822e22004-06-19 21:19:10 +0000416#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
417#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
wdenk3bac3512003-03-12 10:41:04 +0000418
wdenk49822e22004-06-19 21:19:10 +0000419#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
420#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
421#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
422#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
423#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
424#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
425#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
426#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
wdenk3bac3512003-03-12 10:41:04 +0000427
428
429/*-----------------------------------------------------------------------
430 * PCI stuff
431 *-----------------------------------------------------------------------
432 */
433#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000434#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Andre Schwarz76221a62010-10-05 11:59:31 +0200435#define CONFIG_SYS_EARLY_PCI_INIT
wdenk49822e22004-06-19 21:19:10 +0000436#undef CONFIG_PCI_PNP
437#undef CONFIG_PCI_SCAN_SHOW
wdenk3bac3512003-03-12 10:41:04 +0000438
wdenk3bac3512003-03-12 10:41:04 +0000439
440#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000442
wdenk49822e22004-06-19 21:19:10 +0000443#define PCI_ENET0_IOADDR 0x82000000
wdenk3bac3512003-03-12 10:41:04 +0000444#define PCI_ENET0_MEMADDR 0x82000000
wdenk49822e22004-06-19 21:19:10 +0000445#define PCI_PLX9030_IOADDR 0x82100000
446#define PCI_PLX9030_MEMADDR 0x82100000
wdenke2ffd592004-12-31 09:32:47 +0000447
448/*-----------------------------------------------------------------------
449 * PCMCIA stuff
450 *-----------------------------------------------------------------------
451 */
452
453#define CONFIG_I82365
454
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
456#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
wdenke2ffd592004-12-31 09:32:47 +0000457
458#define CONFIG_PCMCIA_SLOT_A
459
460/*-----------------------------------------------------------------------
461 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
462 *-----------------------------------------------------------------------
463 */
464
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000465#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenke2ffd592004-12-31 09:32:47 +0000466#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
467
468#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
469#undef CONFIG_IDE_RESET /* reset for IDE not supported */
470#define CONFIG_IDE_LED /* LED for IDE is supported */
471
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
473#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenke2ffd592004-12-31 09:32:47 +0000474
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenke2ffd592004-12-31 09:32:47 +0000476
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200477#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenke2ffd592004-12-31 09:32:47 +0000478
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE
wdenke2ffd592004-12-31 09:32:47 +0000480
481/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke2ffd592004-12-31 09:32:47 +0000483
484/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
wdenke2ffd592004-12-31 09:32:47 +0000486
487#define CONFIG_DOS_PARTITION
488
wdenk3bac3512003-03-12 10:41:04 +0000489#endif /* __CONFIG_H */