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wdenk3bac3512003-03-12 10:41:04 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk3bac3512003-03-12 10:41:04 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk3bac3512003-03-12 10:41:04 +00006 */
7
8/*
9 *
10 * Configuration settings for the CPC45 board.
11 *
12 */
13
14/* ------------------------------------------------------------------------- */
15
16/*
17 * board/config.h - configuration options, board specific
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23/*
24 * High Level Configuration Options
25 * (easy to change)
26 */
27
28#define CONFIG_MPC824X 1
29#define CONFIG_MPC8245 1
30#define CONFIG_CPC45 1
31
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenk3bac3512003-03-12 10:41:04 +000033
34#define CONFIG_CONS_INDEX 1
35#define CONFIG_BAUDRATE 9600
wdenk3bac3512003-03-12 10:41:04 +000036
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010037#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk3bac3512003-03-12 10:41:04 +000038
39#define CONFIG_BOOTDELAY 5
40
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050041/*
42 * BOOTP options
43 */
44#define CONFIG_BOOTP_SUBNETMASK
45#define CONFIG_BOOTP_GATEWAY
46#define CONFIG_BOOTP_HOSTNAME
47#define CONFIG_BOOTP_BOOTPATH
48
49#define CONFIG_BOOTP_BOOTFILESIZE
wdenk3bac3512003-03-12 10:41:04 +000050
wdenk3bac3512003-03-12 10:41:04 +000051
Jon Loeliger49cf7e82007-07-05 19:52:35 -050052/*
53 * Command line configuration.
wdenk3bac3512003-03-12 10:41:04 +000054 */
Jon Loeliger49cf7e82007-07-05 19:52:35 -050055#include <config_cmd_default.h>
56
57#define CONFIG_CMD_BEDBUG
58#define CONFIG_CMD_DATE
59#define CONFIG_CMD_DHCP
60#define CONFIG_CMD_EEPROM
61#define CONFIG_CMD_EXT2
62#define CONFIG_CMD_FAT
63#define CONFIG_CMD_FLASH
64#define CONFIG_CMD_I2C
65#define CONFIG_CMD_IDE
66#define CONFIG_CMD_NFS
67#define CONFIG_CMD_PCI
68#define CONFIG_CMD_PING
69#define CONFIG_CMD_SDRAM
70#define CONFIG_CMD_SNTP
wdenk3bac3512003-03-12 10:41:04 +000071
72
73/*
74 * Miscellaneous configurable options
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_LONGHELP /* undef to save memory */
77#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
78#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk3bac3512003-03-12 10:41:04 +000079
80#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
wdenk3bac3512003-03-12 10:41:04 +000082#endif
wdenk3bac3512003-03-12 10:41:04 +000083
84/* Print Buffer Size
85 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenk3bac3512003-03-12 10:41:04 +000087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
89#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
90#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenk3bac3512003-03-12 10:41:04 +000091
92/*-----------------------------------------------------------------------
93 * Start addresses for the final memory configuration
94 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk3bac3512003-03-12 10:41:04 +000096 */
97
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk3bac3512003-03-12 10:41:04 +000099
100#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_FLASH_BASE 0xFF000000
wdenk3bac3512003-03-12 10:41:04 +0000102#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_FLASH_BASE 0xFF800000
wdenk3bac3512003-03-12 10:41:04 +0000104#endif
105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk3bac3512003-03-12 10:41:04 +0000107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_EUMB_ADDR 0xFCE00000
wdenk3bac3512003-03-12 10:41:04 +0000109
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200110#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenk3bac3512003-03-12 10:41:04 +0000111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
113#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk3bac3512003-03-12 10:41:04 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
116#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk3bac3512003-03-12 10:41:04 +0000117
wdenk49822e22004-06-19 21:19:10 +0000118/* Maximum amount of RAM.
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenk3bac3512003-03-12 10:41:04 +0000121
122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
124#undef CONFIG_SYS_RAMBOOT
wdenk3bac3512003-03-12 10:41:04 +0000125#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_RAMBOOT
wdenk3bac3512003-03-12 10:41:04 +0000127#endif
128
129
130/*-----------------------------------------------------------------------
131 * Definitions for initial stack pointer and data area
132 */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200135#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200136#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk3bac3512003-03-12 10:41:04 +0000137
138/*
139 * NS16550 Configuration
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_NS16550
142#define CONFIG_SYS_NS16550_SERIAL
wdenk3bac3512003-03-12 10:41:04 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk3bac3512003-03-12 10:41:04 +0000145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk3bac3512003-03-12 10:41:04 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
149#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
150#define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511)
wdenk49822e22004-06-19 21:19:10 +0000151
152/*
153 * I2C configuration
154 */
155#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
158#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk49822e22004-06-19 21:19:10 +0000159
160/*
161 * RTC configuration
162 */
163#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk49822e22004-06-19 21:19:10 +0000165
166/*
167 * EEPROM configuration
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
170#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
171#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
172#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
173#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
wdenk3bac3512003-03-12 10:41:04 +0000174
175/*
176 * Low Level Configuration Settings
177 * (address mappings, register initial values, etc.)
178 * You should know what you are doing if you make changes here.
179 * For the detail description refer to the MPC8240 user's manual.
180 */
181
wdenk49822e22004-06-19 21:19:10 +0000182#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_HZ 1000
wdenk49822e22004-06-19 21:19:10 +0000184
185
186/* Bit-field values for MCCR1.
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_ROMNAL 0
189#define CONFIG_SYS_ROMFAL 8
wdenk49822e22004-06-19 21:19:10 +0000190
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
192#define CONFIG_SYS_BANK1_ROW 0
193#define CONFIG_SYS_BANK2_ROW 0
194#define CONFIG_SYS_BANK3_ROW 0
195#define CONFIG_SYS_BANK4_ROW 0
196#define CONFIG_SYS_BANK5_ROW 0
197#define CONFIG_SYS_BANK6_ROW 0
198#define CONFIG_SYS_BANK7_ROW 0
wdenk49822e22004-06-19 21:19:10 +0000199
200/* Bit-field values for MCCR2.
wdenk3bac3512003-03-12 10:41:04 +0000201 */
stroese53cf9432003-06-05 15:39:44 +0000202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_REFINT 0x2ec
wdenk3bac3512003-03-12 10:41:04 +0000204
wdenk49822e22004-06-19 21:19:10 +0000205/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_BSTOPRE 160
wdenk3bac3512003-03-12 10:41:04 +0000208
wdenk49822e22004-06-19 21:19:10 +0000209/* Bit-field values for MCCR3.
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
212#define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */
wdenk3bac3512003-03-12 10:41:04 +0000213
wdenk49822e22004-06-19 21:19:10 +0000214/* Bit-field values for MCCR4.
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
217#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
218#define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
219#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
220#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
221#define CONFIG_SYS_ACTORW 2
222#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
223#define CONFIG_SYS_EXTROM 0
224#define CONFIG_SYS_REGDIMM 0
wdenk3bac3512003-03-12 10:41:04 +0000225
226/* Memory bank settings.
227 * Only bits 20-29 are actually used from these vales to set the
228 * start/end addresses. The upper two bits will always be 0, and the lower
229 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
230 * address. Refer to the MPC8240 book.
231 */
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_BANK0_START 0x00000000
234#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
235#define CONFIG_SYS_BANK0_ENABLE 1
236#define CONFIG_SYS_BANK1_START 0x3ff00000
237#define CONFIG_SYS_BANK1_END 0x3fffffff
238#define CONFIG_SYS_BANK1_ENABLE 0
239#define CONFIG_SYS_BANK2_START 0x3ff00000
240#define CONFIG_SYS_BANK2_END 0x3fffffff
241#define CONFIG_SYS_BANK2_ENABLE 0
242#define CONFIG_SYS_BANK3_START 0x3ff00000
243#define CONFIG_SYS_BANK3_END 0x3fffffff
244#define CONFIG_SYS_BANK3_ENABLE 0
245#define CONFIG_SYS_BANK4_START 0x3ff00000
246#define CONFIG_SYS_BANK4_END 0x3fffffff
247#define CONFIG_SYS_BANK4_ENABLE 0
248#define CONFIG_SYS_BANK5_START 0x3ff00000
249#define CONFIG_SYS_BANK5_END 0x3fffffff
250#define CONFIG_SYS_BANK5_ENABLE 0
251#define CONFIG_SYS_BANK6_START 0x3ff00000
252#define CONFIG_SYS_BANK6_END 0x3fffffff
253#define CONFIG_SYS_BANK6_ENABLE 0
254#define CONFIG_SYS_BANK7_START 0x3ff00000
255#define CONFIG_SYS_BANK7_END 0x3fffffff
256#define CONFIG_SYS_BANK7_ENABLE 0
wdenk3bac3512003-03-12 10:41:04 +0000257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_ODCR 0xff
259#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenk49822e22004-06-19 21:19:10 +0000260 /* currently accessed page in memory */
261 /* see 8240 book for details */
wdenk3bac3512003-03-12 10:41:04 +0000262
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
264#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
267#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
270#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
273#define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
wdenk3bac3512003-03-12 10:41:04 +0000274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
276#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
277#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
278#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
279#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
280#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
281#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
282#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk3bac3512003-03-12 10:41:04 +0000283
284/*
285 * For booting Linux, the board info and command line data
286 * have to be in the first 8 MB of memory, since this is
287 * the maximum mapped by the Linux kernel during initialization.
288 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk3bac3512003-03-12 10:41:04 +0000290
291/*-----------------------------------------------------------------------
292 * FLASH organization
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
295#define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
wdenk3bac3512003-03-12 10:41:04 +0000296#define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
298#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk3bac3512003-03-12 10:41:04 +0000299
300 /* Warining: environment is not EMBEDDED in the ppcboot code.
301 * It's stored in flash separately.
302 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200303#define CONFIG_ENV_IS_IN_FLASH 1
wdenk3bac3512003-03-12 10:41:04 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200306#define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
307#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
308#define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
wdenk3bac3512003-03-12 10:41:04 +0000309
310/*-----------------------------------------------------------------------
311 * Cache Configuration
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500314#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk3bac3512003-03-12 10:41:04 +0000316#endif
317
wdenk49822e22004-06-19 21:19:10 +0000318/*----------------------------------------------------------------------*/
319/* CPC45 Memory Map */
320/*----------------------------------------------------------------------*/
321#define SRAM_BASE 0x80000000 /* SRAM base address */
Wolfgang Denk36116652010-08-11 09:38:31 +0200322#define SRAM_END 0x801FFFFF
wdenk49822e22004-06-19 21:19:10 +0000323#define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
324#define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
325#define BCSR_BASE 0x80600000 /* board control / status registers */
326#define DISPLAY_BASE 0x80600040 /* DISPLAY base */
wdenke2ffd592004-12-31 09:32:47 +0000327#define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
wdenk49822e22004-06-19 21:19:10 +0000328#define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
wdenk3bac3512003-03-12 10:41:04 +0000329
Wolfgang Denk36116652010-08-11 09:38:31 +0200330#define CONFIG_SYS_SRAM_BASE SRAM_BASE
331#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
wdenk3bac3512003-03-12 10:41:04 +0000332
333/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000334/* CPC45 Control/Status Registers */
wdenk3bac3512003-03-12 10:41:04 +0000335/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000336#define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
337#define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
338#define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
339#define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
340#define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
341#define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
342#define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
343#define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
344#define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
345#define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
wdenk3bac3512003-03-12 10:41:04 +0000346
347/* IRQ_ENA_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000348#define I_ENA_1_IERA 0x80 /* INTA enable */
349#define I_ENA_1_IERB 0x40 /* INTB enable */
350#define I_ENA_1_IERC 0x20 /* INTC enable */
351#define I_ENA_1_IERD 0x10 /* INTD enable */
wdenk3bac3512003-03-12 10:41:04 +0000352
353/* IRQ_STAT_1 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000354#define I_STAT_1_INTA 0x80 /* INTA status */
355#define I_STAT_1_INTB 0x40 /* INTB status */
356#define I_STAT_1_INTC 0x20 /* INTC status */
357#define I_STAT_1_INTD 0x10 /* INTD status */
wdenk3bac3512003-03-12 10:41:04 +0000358
359/* IRQ_ENA_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000360#define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
361#define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
362#define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
363#define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
364#define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
365#define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
366#define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
367#define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
wdenk3bac3512003-03-12 10:41:04 +0000368
369/* IRQ_STAT_2 bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000370#define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
371#define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
372#define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
373#define I_STAT_2_RTC 0x10 /* RTC IRQ status */
374#define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
375#define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
376#define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
377#define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
wdenk3bac3512003-03-12 10:41:04 +0000378
379/* BOARD_CTRL bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000380#define USER_LEDS 2 /* 2 user LEDs */
wdenk3bac3512003-03-12 10:41:04 +0000381
382#if (USER_LEDS == 4)
wdenk49822e22004-06-19 21:19:10 +0000383#define B_CTRL_WRSE 0x80
384#define B_CTRL_KRSE 0x40
385#define B_CTRL_FWRE 0x20 /* Flash write enable */
386#define B_CTRL_FWPT 0x10 /* Flash write protect */
387#define B_CTRL_LED3 0x08 /* LED 3 control */
388#define B_CTRL_LED2 0x04 /* LED 2 control */
389#define B_CTRL_LED1 0x02 /* LED 1 control */
390#define B_CTRL_LED0 0x01 /* LED 0 control */
wdenk3bac3512003-03-12 10:41:04 +0000391#else
wdenk49822e22004-06-19 21:19:10 +0000392#define B_CTRL_WRSE 0x80
393#define B_CTRL_KRSE 0x40
394#define B_CTRL_FWRE_1 0x20 /* Flash write enable */
395#define B_CTRL_FWPT_1 0x10 /* Flash write protect */
396#define B_CTRL_LED1 0x08 /* LED 1 control */
397#define B_CTRL_LED0 0x04 /* LED 0 control */
398#define B_CTRL_FWRE_0 0x02 /* Flash write enable */
399#define B_CTRL_FWPT_0 0x01 /* Flash write protect */
wdenk3bac3512003-03-12 10:41:04 +0000400#endif
401
402/* BOARD_STAT bit definitions */
wdenk49822e22004-06-19 21:19:10 +0000403#define B_STAT_WDGE 0x80
404#define B_STAT_WDGS 0x40
405#define B_STAT_WRST 0x20
406#define B_STAT_KRST 0x10
407#define B_STAT_CSW3 0x08 /* sitch bit 3 status */
408#define B_STAT_CSW2 0x04 /* sitch bit 2 status */
409#define B_STAT_CSW1 0x02 /* sitch bit 1 status */
410#define B_STAT_CSW0 0x01 /* sitch bit 0 status */
wdenk3bac3512003-03-12 10:41:04 +0000411
412/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000413/* Display addresses */
wdenk3bac3512003-03-12 10:41:04 +0000414/*---------------------------------------------------------------------*/
wdenk49822e22004-06-19 21:19:10 +0000415#define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
416#define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
417#define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
wdenk3bac3512003-03-12 10:41:04 +0000418
wdenk49822e22004-06-19 21:19:10 +0000419#define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
420#define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
wdenk3bac3512003-03-12 10:41:04 +0000421
wdenk49822e22004-06-19 21:19:10 +0000422#define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
423#define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
424#define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
425#define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
426#define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
427#define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
428#define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
429#define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
wdenk3bac3512003-03-12 10:41:04 +0000430
431
432/*-----------------------------------------------------------------------
433 * PCI stuff
434 *-----------------------------------------------------------------------
435 */
436#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000437#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Andre Schwarz76221a62010-10-05 11:59:31 +0200438#define CONFIG_SYS_EARLY_PCI_INIT
wdenk49822e22004-06-19 21:19:10 +0000439#undef CONFIG_PCI_PNP
440#undef CONFIG_PCI_SCAN_SHOW
wdenk3bac3512003-03-12 10:41:04 +0000441
wdenk3bac3512003-03-12 10:41:04 +0000442
443#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenk3bac3512003-03-12 10:41:04 +0000445
wdenk49822e22004-06-19 21:19:10 +0000446#define PCI_ENET0_IOADDR 0x82000000
wdenk3bac3512003-03-12 10:41:04 +0000447#define PCI_ENET0_MEMADDR 0x82000000
wdenk49822e22004-06-19 21:19:10 +0000448#define PCI_PLX9030_IOADDR 0x82100000
449#define PCI_PLX9030_MEMADDR 0x82100000
wdenke2ffd592004-12-31 09:32:47 +0000450
451/*-----------------------------------------------------------------------
452 * PCMCIA stuff
453 *-----------------------------------------------------------------------
454 */
455
456#define CONFIG_I82365
457
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200458#define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
459#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
wdenke2ffd592004-12-31 09:32:47 +0000460
461#define CONFIG_PCMCIA_SLOT_A
462
463/*-----------------------------------------------------------------------
464 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
465 *-----------------------------------------------------------------------
466 */
467
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000468#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenke2ffd592004-12-31 09:32:47 +0000469#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
470
471#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
472#undef CONFIG_IDE_RESET /* reset for IDE not supported */
473#define CONFIG_IDE_LED /* LED for IDE is supported */
474
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
476#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenke2ffd592004-12-31 09:32:47 +0000477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenke2ffd592004-12-31 09:32:47 +0000479
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenke2ffd592004-12-31 09:32:47 +0000481
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482#define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE
wdenke2ffd592004-12-31 09:32:47 +0000483
484/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenke2ffd592004-12-31 09:32:47 +0000486
487/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200488#define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
wdenke2ffd592004-12-31 09:32:47 +0000489
490#define CONFIG_DOS_PARTITION
491
wdenk3bac3512003-03-12 10:41:04 +0000492#endif /* __CONFIG_H */