Blame - arch/arm/mach-socfpga/Kconfig - github/trini/u-boot

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Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Goldschmidt	aef4428	2019-04-09 21:02:05 +0200	[diff] [blame^]	3	config NR_DRAM_BANKS
				4	default 1
				5
				6	config SPL_STACK_R_ADDR
				7	default 0x00800000 if TARGET_SOCFPGA_GEN5
				8
Dalon Westergreen	f0fb4fa	2017-02-10 17:15:34 -0800	[diff] [blame]	9	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				10	default 0xa2
				11
Simon Goldschmidt	aef4428	2019-04-09 21:02:05 +0200	[diff] [blame^]	12	config SYS_MALLOC_F_LEN
				13	default 0x2000 if TARGET_SOCFPGA_ARRIA10
				14	default 0x2000 if TARGET_SOCFPGA_GEN5
				15
				16	config SYS_TEXT_BASE
				17	default 0x01000040 if TARGET_SOCFPGA_ARRIA10
				18	default 0x01000040 if TARGET_SOCFPGA_GEN5
				19
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	20	config TARGET_SOCFPGA_ARRIA5
				21	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	22	select TARGET_SOCFPGA_GEN5
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	23
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	24	config TARGET_SOCFPGA_ARRIA10
				25	bool
Tien Fong Chee	901af3e	2017-12-05 15:58:03 +0800	[diff] [blame]	26	select ALTERA_SDRAM
Michal Simek	58008cb	2018-07-23 15:55:15 +0200	[diff] [blame]	27	select SPL_BOARD_INIT if SPL
Marek Vasut	934aec7	2018-07-30 15:56:19 +0200	[diff] [blame]	28	select CLK
				29	select SPL_CLK if SPL
Marek Vasut	fe88c2f	2018-08-13 18:32:38 +0200	[diff] [blame]	30	select DM_I2C
Marek Vasut	8145c1c	2018-08-13 18:32:38 +0200	[diff] [blame]	31	select DM_RESET
				32	select SPL_DM_RESET if SPL
Marek Vasut	d6a61da	2018-08-13 20:06:46 +0200	[diff] [blame]	33	select REGMAP
				34	select SPL_REGMAP if SPL
				35	select SYSCON
				36	select SPL_SYSCON if SPL
				37	select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidt	aef4428	2019-04-09 21:02:05 +0200	[diff] [blame^]	38	imply FPGA_SOCFPGA
				39	imply USE_TINY_PRINTF
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	40
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	41	config TARGET_SOCFPGA_CYCLONE5
				42	bool
Dinh Nguyen	ed77aeb	2015-12-02 13:31:25 -0600	[diff] [blame]	43	select TARGET_SOCFPGA_GEN5
				44
				45	config TARGET_SOCFPGA_GEN5
				46	bool
Ley Foon Tan	707cd01	2017-04-05 17:32:51 +0800	[diff] [blame]	47	select ALTERA_SDRAM
Simon Goldschmidt	aef4428	2019-04-09 21:02:05 +0200	[diff] [blame^]	48	imply FPGA_SOCFPGA
				49	imply SPL_STACK_R
				50	imply SPL_SYS_MALLOC_SIMPLE
				51	imply USE_TINY_PRINTF
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	52
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	53	config TARGET_SOCFPGA_STRATIX10
				54	bool
				55	select ARMV8_MULTIENTRY
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	56	select ARMV8_SET_SMPEN
Michal Simek	58008cb	2018-07-23 15:55:15 +0200	[diff] [blame]	57	select ARMV8_SPIN_TABLE
Ang, Chee Hong	bd55817	2018-12-19 18:35:16 -0800	[diff] [blame]	58	select FPGA_STRATIX10
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	59
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	60	choice
				61	prompt "Altera SOCFPGA board select"
Joe Hershberger	a26cd04	2015-05-12 14:46:23 -0500	[diff] [blame]	62	optional
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	63
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	64	config TARGET_SOCFPGA_ARRIA10_SOCDK
				65	bool "Altera SOCFPGA SoCDK (Arria 10)"
				66	select TARGET_SOCFPGA_ARRIA10
				67
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	68	config TARGET_SOCFPGA_ARRIA5_SOCDK
				69	bool "Altera SOCFPGA SoCDK (Arria V)"
				70	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	71
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	72	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				73	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				74	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	75
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	76	config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
				77	bool "Devboards DBM-SoC1 (Cyclone V)"
				78	select TARGET_SOCFPGA_CYCLONE5
				79
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	80	config TARGET_SOCFPGA_EBV_SOCRATES
				81	bool "EBV SoCrates (Cyclone V)"
				82	select TARGET_SOCFPGA_CYCLONE5
				83
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	84	config TARGET_SOCFPGA_IS1
				85	bool "IS1 (Cyclone V)"
				86	select TARGET_SOCFPGA_CYCLONE5
				87
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	88	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				89	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	e5ec481	2017-01-22 19:43:11 -0500	[diff] [blame]	90	select BOARD_LATE_INIT
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	91	select TARGET_SOCFPGA_CYCLONE5
				92
Marek Vasut	cf0a8da	2016-06-08 02:57:05 +0200	[diff] [blame]	93	config TARGET_SOCFPGA_SR1500
				94	bool "SR1500 (Cyclone V)"
				95	select TARGET_SOCFPGA_CYCLONE5
				96
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	97	config TARGET_SOCFPGA_STRATIX10_SOCDK
				98	bool "Intel SOCFPGA SoCDK (Stratix 10)"
				99	select TARGET_SOCFPGA_STRATIX10
				100
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	101	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				102	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				103	select TARGET_SOCFPGA_CYCLONE5
				104
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	105	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				106	bool "Terasic DE10-Nano (Cyclone V)"
				107	select TARGET_SOCFPGA_CYCLONE5
				108
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	109	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				110	bool "Terasic DE1-SoC (Cyclone V)"
				111	select TARGET_SOCFPGA_CYCLONE5
				112
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	113	config TARGET_SOCFPGA_TERASIC_SOCKIT
				114	bool "Terasic SoCkit (Cyclone V)"
				115	select TARGET_SOCFPGA_CYCLONE5
				116
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	117	endchoice
				118
				119	config SYS_BOARD
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	120	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	121	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	f089240	2015-08-10 21:24:53 +0200	[diff] [blame]	122	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	123	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	124	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	125	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	126	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	127	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	128	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	129	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	130	default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	131	default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	132	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	133
				134	config SYS_VENDOR
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	135	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	136	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	cd9b731	2015-08-02 21:57:57 +0200	[diff] [blame]	137	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	138	default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	139	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	140	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	141	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	142	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	143	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	144	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	145	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	146
				147	config SYS_SOC
				148	default "socfpga"
				149
				150	config SYS_CONFIG_NAME
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	151	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	d89e979	2017-04-26 02:44:48 +0800	[diff] [blame]	152	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	3cbc7b8	2015-09-22 17:01:32 -0500	[diff] [blame]	153	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	7fb4643	2018-02-24 23:34:00 +0100	[diff] [blame]	154	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	55c7a76	2015-09-01 17:41:52 -0500	[diff] [blame]	155	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	e9c847c	2016-11-14 16:07:10 +0100	[diff] [blame]	156	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	6bd041f	2017-04-18 08:11:16 -0700	[diff] [blame]	157	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	35546f6	2016-06-07 12:37:23 +0200	[diff] [blame]	158	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	952caa2	2015-06-21 17:28:53 +0200	[diff] [blame]	159	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	856b30d	2015-11-23 17:06:27 +0100	[diff] [blame]	160	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	ae9996c	2015-11-18 11:06:09 +0100	[diff] [blame]	161	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan	a684729	2018-05-24 00:17:32 +0800	[diff] [blame]	162	default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut	569a191	2015-12-01 18:09:52 +0100	[diff] [blame]	163	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	7865f4b	2015-04-21 20:38:20 +0900	[diff] [blame]	164
				165	endif