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Masahiro Yamada7865f4b2015-04-21 20:38:20 +09001if ARCH_SOCFPGA
2
Marek Vasutcd9b7312015-08-02 21:57:57 +02003config TARGET_SOCFPGA_ARRIA5
4 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -06005 select TARGET_SOCFPGA_GEN5
Marek Vasutcd9b7312015-08-02 21:57:57 +02006
7config TARGET_SOCFPGA_CYCLONE5
8 bool
Dinh Nguyened77aeb2015-12-02 13:31:25 -06009 select TARGET_SOCFPGA_GEN5
10
11config TARGET_SOCFPGA_GEN5
12 bool
Marek Vasutcd9b7312015-08-02 21:57:57 +020013
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090014choice
15 prompt "Altera SOCFPGA board select"
Joe Hershbergera26cd042015-05-12 14:46:23 -050016 optional
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090017
Marek Vasutcd9b7312015-08-02 21:57:57 +020018config TARGET_SOCFPGA_ARRIA5_SOCDK
19 bool "Altera SOCFPGA SoCDK (Arria V)"
20 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090021
Marek Vasutcd9b7312015-08-02 21:57:57 +020022config TARGET_SOCFPGA_CYCLONE5_SOCDK
23 bool "Altera SOCFPGA SoCDK (Cyclone V)"
24 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090025
Marek Vasutd88995a2015-08-03 01:37:28 +020026config TARGET_SOCFPGA_DENX_MCVEVK
27 bool "DENX MCVEVK (Cyclone V)"
28 select TARGET_SOCFPGA_CYCLONE5
29
Marek Vasut856b30d2015-11-23 17:06:27 +010030config TARGET_SOCFPGA_EBV_SOCRATES
31 bool "EBV SoCrates (Cyclone V)"
32 select TARGET_SOCFPGA_CYCLONE5
33
Pavel Machek35546f62016-06-07 12:37:23 +020034config TARGET_SOCFPGA_IS1
35 bool "IS1 (Cyclone V)"
36 select TARGET_SOCFPGA_CYCLONE5
37
Marek Vasut569a1912015-12-01 18:09:52 +010038config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
39 bool "samtec VIN|ING FPGA (Cyclone V)"
40 select TARGET_SOCFPGA_CYCLONE5
41
Marek Vasutcf0a8da2016-06-08 02:57:05 +020042config TARGET_SOCFPGA_SR1500
43 bool "SR1500 (Cyclone V)"
44 select TARGET_SOCFPGA_CYCLONE5
45
Dinh Nguyen55c7a762015-09-01 17:41:52 -050046config TARGET_SOCFPGA_TERASIC_DE0_NANO
47 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
48 select TARGET_SOCFPGA_CYCLONE5
49
Marek Vasut952caa22015-06-21 17:28:53 +020050config TARGET_SOCFPGA_TERASIC_SOCKIT
51 bool "Terasic SoCkit (Cyclone V)"
52 select TARGET_SOCFPGA_CYCLONE5
53
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090054endchoice
55
56config SYS_BOARD
Marek Vasutf0892402015-08-10 21:24:53 +020057 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
58 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen55c7a762015-09-01 17:41:52 -050059 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek35546f62016-06-07 12:37:23 +020060 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasutd88995a2015-08-03 01:37:28 +020061 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut952caa22015-06-21 17:28:53 +020062 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +010063 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +010064 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut569a1912015-12-01 18:09:52 +010065 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090066
67config SYS_VENDOR
Marek Vasutcd9b7312015-08-02 21:57:57 +020068 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
69 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutd88995a2015-08-03 01:37:28 +020070 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut856b30d2015-11-23 17:06:27 +010071 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut569a1912015-12-01 18:09:52 +010072 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen55c7a762015-09-01 17:41:52 -050073 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut952caa22015-06-21 17:28:53 +020074 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090075
76config SYS_SOC
77 default "socfpga"
78
79config SYS_CONFIG_NAME
Dinh Nguyen3cbc7b82015-09-22 17:01:32 -050080 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
81 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen55c7a762015-09-01 17:41:52 -050082 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek35546f62016-06-07 12:37:23 +020083 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasutd88995a2015-08-03 01:37:28 +020084 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut952caa22015-06-21 17:28:53 +020085 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut856b30d2015-11-23 17:06:27 +010086 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roeseae9996c2015-11-18 11:06:09 +010087 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut569a1912015-12-01 18:09:52 +010088 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada7865f4b2015-04-21 20:38:20 +090089
90endif