Wolfgang Denk | 46263f2 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 1 | /* |
Wolfgang Denk | 1b387ef | 2013-09-17 11:24:06 +0200 | [diff] [blame] | 2 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 3 | * |
| 4 | * File Name: 405gp_pci.c |
| 5 | * |
| 6 | * Function: Initialization code for the 405GP PCI Configuration regs. |
| 7 | * |
| 8 | * Author: Mark Game |
| 9 | * |
| 10 | * Change Activity- |
| 11 | * |
| 12 | * Date Description of Change BY |
| 13 | * --------- --------------------- --- |
| 14 | * 09-Sep-98 Created MCG |
| 15 | * 02-Nov-98 Removed External arbiter selected message JWB |
| 16 | * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB |
| 17 | * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG |
| 18 | * from (0 to n) to (1 to n). |
| 19 | * 17-May-99 Port to Walnut JWB |
| 20 | * 17-Jun-99 Updated for VGA support JWB |
| 21 | * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB |
| 22 | * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG |
| 23 | * target latency timer values are not supported). |
| 24 | * Should be fixed in pass 2. |
| 25 | * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB |
| 26 | * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. |
| 27 | * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB |
| 28 | * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not |
| 29 | * really required after a reset since PMMxMAs are already |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 30 | * disabled but is a good practice nonetheless. JWB |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 31 | * 12-Jun-01 stefan.roese@esd-electronics.com |
| 32 | * - PCI host/adapter handling reworked |
| 33 | * 09-Jul-01 stefan.roese@esd-electronics.com |
| 34 | * - PCI host now configures from device 0 (not 1) to max_dev, |
| 35 | * (host configures itself) |
| 36 | * - On CPCI-405 pci base address and size is generated from |
| 37 | * SDRAM and FLASH size (CFG regs not used anymore) |
| 38 | * - Some minor changes for CPCI-405-A (adapter version) |
| 39 | * 14-Sep-01 stefan.roese@esd-electronics.com |
| 40 | * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup |
| 41 | * 28-Sep-01 stefan.roese@esd-electronics.com |
| 42 | * - Changed pci master configuration for linux compatibility |
| 43 | * (no need for bios_fixup() anymore) |
| 44 | * 26-Feb-02 stefan.roese@esd-electronics.com |
| 45 | * - Bug fixed in pci configuration (Andrew May) |
| 46 | * - Removed pci class code init for CPCI405 board |
| 47 | * 15-May-02 stefan.roese@esd-electronics.com |
| 48 | * - New vga device handling |
| 49 | * 29-May-02 stefan.roese@esd-electronics.com |
| 50 | * - PCI class code init added (if defined) |
| 51 | *----------------------------------------------------------------------------*/ |
| 52 | |
| 53 | #include <common.h> |
| 54 | #include <command.h> |
Stefan Roese | 3048bcb | 2007-10-03 15:01:02 +0200 | [diff] [blame] | 55 | #include <asm/4xx_pci.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 56 | #include <asm/processor.h> |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 57 | #include <asm/io.h> |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 58 | #include <pci.h> |
| 59 | |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 60 | #ifdef CONFIG_PCI |
| 61 | |
Wolfgang Denk | d87080b | 2006-03-31 18:32:53 +0200 | [diff] [blame] | 62 | DECLARE_GLOBAL_DATA_PTR; |
| 63 | |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 64 | #if defined(CONFIG_405GP) || defined(CONFIG_405EP) |
| 65 | |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 66 | /*#define DEBUG*/ |
| 67 | |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 68 | /* |
| 69 | * Board-specific pci initialization |
| 70 | * Platform code can reimplement pci_pre_init() if needed |
| 71 | */ |
| 72 | int __pci_pre_init(struct pci_controller *hose) |
| 73 | { |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 74 | #if defined(CONFIG_405EP) |
Matthias Fuchs | 123f102 | 2009-07-08 13:43:55 +0200 | [diff] [blame] | 75 | /* |
| 76 | * Enable the internal PCI arbiter by default. |
| 77 | * |
| 78 | * On 405EP CPUs the internal arbiter can be controlled |
| 79 | * by the I2C strapping EEPROM. If you want to do so |
| 80 | * or if you want to disable the arbiter pci_pre_init() |
| 81 | * must be reimplemented without enabling the arbiter. |
| 82 | * The arbiter is enabled in this place because of |
| 83 | * compatibility reasons. |
| 84 | */ |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 85 | mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN); |
Matthias Fuchs | 123f102 | 2009-07-08 13:43:55 +0200 | [diff] [blame] | 86 | #endif /* CONFIG_405EP */ |
| 87 | |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 88 | return 1; |
| 89 | } |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 90 | int pci_pre_init(struct pci_controller *hose) |
| 91 | __attribute__((weak, alias("__pci_pre_init"))); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 92 | |
Matthias Fuchs | d0a1364 | 2009-07-03 16:06:06 +0200 | [diff] [blame] | 93 | int __is_pci_host(struct pci_controller *hose) |
| 94 | { |
| 95 | #if defined(CONFIG_405GP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 96 | if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) |
Matthias Fuchs | d0a1364 | 2009-07-03 16:06:06 +0200 | [diff] [blame] | 97 | return 1; |
| 98 | #elif defined (CONFIG_405EP) |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 99 | if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN) |
Matthias Fuchs | d0a1364 | 2009-07-03 16:06:06 +0200 | [diff] [blame] | 100 | return 1; |
| 101 | #endif |
| 102 | return 0; |
| 103 | } |
| 104 | int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host"))); |
| 105 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 106 | /*-----------------------------------------------------------------------------+ |
| 107 | * pci_init. Initializes the 405GP PCI Configuration regs. |
| 108 | *-----------------------------------------------------------------------------*/ |
| 109 | void pci_405gp_init(struct pci_controller *hose) |
| 110 | { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 111 | int i, reg_num = 0; |
| 112 | bd_t *bd = gd->bd; |
| 113 | |
| 114 | unsigned short temp_short; |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 115 | unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI}; |
Matthias Fuchs | 99bcf14 | 2009-09-07 17:00:40 +0200 | [diff] [blame] | 116 | #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) |
stroese | fddae7b | 2005-04-20 06:52:40 +0000 | [diff] [blame] | 117 | char *ptmla_str, *ptmms_str; |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 118 | #endif |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; |
| 120 | unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS}; |
Tom Rini | adf32ad | 2016-09-19 21:55:34 -0400 | [diff] [blame^] | 121 | #if defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ |
| 122 | || defined(CONFIG_TARGET_MIP405T) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 123 | unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; |
| 124 | unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; |
| 125 | unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; |
| 126 | unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; |
| 127 | #else |
| 128 | unsigned long pmmla[3] = {0x80000000, 0,0}; |
| 129 | unsigned long pmmma[3] = {0xC0000001, 0,0}; |
| 130 | unsigned long pmmpcila[3] = {0x80000000, 0,0}; |
| 131 | unsigned long pmmpciha[3] = {0x00000000, 0,0}; |
| 132 | #endif |
stroese | 5e746fc | 2004-12-16 18:15:52 +0000 | [diff] [blame] | 133 | #ifdef CONFIG_PCI_PNP |
| 134 | #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) |
| 135 | char *s; |
| 136 | #endif |
| 137 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 138 | |
Matthias Fuchs | 99bcf14 | 2009-09-07 17:00:40 +0200 | [diff] [blame] | 139 | #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) |
stroese | fddae7b | 2005-04-20 06:52:40 +0000 | [diff] [blame] | 140 | ptmla_str = getenv("ptm1la"); |
| 141 | ptmms_str = getenv("ptm1ms"); |
| 142 | if(NULL != ptmla_str && NULL != ptmms_str ) { |
Wolfgang Denk | 93e1459 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 143 | ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); |
stroese | fddae7b | 2005-04-20 06:52:40 +0000 | [diff] [blame] | 144 | ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); |
| 145 | } |
| 146 | |
| 147 | ptmla_str = getenv("ptm2la"); |
| 148 | ptmms_str = getenv("ptm2ms"); |
| 149 | if(NULL != ptmla_str && NULL != ptmms_str ) { |
Wolfgang Denk | 93e1459 | 2013-10-04 17:43:24 +0200 | [diff] [blame] | 150 | ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); |
stroese | fddae7b | 2005-04-20 06:52:40 +0000 | [diff] [blame] | 151 | ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); |
| 152 | } |
| 153 | #endif |
| 154 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 155 | /* |
| 156 | * Register the hose |
| 157 | */ |
| 158 | hose->first_busno = 0; |
| 159 | hose->last_busno = 0xff; |
| 160 | |
| 161 | /* ISA/PCI I/O space */ |
| 162 | pci_set_region(hose->regions + reg_num++, |
| 163 | MIN_PCI_PCI_IOADDR, |
| 164 | MIN_PLB_PCI_IOADDR, |
| 165 | 0x10000, |
| 166 | PCI_REGION_IO); |
| 167 | |
| 168 | /* PCI I/O space */ |
| 169 | pci_set_region(hose->regions + reg_num++, |
| 170 | 0x00800000, |
| 171 | 0xe8800000, |
| 172 | 0x03800000, |
| 173 | PCI_REGION_IO); |
| 174 | |
| 175 | reg_num = 2; |
| 176 | |
| 177 | /* Memory spaces */ |
| 178 | for (i=0; i<2; i++) |
| 179 | if (ptmms[i] & 1) |
| 180 | { |
| 181 | if (!i) hose->pci_fb = hose->regions + reg_num; |
| 182 | |
| 183 | pci_set_region(hose->regions + reg_num++, |
| 184 | ptmpcila[i], ptmla[i], |
| 185 | ~(ptmms[i] & 0xfffff000) + 1, |
| 186 | PCI_REGION_MEM | |
Kumar Gala | ff4e66e | 2009-02-06 09:49:31 -0600 | [diff] [blame] | 187 | PCI_REGION_SYS_MEMORY); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 188 | } |
| 189 | |
| 190 | /* PCI memory spaces */ |
| 191 | for (i=0; i<3; i++) |
| 192 | if (pmmma[i] & 1) |
| 193 | { |
| 194 | pci_set_region(hose->regions + reg_num++, |
| 195 | pmmpcila[i], pmmla[i], |
| 196 | ~(pmmma[i] & 0xfffff000) + 1, |
| 197 | PCI_REGION_MEM); |
| 198 | } |
| 199 | |
| 200 | hose->region_count = reg_num; |
| 201 | |
| 202 | pci_setup_indirect(hose, |
| 203 | PCICFGADR, |
| 204 | PCICFGDATA); |
| 205 | |
| 206 | if (hose->pci_fb) |
| 207 | pciauto_region_init(hose->pci_fb); |
| 208 | |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 209 | /* Let board change/modify hose & do initial checks */ |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 210 | if (pci_pre_init(hose) == 0) { |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 211 | printf("PCI: Board-specific initialization failed.\n"); |
| 212 | printf("PCI: Configuration aborted.\n"); |
| 213 | return; |
| 214 | } |
| 215 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 216 | pci_register_hose(hose); |
| 217 | |
| 218 | /*--------------------------------------------------------------------------+ |
| 219 | * 405GP PCI Master configuration. |
| 220 | * Map one 512 MB range of PLB/processor addresses to PCI memory space. |
| 221 | * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF |
| 222 | * Use byte reversed out routines to handle endianess. |
| 223 | *--------------------------------------------------------------------------*/ |
wdenk | f3e0de6 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 224 | out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 225 | out32r(PMM0LA, pmmla[0]); |
| 226 | out32r(PMM0PCILA, pmmpcila[0]); |
| 227 | out32r(PMM0PCIHA, pmmpciha[0]); |
| 228 | out32r(PMM0MA, pmmma[0]); |
| 229 | |
| 230 | /*--------------------------------------------------------------------------+ |
| 231 | * PMM1 is not used. Initialize them to zero. |
| 232 | *--------------------------------------------------------------------------*/ |
wdenk | f3e0de6 | 2003-06-04 15:05:30 +0000 | [diff] [blame] | 233 | out32r(PMM1MA, (pmmma[1]&~0x1)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 234 | out32r(PMM1LA, pmmla[1]); |
| 235 | out32r(PMM1PCILA, pmmpcila[1]); |
| 236 | out32r(PMM1PCIHA, pmmpciha[1]); |
| 237 | out32r(PMM1MA, pmmma[1]); |
| 238 | |
| 239 | /*--------------------------------------------------------------------------+ |
| 240 | * PMM2 is not used. Initialize them to zero. |
| 241 | *--------------------------------------------------------------------------*/ |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 242 | out32r(PMM2MA, (pmmma[2]&~0x1)); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 243 | out32r(PMM2LA, pmmla[2]); |
| 244 | out32r(PMM2PCILA, pmmpcila[2]); |
| 245 | out32r(PMM2PCIHA, pmmpciha[2]); |
| 246 | out32r(PMM2MA, pmmma[2]); |
| 247 | |
| 248 | /*--------------------------------------------------------------------------+ |
| 249 | * 405GP PCI Target configuration. (PTM1) |
| 250 | * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. |
| 251 | *--------------------------------------------------------------------------*/ |
| 252 | out32r(PTM1LA, ptmla[0]); /* insert address */ |
| 253 | out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ |
wdenk | 4654af2 | 2003-10-22 09:00:28 +0000 | [diff] [blame] | 254 | pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 255 | |
| 256 | /*--------------------------------------------------------------------------+ |
| 257 | * 405GP PCI Target configuration. (PTM2) |
| 258 | *--------------------------------------------------------------------------*/ |
| 259 | out32r(PTM2LA, ptmla[1]); /* insert address */ |
wdenk | 4654af2 | 2003-10-22 09:00:28 +0000 | [diff] [blame] | 260 | pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); |
| 261 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 262 | if (ptmms[1] == 0) |
| 263 | { |
| 264 | out32r(PTM2MS, 0x00000001); /* set enable bit */ |
| 265 | pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); |
| 266 | out32r(PTM2MS, 0x00000000); /* disable */ |
| 267 | } |
| 268 | else |
| 269 | { |
| 270 | out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ |
| 271 | } |
| 272 | |
| 273 | /* |
| 274 | * Insert Subsystem Vendor and Device ID |
| 275 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 276 | pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 277 | #ifdef CONFIG_CPCI405 |
Matthias Fuchs | d0a1364 | 2009-07-03 16:06:06 +0200 | [diff] [blame] | 278 | if (is_pci_host(hose)) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 279 | pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 280 | else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 281 | pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 282 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 283 | pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 284 | #endif |
| 285 | |
| 286 | /* |
| 287 | * Insert Class-code |
| 288 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 289 | #ifdef CONFIG_SYS_PCI_CLASSCODE |
| 290 | pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE); |
| 291 | #endif /* CONFIG_SYS_PCI_CLASSCODE */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 292 | |
| 293 | /*--------------------------------------------------------------------------+ |
Wolfgang Denk | 8ed44d9 | 2008-10-19 02:35:50 +0200 | [diff] [blame] | 294 | * If PCI speed = 66MHz, set 66MHz capable bit. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 295 | *--------------------------------------------------------------------------*/ |
| 296 | if (bd->bi_pci_busfreq >= 66000000) { |
| 297 | pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); |
| 298 | pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); |
| 299 | } |
| 300 | |
| 301 | #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) |
wdenk | 4654af2 | 2003-10-22 09:00:28 +0000 | [diff] [blame] | 302 | #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) |
Matthias Fuchs | d0a1364 | 2009-07-03 16:06:06 +0200 | [diff] [blame] | 303 | if (is_pci_host(hose) || |
stroese | 5e746fc | 2004-12-16 18:15:52 +0000 | [diff] [blame] | 304 | (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 305 | #endif |
| 306 | { |
| 307 | /*--------------------------------------------------------------------------+ |
| 308 | * Write the 405GP PCI Configuration regs. |
| 309 | * Enable 405GP to be a master on the PCI bus (PMM). |
| 310 | * Enable 405GP to act as a PCI memory target (PTM). |
| 311 | *--------------------------------------------------------------------------*/ |
| 312 | pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); |
| 313 | pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | |
| 314 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 315 | } |
| 316 | #endif |
| 317 | |
Matthias Fuchs | 632e9b6 | 2009-07-08 15:31:57 +0200 | [diff] [blame] | 318 | #if defined(CONFIG_405EP) |
| 319 | /* |
| 320 | * on ppc405ep vendor/device id is not set |
| 321 | * The user manual says 0x1014 (IBM) / 0x0156 (405GP!) |
| 322 | * are the correct values. |
| 323 | */ |
| 324 | pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM); |
| 325 | pci_write_config_word(PCIDEVID_405GP, |
| 326 | PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP); |
stroese | 428c563 | 2003-09-12 08:52:09 +0000 | [diff] [blame] | 327 | #endif |
| 328 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 329 | /* |
| 330 | * Set HCE bit (Host Configuration Enabled) |
| 331 | */ |
| 332 | pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); |
| 333 | pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); |
| 334 | |
| 335 | #ifdef CONFIG_PCI_PNP |
| 336 | /*--------------------------------------------------------------------------+ |
| 337 | * Scan the PCI bus and configure devices found. |
| 338 | *--------------------------------------------------------------------------*/ |
| 339 | #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) |
Matthias Fuchs | d0a1364 | 2009-07-03 16:06:06 +0200 | [diff] [blame] | 340 | if (is_pci_host(hose) || |
stroese | 5e746fc | 2004-12-16 18:15:52 +0000 | [diff] [blame] | 341 | (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 342 | #endif |
| 343 | { |
| 344 | #ifdef CONFIG_PCI_SCAN_SHOW |
| 345 | printf("PCI: Bus Dev VenId DevId Class Int\n"); |
| 346 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 347 | hose->last_busno = pci_hose_scan(hose); |
| 348 | } |
| 349 | #endif /* CONFIG_PCI_PNP */ |
| 350 | |
| 351 | } |
| 352 | |
| 353 | /* |
Marcel Ziswiler | 7817cb2 | 2007-12-30 03:30:46 +0100 | [diff] [blame] | 354 | * drivers/pci/pci.c skips every host bridge but the 405GP since it could |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 355 | * be set as an Adapter. |
| 356 | * |
| 357 | * I (Andrew May) don't know what we should do here, but I don't want |
| 358 | * the auto setup of a PCI device disabling what is done pci_405gp_init |
| 359 | * as has happened before. |
| 360 | */ |
| 361 | void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, |
| 362 | struct pci_config_table *entry) |
| 363 | { |
| 364 | #ifdef DEBUG |
wdenk | 8bde7f7 | 2003-06-27 21:31:46 +0000 | [diff] [blame] | 365 | printf("405gp_setup_bridge\n"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 366 | #endif |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * |
| 371 | */ |
| 372 | |
| 373 | void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) |
| 374 | { |
| 375 | unsigned char int_line = 0xff; |
| 376 | |
| 377 | /* |
| 378 | * Write pci interrupt line register (cpci405 specific) |
| 379 | */ |
| 380 | switch (PCI_DEV(dev) & 0x03) |
| 381 | { |
| 382 | case 0: |
| 383 | int_line = 27 + 2; |
| 384 | break; |
| 385 | case 1: |
| 386 | int_line = 27 + 3; |
| 387 | break; |
| 388 | case 2: |
| 389 | int_line = 27 + 0; |
| 390 | break; |
| 391 | case 3: |
| 392 | int_line = 27 + 1; |
| 393 | break; |
| 394 | } |
| 395 | |
| 396 | pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); |
| 397 | } |
| 398 | |
| 399 | void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, |
| 400 | struct pci_config_table *entry) |
| 401 | { |
| 402 | unsigned int cmdstat = 0; |
| 403 | |
Stefan Roese | f3fecfe | 2006-03-13 09:43:01 +0100 | [diff] [blame] | 404 | pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 405 | |
| 406 | /* always enable io space on vga boards */ |
| 407 | pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); |
| 408 | cmdstat |= PCI_COMMAND_IO; |
| 409 | pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); |
| 410 | } |
| 411 | |
Tom Rini | adf32ad | 2016-09-19 21:55:34 -0400 | [diff] [blame^] | 412 | #if !(defined(CONFIG_PIP405) || defined(CONFIG_TARGET_MIP405) \ |
| 413 | || defined(CONFIG_TARGET_MIP405T)) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 414 | |
| 415 | /* |
| 416 | *As is these functs get called out of flash Not a horrible |
| 417 | *thing, but something to keep in mind. (no statics?) |
| 418 | */ |
| 419 | static struct pci_config_table pci_405gp_config_table[] = { |
| 420 | /*if VendID is 0 it terminates the table search (ie Walnut)*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 421 | #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID |
| 422 | {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 423 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, |
| 424 | #endif |
| 425 | {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, |
| 426 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, |
| 427 | |
| 428 | {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, |
| 429 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, |
| 430 | |
| 431 | { } |
| 432 | }; |
| 433 | |
| 434 | static struct pci_controller hose = { |
| 435 | fixup_irq: pci_405gp_fixup_irq, |
| 436 | config_table: pci_405gp_config_table, |
| 437 | }; |
| 438 | |
stroese | ad10dd9 | 2003-02-14 11:21:23 +0000 | [diff] [blame] | 439 | void pci_init_board(void) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 440 | { |
| 441 | /*we want the ptrs to RAM not flash (ie don't use init list)*/ |
| 442 | hose.fixup_irq = pci_405gp_fixup_irq; |
| 443 | hose.config_table = pci_405gp_config_table; |
| 444 | pci_405gp_init(&hose); |
| 445 | } |
| 446 | |
| 447 | #endif |
| 448 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 449 | #endif /* CONFIG_405GP */ |
| 450 | |
| 451 | /*-----------------------------------------------------------------------------+ |
| 452 | * CONFIG_440 |
| 453 | *-----------------------------------------------------------------------------*/ |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 454 | #if defined(CONFIG_440) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 455 | |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 456 | #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 457 | static struct pci_controller ppc440_hose = {0}; |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 458 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 459 | |
Stefan Roese | 9a81c61 | 2009-10-29 16:54:52 +0100 | [diff] [blame] | 460 | /* |
| 461 | * This routine is called to determine if a pci scan should be |
| 462 | * performed. With various hardware environments (especially cPCI and |
| 463 | * PPMC) it's insufficient to depend on the state of the arbiter enable |
| 464 | * bit in the strap register, or generic host/adapter assumptions. |
| 465 | * |
| 466 | * Rather than hard-code a bad assumption in the general 440 code, the |
| 467 | * 440 pci code requires the board to decide at runtime. |
| 468 | * |
| 469 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
| 470 | * |
| 471 | * Weak default implementation: "Normal" boards implement the PCI |
| 472 | * host functionality. This can be overridden for PCI adapter boards. |
| 473 | */ |
| 474 | int __is_pci_host(struct pci_controller *hose) |
| 475 | { |
| 476 | return 1; |
| 477 | } |
| 478 | int is_pci_host(struct pci_controller *hose) |
| 479 | __attribute__((weak, alias("__is_pci_host"))); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 480 | |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 481 | #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ |
| 482 | defined(CONFIG_440GR) || defined(CONFIG_440GRX) |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 483 | |
| 484 | #if defined(CONFIG_SYS_PCI_TARGET_INIT) |
| 485 | /* |
| 486 | * pci_target_init |
| 487 | * |
| 488 | * The bootstrap configuration provides default settings for the pci |
| 489 | * inbound map (PIM). But the bootstrap config choices are limited and |
| 490 | * may not be sufficient for a given board. |
| 491 | */ |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 492 | void __pci_target_init(struct pci_controller *hose) |
| 493 | { |
| 494 | /* |
| 495 | * Set up Direct MMIO registers |
| 496 | */ |
| 497 | |
| 498 | /* |
| 499 | * PowerPC440 EP PCI Master configuration. |
| 500 | * Map one 1Gig range of PLB/processor addresses to PCI memory space. |
| 501 | * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF |
| 502 | * Use byte reversed out routines to handle endianess. |
| 503 | * Make this region non-prefetchable. |
| 504 | */ |
| 505 | /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 506 | out_le32((void *)PCIL0_PMM0MA, 0x00000000); |
| 507 | /* PMM0 Local Address */ |
| 508 | out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); |
| 509 | /* PMM0 PCI Low Address */ |
| 510 | out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); |
| 511 | /* PMM0 PCI High Address */ |
| 512 | out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000); |
| 513 | /* 512M + No prefetching, and enable region */ |
| 514 | out_le32((void *)PCIL0_PMM0MA, 0xE0000001); |
| 515 | |
| 516 | /* PMM1 Mask/Attribute - disabled b4 setting */ |
| 517 | out_le32((void *)PCIL0_PMM1MA, 0x00000000); |
| 518 | /* PMM1 Local Address */ |
| 519 | out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); |
| 520 | /* PMM1 PCI Low Address */ |
| 521 | out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); |
| 522 | /* PMM1 PCI High Address */ |
| 523 | out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000); |
| 524 | /* 512M + No prefetching, and enable region */ |
| 525 | out_le32((void *)PCIL0_PMM1MA, 0xE0000001); |
| 526 | |
| 527 | out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
| 528 | out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */ |
| 529 | out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ |
| 530 | out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */ |
| 531 | |
| 532 | /* |
| 533 | * Set up Configuration registers |
| 534 | */ |
| 535 | |
| 536 | /* Program the board's subsystem id/vendor id */ |
| 537 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
| 538 | CONFIG_SYS_PCI_SUBSYS_VENDORID); |
| 539 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); |
| 540 | |
| 541 | /* Configure command register as bus master */ |
| 542 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 543 | |
| 544 | /* 240nS PCI clock */ |
| 545 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
| 546 | |
| 547 | /* No error reporting */ |
| 548 | pci_write_config_word(0, PCI_ERREN, 0); |
| 549 | |
| 550 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
| 551 | } |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 552 | #endif /* CONFIG_SYS_PCI_TARGET_INIT */ |
| 553 | |
| 554 | /* |
| 555 | * pci_pre_init |
| 556 | * |
| 557 | * This routine is called just prior to registering the hose and gives |
| 558 | * the board the opportunity to check things. Returning a value of zero |
| 559 | * indicates that things are bad & PCI initialization should be aborted. |
| 560 | * |
| 561 | * Different boards may wish to customize the pci controller structure |
| 562 | * (add regions, override default access routines, etc) or perform |
| 563 | * certain pre-initialization actions. |
| 564 | * |
| 565 | */ |
| 566 | int __pci_pre_init(struct pci_controller *hose) |
| 567 | { |
| 568 | u32 reg; |
| 569 | |
| 570 | /* |
| 571 | * Set priority for all PLB3 devices to 0. |
| 572 | * Set PLB3 arbiter to fair mode. |
| 573 | */ |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 574 | mfsdr(SDR0_AMP1, reg); |
| 575 | mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00); |
| 576 | reg = mfdcr(PLB3A0_ACR); |
| 577 | mtdcr(PLB3A0_ACR, reg | 0x80000000); |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 578 | |
| 579 | /* |
| 580 | * Set priority for all PLB4 devices to 0. |
| 581 | */ |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 582 | mfsdr(SDR0_AMP0, reg); |
| 583 | mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00); |
| 584 | reg = mfdcr(PLB4A0_ACR) | 0xa0000000; |
| 585 | mtdcr(PLB4A0_ACR, reg); |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 586 | |
| 587 | /* |
| 588 | * Set Nebula PLB4 arbiter to fair mode. |
| 589 | */ |
| 590 | /* Segment0 */ |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 591 | reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; |
| 592 | reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; |
| 593 | reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; |
| 594 | reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; |
| 595 | mtdcr(PLB4A0_ACR, reg); |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 596 | |
| 597 | /* Segment1 */ |
Stefan Roese | 5e7abce | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 598 | reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; |
| 599 | reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; |
| 600 | reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; |
| 601 | reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; |
| 602 | mtdcr(PLB4A1_ACR, reg); |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 603 | |
| 604 | #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ) |
| 605 | hose->fixup_irq = board_pci_fixup_irq; |
| 606 | #endif |
| 607 | |
| 608 | return 1; |
| 609 | } |
| 610 | |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 611 | #else /* defined(CONFIG_440EP) ... */ |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 612 | |
| 613 | #if defined(CONFIG_SYS_PCI_TARGET_INIT) |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 614 | void __pci_target_init(struct pci_controller * hose) |
| 615 | { |
| 616 | /* |
| 617 | * Disable everything |
| 618 | */ |
| 619 | out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ |
| 620 | out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ |
| 621 | out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ |
| 622 | out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ |
| 623 | |
| 624 | /* |
| 625 | * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 |
| 626 | * strapping options do not support sizes such as 128/256 MB. |
| 627 | */ |
| 628 | out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); |
| 629 | out_le32((void *)PCIL0_PIM0LAH, 0); |
| 630 | out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); |
| 631 | out_le32((void *)PCIL0_BAR0, 0); |
| 632 | |
| 633 | /* |
| 634 | * Program the board's subsystem id/vendor id |
| 635 | */ |
| 636 | out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); |
| 637 | out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); |
| 638 | |
| 639 | out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) | |
| 640 | PCI_COMMAND_MEMORY); |
| 641 | } |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 642 | #endif /* CONFIG_SYS_PCI_TARGET_INIT */ |
| 643 | |
| 644 | int __pci_pre_init(struct pci_controller *hose) |
| 645 | { |
| 646 | /* |
| 647 | * This board is always configured as the host & requires the |
| 648 | * PCI arbiter to be enabled. |
| 649 | */ |
| 650 | if (!pci_arbiter_enabled()) { |
| 651 | printf("PCI: PCI Arbiter disabled!\n"); |
| 652 | return 0; |
| 653 | } |
| 654 | |
| 655 | return 1; |
| 656 | } |
| 657 | |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 658 | #endif /* defined(CONFIG_440EP) ... */ |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 659 | |
| 660 | #if defined(CONFIG_SYS_PCI_TARGET_INIT) |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 661 | void pci_target_init(struct pci_controller * hose) |
| 662 | __attribute__((weak, alias("__pci_target_init"))); |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 663 | #endif /* CONFIG_SYS_PCI_TARGET_INIT */ |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 664 | |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 665 | int pci_pre_init(struct pci_controller *hose) |
| 666 | __attribute__((weak, alias("__pci_pre_init"))); |
Stefan Roese | 1095493 | 2009-11-12 12:00:49 +0100 | [diff] [blame] | 667 | |
Stefan Roese | 6c70049 | 2009-11-12 17:19:37 +0100 | [diff] [blame] | 668 | #if defined(CONFIG_SYS_PCI_MASTER_INIT) |
| 669 | void __pci_master_init(struct pci_controller *hose) |
| 670 | { |
| 671 | u16 reg; |
| 672 | |
| 673 | /* |
| 674 | * Write the PowerPC440 EP PCI Configuration regs. |
| 675 | * Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
| 676 | * Enable PowerPC440 EP to act as a PCI memory target (PTM). |
| 677 | */ |
| 678 | pci_read_config_word(0, PCI_COMMAND, ®); |
| 679 | pci_write_config_word(0, PCI_COMMAND, reg | |
| 680 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 681 | } |
| 682 | void pci_master_init(struct pci_controller *hose) |
| 683 | __attribute__((weak, alias("__pci_master_init"))); |
| 684 | #endif /* CONFIG_SYS_PCI_MASTER_INIT */ |
| 685 | |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 686 | #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT) |
Wolfgang Denk | e5d5ed4 | 2011-10-29 09:38:31 +0000 | [diff] [blame] | 687 | static int pci_440_init (struct pci_controller *hose) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 688 | { |
| 689 | int reg_num = 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 690 | |
Stefan Roese | 5568e61 | 2005-11-22 13:20:42 +0100 | [diff] [blame] | 691 | #ifndef CONFIG_DISABLE_PISE_TEST |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 692 | /*--------------------------------------------------------------------------+ |
| 693 | * The PCI initialization sequence enable bit must be set ... if not abort |
wdenk | 3c74e32 | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 694 | * pci setup since updating the bit requires chip reset. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 695 | *--------------------------------------------------------------------------*/ |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 696 | #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
Stefan Roese | 5568e61 | 2005-11-22 13:20:42 +0100 | [diff] [blame] | 697 | unsigned long strap; |
| 698 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 699 | mfsdr(SDR0_SDSTP1,strap); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 700 | if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { |
wdenk | 3c74e32 | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 701 | printf("PCI: SDR0_STRP1[PISE] not set.\n"); |
| 702 | printf("PCI: Configuration aborted.\n"); |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 703 | return -1; |
wdenk | 3c74e32 | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 704 | } |
Stefan Roese | 5568e61 | 2005-11-22 13:20:42 +0100 | [diff] [blame] | 705 | #elif defined(CONFIG_440GP) |
| 706 | unsigned long strap; |
| 707 | |
Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 708 | strap = mfdcr(CPC0_STRP1); |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 709 | if ((strap & CPC0_STRP1_PISE_MASK) == 0) { |
wdenk | 3c74e32 | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 710 | printf("PCI: CPC0_STRP1[PISE] not set.\n"); |
| 711 | printf("PCI: Configuration aborted.\n"); |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 712 | return -1; |
wdenk | 3c74e32 | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 713 | } |
| 714 | #endif |
Stefan Roese | 5568e61 | 2005-11-22 13:20:42 +0100 | [diff] [blame] | 715 | #endif /* CONFIG_DISABLE_PISE_TEST */ |
| 716 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 717 | /*--------------------------------------------------------------------------+ |
| 718 | * PCI controller init |
| 719 | *--------------------------------------------------------------------------*/ |
| 720 | hose->first_busno = 0; |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 721 | hose->last_busno = 0; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 722 | |
Marian Balakowicz | fbb0b55 | 2006-07-04 00:55:47 +0200 | [diff] [blame] | 723 | /* PCI I/O space */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 724 | pci_set_region(hose->regions + reg_num++, |
| 725 | 0x00000000, |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 726 | PCIL0_IOBASE, |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 727 | 0x10000, |
| 728 | PCI_REGION_IO); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 729 | |
Marian Balakowicz | fbb0b55 | 2006-07-04 00:55:47 +0200 | [diff] [blame] | 730 | /* PCI memory space */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 731 | pci_set_region(hose->regions + reg_num++, |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 732 | CONFIG_SYS_PCI_TARGBASE, |
| 733 | CONFIG_SYS_PCI_MEMBASE, |
| 734 | #ifdef CONFIG_SYS_PCI_MEMSIZE |
| 735 | CONFIG_SYS_PCI_MEMSIZE, |
Stefan Roese | 899620c | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 736 | #else |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 737 | 0x10000000, |
Stefan Roese | 899620c | 2006-08-15 14:22:35 +0200 | [diff] [blame] | 738 | #endif |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 739 | PCI_REGION_MEM ); |
Marian Balakowicz | fbb0b55 | 2006-07-04 00:55:47 +0200 | [diff] [blame] | 740 | |
| 741 | #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ |
| 742 | defined(CONFIG_PCI_SYS_MEM_SIZE) |
| 743 | /* System memory space */ |
| 744 | pci_set_region(hose->regions + reg_num++, |
| 745 | CONFIG_PCI_SYS_MEM_BUS, |
| 746 | CONFIG_PCI_SYS_MEM_PHYS, |
| 747 | CONFIG_PCI_SYS_MEM_SIZE, |
Kumar Gala | ff4e66e | 2009-02-06 09:49:31 -0600 | [diff] [blame] | 748 | PCI_REGION_MEM | PCI_REGION_SYS_MEMORY ); |
Marian Balakowicz | fbb0b55 | 2006-07-04 00:55:47 +0200 | [diff] [blame] | 749 | #endif |
| 750 | |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 751 | hose->region_count = reg_num; |
| 752 | |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 753 | pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 754 | |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 755 | /* Let board change/modify hose & do initial checks */ |
Stefan Roese | a760b02 | 2009-11-12 16:41:09 +0100 | [diff] [blame] | 756 | if (pci_pre_init(hose) == 0) { |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 757 | printf("PCI: Board-specific initialization failed.\n"); |
| 758 | printf("PCI: Configuration aborted.\n"); |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 759 | return -1; |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 760 | } |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 761 | |
| 762 | pci_register_hose( hose ); |
| 763 | |
| 764 | /*--------------------------------------------------------------------------+ |
| 765 | * PCI target init |
| 766 | *--------------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 767 | #if defined(CONFIG_SYS_PCI_TARGET_INIT) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 768 | pci_target_init(hose); /* Let board setup pci target */ |
| 769 | #else |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 770 | out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); |
| 771 | out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); |
| 772 | out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */ |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 773 | #endif |
| 774 | |
Stefan Roese | 8ac41e3 | 2008-03-11 15:05:26 +0100 | [diff] [blame] | 775 | #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ |
| 776 | defined(CONFIG_460EX) || defined(CONFIG_460GT) |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 777 | out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ |
| 778 | out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ |
| 779 | #elif defined(PCIL0_BRDGOPT1) |
| 780 | out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ |
| 781 | out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */ |
wdenk | 3c74e32 | 2004-02-22 23:46:08 +0000 | [diff] [blame] | 782 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 783 | |
| 784 | /*--------------------------------------------------------------------------+ |
| 785 | * PCI master init: default is one 256MB region for PCI memory: |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 786 | * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 787 | *--------------------------------------------------------------------------*/ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 788 | #if defined(CONFIG_SYS_PCI_MASTER_INIT) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 789 | pci_master_init(hose); /* Let board setup pci master */ |
| 790 | #else |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 791 | out32r( PCIL0_POM0SA, 0 ); /* disable */ |
| 792 | out32r( PCIL0_POM1SA, 0 ); /* disable */ |
| 793 | out32r( PCIL0_POM2SA, 0 ); /* disable */ |
Anatolij Gustschin | f8853d1 | 2009-03-20 12:45:50 +0100 | [diff] [blame] | 794 | #if defined(CONFIG_440SPE) |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 795 | out32r( PCIL0_POM0LAL, 0x10000000 ); |
| 796 | out32r( PCIL0_POM0LAH, 0x0000000c ); |
Anatolij Gustschin | f8853d1 | 2009-03-20 12:45:50 +0100 | [diff] [blame] | 797 | #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 798 | out32r( PCIL0_POM0LAL, 0x20000000 ); |
| 799 | out32r( PCIL0_POM0LAH, 0x0000000c ); |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 800 | #else |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 801 | out32r( PCIL0_POM0LAL, 0x00000000 ); |
| 802 | out32r( PCIL0_POM0LAH, 0x00000003 ); |
Marian Balakowicz | 6c5879f | 2006-06-30 16:30:46 +0200 | [diff] [blame] | 803 | #endif |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 804 | out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); |
| 805 | out32r( PCIL0_POM0PCIAH, 0x00000000 ); |
| 806 | out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ |
| 807 | out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 ); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 808 | #endif |
| 809 | |
| 810 | /*--------------------------------------------------------------------------+ |
| 811 | * PCI host configuration -- we don't make any assumptions here ... the |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 812 | * _board_must_indicate_ what to do -- there's just too many runtime |
| 813 | * scenarios in environments like cPCI, PPMC, etc. to make a determination |
| 814 | * based on hard-coded values or state of arbiter enable. |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 815 | *--------------------------------------------------------------------------*/ |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 816 | if (is_pci_host(hose)) { |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 817 | #ifdef CONFIG_PCI_SCAN_SHOW |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 818 | printf("PCI: Bus Dev VenId DevId Class Int\n"); |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 819 | #endif |
Stefan Roese | 887e2ec | 2006-09-07 11:51:23 +0200 | [diff] [blame] | 820 | #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ |
| 821 | !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) |
Niklaus Giger | ddc922f | 2009-10-04 20:04:20 +0200 | [diff] [blame] | 822 | out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER); |
Stefan Roese | c157d8e | 2005-08-01 16:41:48 +0200 | [diff] [blame] | 823 | #endif |
Stefan Roese | 6e7fb6e | 2005-11-29 18:18:21 +0100 | [diff] [blame] | 824 | hose->last_busno = pci_hose_scan(hose); |
| 825 | } |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 826 | return hose->last_busno; |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 827 | } |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 828 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 829 | |
stroese | ad10dd9 | 2003-02-14 11:21:23 +0000 | [diff] [blame] | 830 | void pci_init_board(void) |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 831 | { |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 832 | int busno = 0; |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 833 | |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 834 | /* |
| 835 | * Only init PCI when either master or target functionality |
| 836 | * is selected. |
| 837 | */ |
| 838 | #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT) |
Wolfgang Denk | e5d5ed4 | 2011-10-29 09:38:31 +0000 | [diff] [blame] | 839 | busno = pci_440_init(&ppc440_hose); |
| 840 | if (busno < 0) |
| 841 | return; |
Stefan Roese | db64377 | 2010-05-21 15:06:19 +0200 | [diff] [blame] | 842 | #endif |
Dirk Eibach | 59d1bda | 2009-02-03 15:15:21 +0100 | [diff] [blame] | 843 | #if (defined(CONFIG_440SPE) || \ |
| 844 | defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ |
| 845 | !defined(CONFIG_PCI_DISABLE_PCIE) |
Grzegorz Bernacki | 7f19139 | 2007-09-07 18:20:23 +0200 | [diff] [blame] | 846 | pcie_setup_hoses(busno + 1); |
Rafal Jaworowski | 692519b | 2006-08-10 12:43:17 +0200 | [diff] [blame] | 847 | #endif |
wdenk | c609719 | 2002-11-03 00:24:07 +0000 | [diff] [blame] | 848 | } |
| 849 | |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 850 | #endif /* CONFIG_440 */ |
Stefan Roese | 1d7b874 | 2007-10-05 17:09:36 +0200 | [diff] [blame] | 851 | |
| 852 | #if defined(CONFIG_405EX) |
| 853 | void pci_init_board(void) |
| 854 | { |
| 855 | #ifdef CONFIG_PCI_SCAN_SHOW |
| 856 | printf("PCI: Bus Dev VenId DevId Class Int\n"); |
| 857 | #endif |
| 858 | pcie_setup_hoses(0); |
| 859 | } |
| 860 | #endif /* CONFIG_405EX */ |
| 861 | |
Matthias Fuchs | 5a1c9ff | 2007-06-24 17:23:41 +0200 | [diff] [blame] | 862 | #endif /* CONFIG_PCI */ |