stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 1 | /* |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 2 | * (C) Copyright 2001-2004 |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 3 | * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 8 | #ifndef __CONFIG_H |
| 9 | #define __CONFIG_H |
| 10 | |
| 11 | /* |
| 12 | * High Level Configuration Options |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #define CONFIG_405GP 1 /* This is a PPC405 CPU */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 16 | #define CONFIG_PMC405 1 /* ...on a PMC405 board */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 17 | |
Wolfgang Denk | 2ae1824 | 2010-10-06 09:05:45 +0200 | [diff] [blame] | 18 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
| 19 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 20 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ |
| 21 | #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 22 | |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 23 | #define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 24 | |
| 25 | #define CONFIG_BAUDRATE 9600 |
| 26 | #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ |
| 27 | |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 28 | /* Only interrupt boot if space is pressed. */ |
| 29 | #define CONFIG_AUTOBOOT_KEYED 1 |
| 30 | #define CONFIG_AUTOBOOT_PROMPT \ |
| 31 | "Press SPACE to abort autoboot in %d seconds\n", bootdelay |
| 32 | #undef CONFIG_AUTOBOOT_DELAY_STR |
| 33 | #define CONFIG_AUTOBOOT_STOP_STR " " |
| 34 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 35 | #undef CONFIG_BOOTARGS |
| 36 | #undef CONFIG_BOOTCOMMAND |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 37 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 38 | #define CONFIG_PREBOOT /* enable preboot variable */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 39 | |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 40 | #define CFG_BOOTM_LEN 0x1000000 /* support booting of huge images */ |
| 41 | |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 42 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 43 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 44 | |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 45 | #undef CONFIG_HAS_ETH1 |
| 46 | |
Ben Warren | 96e21f8 | 2008-10-27 23:50:15 -0700 | [diff] [blame] | 47 | #define CONFIG_PPC4xx_EMAC |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 48 | #define CONFIG_MII 1 /* MII PHY management */ |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 49 | #define CONFIG_PHY_ADDR 0 /* PHY address */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 50 | #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ |
| 51 | #define CONFIG_RESET_PHY_R 1 /* use reset_phy() */ |
Jon Loeliger | acf0269 | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 52 | |
| 53 | /* |
Jon Loeliger | a1aa0bb | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 54 | * BOOTP options |
| 55 | */ |
| 56 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 57 | #define CONFIG_BOOTP_BOOTPATH |
| 58 | #define CONFIG_BOOTP_GATEWAY |
| 59 | #define CONFIG_BOOTP_HOSTNAME |
| 60 | |
Jon Loeliger | a1aa0bb | 2007-07-10 09:22:23 -0500 | [diff] [blame] | 61 | /* |
Jon Loeliger | acf0269 | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 62 | * Command line configuration. |
| 63 | */ |
| 64 | #include <config_cmd_default.h> |
| 65 | |
| 66 | #define CONFIG_CMD_BSP |
| 67 | #define CONFIG_CMD_PCI |
| 68 | #define CONFIG_CMD_IRQ |
| 69 | #define CONFIG_CMD_ELF |
| 70 | #define CONFIG_CMD_DATE |
| 71 | #define CONFIG_CMD_JFFS2 |
| 72 | #define CONFIG_CMD_MII |
| 73 | #define CONFIG_CMD_I2C |
| 74 | #define CONFIG_CMD_PING |
| 75 | #define CONFIG_CMD_UNIVERSE |
| 76 | #define CONFIG_CMD_EEPROM |
| 77 | |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 78 | #define CONFIG_MAC_PARTITION |
| 79 | #define CONFIG_DOS_PARTITION |
| 80 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 81 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 82 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 83 | #define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible */ |
| 84 | #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 85 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 86 | #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 87 | |
| 88 | /* |
| 89 | * Miscellaneous configurable options |
| 90 | */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 91 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 92 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 93 | #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 94 | |
Jon Loeliger | acf0269 | 2007-07-08 14:49:44 -0500 | [diff] [blame] | 95 | #if defined(CONFIG_CMD_KGDB) |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 96 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 97 | #else |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 98 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 99 | #endif |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 100 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 101 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 102 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Sz */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 103 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 104 | #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 105 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 106 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console info */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 107 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 108 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 109 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 110 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
| 111 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 112 | |
Stefan Roese | 550650d | 2010-09-20 16:05:31 +0200 | [diff] [blame] | 113 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
| 114 | #define CONFIG_SYS_NS16550 |
| 115 | #define CONFIG_SYS_NS16550_SERIAL |
| 116 | #define CONFIG_SYS_NS16550_REG_SIZE 1 |
| 117 | #define CONFIG_SYS_NS16550_CLK get_serial_clock() |
| 118 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 119 | #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 120 | #define CONFIG_SYS_BASE_BAUD 806400 |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 121 | |
| 122 | /* The following table includes the supported baudrates */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 124 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 125 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 126 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 127 | #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 128 | |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 129 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 130 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 131 | |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 132 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 133 | |
wdenk | c837dcb | 2004-01-20 23:12:12 +0000 | [diff] [blame] | 134 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
stroese | 53cf943 | 2003-06-05 15:39:44 +0000 | [diff] [blame] | 135 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 136 | #define CONFIG_SYS_RX_ETH_BUFFER 16 |
stroese | 53cf943 | 2003-06-05 15:39:44 +0000 | [diff] [blame] | 137 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 138 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 139 | * PCI stuff |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 140 | */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 141 | #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ |
| 142 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 143 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 144 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 145 | #define CONFIG_PCI /* include pci support */ |
Gabor Juhos | 842033e | 2013-05-30 07:06:12 +0000 | [diff] [blame] | 146 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 147 | #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ |
| 148 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 149 | /* resource configuration */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 150 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 151 | #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 152 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 153 | #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config */ |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 154 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 155 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ |
| 156 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID */ |
| 157 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid() |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 159 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 160 | #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* Processor/PPC */ |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 161 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 162 | #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ |
| 163 | #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable */ |
| 164 | #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ |
| 165 | #define CONFIG_SYS_PCI_PTM2LA 0xef000000 /* point to internal regs */ |
| 166 | #define CONFIG_SYS_PCI_PTM2MS 0xff000001 /* 16MB, enable */ |
| 167 | #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ |
| 168 | |
Matthias Fuchs | 82379b5 | 2009-09-07 17:00:41 +0200 | [diff] [blame] | 169 | #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */ |
| 170 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 171 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 172 | * Start addresses for the final memory configuration |
| 173 | * (Set up by the startup code) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 174 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 175 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 176 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
Wolfgang Denk | 14d0a02 | 2010-10-07 21:51:12 +0200 | [diff] [blame] | 177 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| 178 | #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 179 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* 128 kB for malloc() */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 180 | |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 181 | #define CONFIG_PRAM 0 /* use pram variable to overwrite */ |
| 182 | |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 183 | /* |
| 184 | * For booting Linux, the board info and command line data |
| 185 | * have to be in the first 8 MB of memory, since this is |
| 186 | * the maximum mapped by the Linux kernel during initialization. |
| 187 | */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 188 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 189 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 190 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 191 | * FLASH organization |
| 192 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 193 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
| 194 | #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 195 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 196 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ |
| 197 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ |
| 198 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* don't use hardware protection */ |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 199 | #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST {{0xfff80000, 0x80000}} |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 200 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (faster) */ |
| 201 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */ |
| 202 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ |
| 203 | CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT} |
| 204 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
| 205 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on fli */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 206 | |
Wolfgang Denk | 700a0c6 | 2005-08-08 01:03:24 +0200 | [diff] [blame] | 207 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 208 | * Environment Variable setup |
| 209 | */ |
Jean-Christophe PLAGNIOL-VILLARD | bb1f8b4 | 2008-09-05 09:19:30 +0200 | [diff] [blame] | 210 | #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 211 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 212 | /* environment starts at the beginning of the EEPROM */ |
| 213 | #define CONFIG_ENV_OFFSET 0x000 |
| 214 | #define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 215 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 216 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */ |
| 217 | #define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */ |
| 218 | |
| 219 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 220 | * I2C EEPROM (CAT24WC16) for environment |
| 221 | */ |
Dirk Eibach | 880540d | 2013-04-25 02:40:01 +0000 | [diff] [blame] | 222 | #define CONFIG_SYS_I2C |
| 223 | #define CONFIG_SYS_I2C_PPC4XX |
| 224 | #define CONFIG_SYS_I2C_PPC4XX_CH0 |
| 225 | #define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 |
| 226 | #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 227 | |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 228 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24W16 */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 229 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ |
| 230 | /* mask of address bits that overflow into the "EEPROM chip address" */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 231 | #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 232 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24W16 has */ |
| 233 | /* 16 byte page write mode using*/ |
| 234 | /* last 4 bits of the address */ |
| 235 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 236 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 237 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 238 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 239 | * External Bus Controller (EBC) Setup |
| 240 | */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 241 | #define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */ |
| 242 | #define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */ |
| 243 | #define CAN_BA 0xF0000000 /* CAN Base Addres */ |
| 244 | #define RTC_BA 0xF0000500 /* RTC Base Address */ |
| 245 | #define NVRAM_BA 0xF0200000 /* NVRAM Base Address */ |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 246 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 247 | /* Memory Bank 0 (Flash Bank 0) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 248 | #define CONFIG_SYS_EBC_PB0AP 0x92015480 |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 249 | /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit */ |
| 250 | #define CONFIG_SYS_EBC_PB0CR (FLASH0_BA | 0x9A000) |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 251 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 252 | /* Memory Bank 1 (Flash Bank 1) initialization */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 253 | #define CONFIG_SYS_EBC_PB1AP 0x92015480 |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 254 | /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/ |
| 255 | #define CONFIG_SYS_EBC_PB1CR (FLASH1_BA | 0x9A000) |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 256 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 257 | /* Memory Bank 2 (CAN0, 1, RTC) initialization */ |
| 258 | /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ |
| 259 | #define CONFIG_SYS_EBC_PB2AP 0x03000440 |
| 260 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
| 261 | #define CONFIG_SYS_EBC_PB2CR (CAN_BA | 0x18000) |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 262 | |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 263 | /* Memory Bank 3 -> unused */ |
| 264 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 265 | /* Memory Bank 4 (NVRAM) initialization */ |
| 266 | /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */ |
| 267 | #define CONFIG_SYS_EBC_PB4AP 0x03000440 |
| 268 | /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ |
| 269 | #define CONFIG_SYS_EBC_PB4CR (NVRAM_BA | 0x18000) |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 270 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 271 | /* |
stroese | 2853d29 | 2003-09-12 08:53:54 +0000 | [diff] [blame] | 272 | * FPGA stuff |
| 273 | */ |
stroese | 2853d29 | 2003-09-12 08:53:54 +0000 | [diff] [blame] | 274 | /* FPGA program pin configuration */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 275 | #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (output) */ |
| 276 | #define CONFIG_SYS_FPGA_CLK 0x02000000 /* JTAG TCK pin (output) */ |
| 277 | #define CONFIG_SYS_FPGA_DATA 0x01000000 /* JTAG TDO pin (output) */ |
| 278 | #define CONFIG_SYS_FPGA_INIT 0x00010000 /* unused (ppc input) */ |
| 279 | #define CONFIG_SYS_FPGA_DONE 0x00008000 /* JTAG TDI pin (input) */ |
stroese | 2853d29 | 2003-09-12 08:53:54 +0000 | [diff] [blame] | 280 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 281 | /* pass Ethernet MAC to VxWorks */ |
| 282 | #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 |
stroese | a20b27a | 2004-12-16 18:05:42 +0000 | [diff] [blame] | 283 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 284 | /* |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 285 | * GPIOs |
| 286 | */ |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 287 | #define CONFIG_SYS_VPEN (0x80000000 >> 3) /* GPIO3 */ |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 288 | #define CONFIG_SYS_NONMONARCH (0x80000000 >> 14) /* GPIO14 */ |
| 289 | #define CONFIG_SYS_XEREADY (0x80000000 >> 15) /* GPIO15 */ |
| 290 | #define CONFIG_SYS_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */ |
| 291 | #define CONFIG_SYS_SELF_RST (0x80000000 >> 21) /* GPIO21 */ |
| 292 | #define CONFIG_SYS_REV1_2 (0x80000000 >> 23) /* GPIO23 */ |
Stefan Roese | 2076d0a | 2006-01-18 20:03:15 +0100 | [diff] [blame] | 293 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 294 | /* |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 295 | * Definitions for initial stack pointer and data area (in data cache) |
| 296 | */ |
| 297 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 298 | /* use on chip memory (OCM) for temperary stack until sdram is tested */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 299 | #define CONFIG_SYS_TEMP_STACK_OCM 1 |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 300 | |
| 301 | /* On Chip Memory location */ |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 302 | #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 |
| 303 | #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 304 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 305 | /* inside of SDRAM */ |
| 306 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR |
| 307 | |
| 308 | /* End of used area in RAM */ |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 309 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 310 | |
Wolfgang Denk | 553f098 | 2010-10-26 13:32:32 +0200 | [diff] [blame] | 311 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
Wolfgang Denk | 25ddd1f | 2010-10-26 14:34:52 +0200 | [diff] [blame] | 312 | GENERATED_GBL_DATA_SIZE) |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 313 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
stroese | 071d897 | 2003-05-23 11:35:47 +0000 | [diff] [blame] | 314 | |
Matthias Fuchs | 2f6eb91 | 2009-02-15 22:27:47 +0100 | [diff] [blame] | 315 | #define CONFIG_OF_LIBFDT |
| 316 | #define CONFIG_OF_BOARD_SETUP |
| 317 | |
Matthias Fuchs | c553b5f | 2009-02-15 22:26:54 +0100 | [diff] [blame] | 318 | #endif /* __CONFIG_H */ |