* The PS/2 mux on the BMS2003 board needs 450 ms after power on
before we can access it; add delay in case we are faster (with no
CF card inserted)
* Cleanup of some init functions
* Make sure SCC Ethernet is always stopped by the time we boot Linux
to avoid Linux crashes by early packets coming in.
* Accelerate flash accesses on LWMON board by using buffered writes
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 35d49fc..49414bb 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -34,13 +34,13 @@
*/
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_PMC405 1 /* ...on a PMC405 board */
+#define CONFIG_4xx 1 /* ...member of PPC4xx family */
+#define CONFIG_PMC405 1 /* ...on a PMC405 board */
-#define CONFIG_BOARD_PRE_INIT 1 /* call board_pre_init() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
#define CONFIG_BAUDRATE 9600
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
@@ -60,7 +60,7 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BSP | \
@@ -72,7 +72,7 @@
CFG_CMD_MII | \
CFG_CMD_I2C | \
CFG_CMD_PING | \
- CFG_CMD_EEPROM )
+ CFG_CMD_EEPROM )
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
@@ -80,12 +80,12 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
-#undef CONFIG_WATCHDOG /* watchdog disabled */
+#undef CONFIG_WATCHDOG /* watchdog disabled */
-#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
-#define CFG_RTC_REG_BASE_ADDR 0xF0000300 /* RTC Base Address */
+#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
+#define CFG_RTC_REG_BASE_ADDR 0xF0000300 /* RTC Base Address */
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
+#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
/*
* Miscellaneous configurable options
@@ -95,69 +95,69 @@
#undef CFG_HUSH_PARSER /* use "hush" command parser */
#ifdef CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_PROMPT_HUSH_PS2 "> "
#endif
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
-#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
+#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
-#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
+#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
-#define CFG_BASE_BAUD 691200
+#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
+#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
+#define CFG_BASE_BAUD 691200
/* The following table includes the supported baudrates */
-#define CFG_BAUDRATE_TABLE \
+#define CFG_BAUDRATE_TABLE \
{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
57600, 115200, 230400, 460800, 921600 }
#define CFG_LOAD_ADDR 0x100000 /* default load address */
#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
+#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
/*-----------------------------------------------------------------------
* PCI stuff
*-----------------------------------------------------------------------
*/
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
+#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
+#define PCI_HOST_FORCE 1 /* configure as pci host */
+#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
+#define CONFIG_PCI /* include pci support */
+#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
+#define CONFIG_PCI_PNP /* do pci plug-and-play */
+ /* resource configuration */
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
+#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
-#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
+#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
+#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
+#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
+#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
+#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
+#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
+#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
@@ -187,21 +187,21 @@
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_INCREMENT 0x01000000
-#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
+#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
+#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
/*-----------------------------------------------------------------------
* Environment Variable setup
*/
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
+#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
+#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CFG_NVRAM_SIZE 242 /* NVRAM size */
+#define CFG_NVRAM_SIZE 242 /* NVRAM size */
/*-----------------------------------------------------------------------
* I2C EEPROM (CAT24WC16) for environment
@@ -211,20 +211,20 @@
#define CFG_I2C_SLAVE 0x7F
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
+#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
+/* mask of address bits that overflow into the "EEPROM chip address" */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
/* 16 byte page write mode using*/
- /* last 4 bits of the address */
+ /* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
#define CFG_EEPROM_PAGE_WRITE_ENABLE
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
+#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
+ /* have only 8kB, 16kB is save here */
#define CFG_CACHELINE_SIZE 32 /* ... */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
@@ -233,47 +233,47 @@
/*-----------------------------------------------------------------------
* External Bus Controller (EBC) Setup
*/
-#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
-#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
-#define CAN_BA 0xF0000000 /* CAN Base Address */
-#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define CF_BA 0xF0100000 /* CompactFlash Base Address */
+#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
+#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
+#define CAN_BA 0xF0000000 /* CAN Base Address */
+#define RTC_BA 0xF0000500 /* RTC Base Address */
+#define CF_BA 0xF0100000 /* CompactFlash Base Address */
-/* Memory Bank 0 (Flash Bank 0) initialization */
-#define CFG_EBC_PB0AP 0x92015480
-#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
+/* Memory Bank 0 (Flash Bank 0) initialization */
+#define CFG_EBC_PB0AP 0x92015480
+#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
-/* Memory Bank 1 (Flash Bank 1) initialization */
-#define CFG_EBC_PB1AP 0x92015480
-#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
+/* Memory Bank 1 (Flash Bank 1) initialization */
+#define CFG_EBC_PB1AP 0x92015480
+#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
-/* Memory Bank 2 (CAN0, 1, RTC) initialization */
-#define CFG_EBC_PB2AP 0x03000040 /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0 */
-#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
+/* Memory Bank 2 (CAN0, 1, RTC) initialization */
+#define CFG_EBC_PB2AP 0x03000040 /* TWT=6,TH=0,CSN=0,OEN=0,WBN=0,WBF=0 */
+#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
-#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
+#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
+#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
/*-----------------------------------------------------------------------
* FPGA stuff
*/
-#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
-#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
+#define CFG_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */
+#define CFG_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */
/* FPGA program pin configuration */
-#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
-#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
-#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
-#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
-#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
+#define CFG_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */
+#define CFG_FPGA_CLK 0x02000000 /* JTAG TCK pin (ppc output) */
+#define CFG_FPGA_DATA 0x01000000 /* JTAG TDO->TDI data pin (ppc output) */
+#define CFG_FPGA_INIT 0x00010000 /* unused (ppc input) */
+#define CFG_FPGA_DONE 0x00008000 /* JTAG TDI->TDO pin (ppc input) */
/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CFG_TEMP_STACK_OCM 1
+#define CFG_TEMP_STACK_OCM 1
/* On Chip Memory location */
#define CFG_OCM_DATA_ADDR 0xF8000000
@@ -283,7 +283,7 @@
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*
* Internal Definitions