blob: 9181d59a947f2643ca51cafdf11c7c464fef03a2 [file] [log] [blame]
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +09001/*
Yusuke Godab55523e2008-03-05 14:23:26 +09002 * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +09003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +09005 */
6
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +09007#ifndef _ASM_CPU_SH4_H_
8#define _ASM_CPU_SH4_H_
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +09009
10/* cache control */
11#define CCR_CACHE_STOP 0x00000808
12#define CCR_CACHE_ENABLE 0x00000101
13#define CCR_CACHE_ICI 0x00000800
14
15#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
Nobuhiro Iwamatsuc54b9a42008-11-25 11:05:19 +090016
17#if defined (CONFIG_CPU_SH7750) || \
18 defined(CONFIG_CPU_SH7751)
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +090019#define CACHE_OC_WAY_SHIFT 14
20#define CACHE_OC_NUM_ENTRIES 512
Nobuhiro Iwamatsuc54b9a42008-11-25 11:05:19 +090021#else
22#define CACHE_OC_WAY_SHIFT 13
23#define CACHE_OC_NUM_ENTRIES 256
24#endif
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +090025#define CACHE_OC_ENTRY_SHIFT 5
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +090026
Nobuhiro Iwamatsu56693322008-03-12 12:10:28 +090027#if defined (CONFIG_CPU_SH7750) || \
28 defined(CONFIG_CPU_SH7751)
29# include <asm/cpu_sh7750.h>
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +090030#elif defined (CONFIG_CPU_SH7722)
Nobuhiro Iwamatsu56693322008-03-12 12:10:28 +090031# include <asm/cpu_sh7722.h>
Nobuhiro Iwamatsuab09f432008-08-22 17:48:51 +090032#elif defined (CONFIG_CPU_SH7723)
33# include <asm/cpu_sh7723.h>
Nobuhiro Iwamatsubead86a2011-11-15 11:00:01 +090034#elif defined (CONFIG_CPU_SH7724)
35# include <asm/cpu_sh7724.h>
Nobuhiro Iwamatsu2a57e7e2012-01-11 10:45:01 +090036#elif defined (CONFIG_CPU_SH7734)
37# include <asm/cpu_sh7734.h>
Yoshihiro Shimoda1a2621b2012-11-04 15:53:22 +000038#elif defined (CONFIG_CPU_SH7752)
39# include <asm/cpu_sh7752.h>
Yoshihiro Shimoda8e9c8972011-02-02 10:05:36 +090040#elif defined (CONFIG_CPU_SH7757)
41# include <asm/cpu_sh7757.h>
Nobuhiro Iwamatsu60179092008-06-06 16:24:13 +090042#elif defined (CONFIG_CPU_SH7763)
43# include <asm/cpu_sh7763.h>
Yusuke Godab55523e2008-03-05 14:23:26 +090044#elif defined (CONFIG_CPU_SH7780)
Nobuhiro Iwamatsu56693322008-03-12 12:10:28 +090045# include <asm/cpu_sh7780.h>
Yoshihiro Shimodab0b62182008-07-10 19:32:53 +090046#elif defined (CONFIG_CPU_SH7785)
47# include <asm/cpu_sh7785.h>
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090048#else
Nobuhiro Iwamatsu56693322008-03-12 12:10:28 +090049# error "Unknown SH4 variant"
Nobuhiro Iwamatsu0b135cf2007-05-13 20:58:00 +090050#endif
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +090051
Yoshihiro Shimoda6d84ae32009-03-03 15:11:08 +090052#if defined(CONFIG_SH_32BIT)
53#define PMB_ADDR_ARRAY 0xf6100000
54#define PMB_ADDR_ENTRY 8
55#define PMB_VPN 24
56
57#define PMB_DATA_ARRAY 0xf7100000
58#define PMB_DATA_ENTRY 8
59#define PMB_PPN 24
60#define PMB_UB 9 /* Buffered write */
61#define PMB_V 8 /* Valid */
62#define PMB_SZ1 7 /* Page size (upper bit) */
63#define PMB_SZ0 4 /* Page size (lower bit) */
64#define PMB_C 3 /* Cacheability */
65#define PMB_WT 0 /* Write-through */
66
67#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
68#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
69#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
70#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
71 ((ppn << PMB_PPN) | (ub << PMB_UB) | \
72 (v << PMB_V) | (sz1 << PMB_SZ1) | \
73 (sz0 << PMB_SZ0) | (c << PMB_C) | \
74 (wt << PMB_WT))
75#endif
76
Nobuhiro Iwamatsub02bad12007-09-23 02:12:30 +090077#endif /* _ASM_CPU_SH4_H_ */