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Ilko Iliev32949232009-06-12 21:20:39 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Ilko Iliev32949232009-06-12 21:20:39 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 * Ilko Iliev <www.ronetix.at>
6 *
7 * Configuation settings for the RONETIX PM9261 board.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Ilko Iliev32949232009-06-12 21:20:39 +020010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
Asen Dimovf47316a2011-07-26 04:48:41 +000015/*
16 * SoC must be defined first, before hardware.h is included.
17 * In this case SoC is defined in boards.cfg.
18 */
19
20#include <asm/hardware.h>
Ilko Iliev32949232009-06-12 21:20:39 +020021/* ARM asynchronous clock */
Ilko Iliev32949232009-06-12 21:20:39 +020022
Ilko Iliev32949232009-06-12 21:20:39 +020023#define MASTER_PLL_DIV 15
24#define MASTER_PLL_MUL 162
25#define MAIN_PLL_DIV 2
Asen Dimovf47316a2011-07-26 04:48:41 +000026#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Achim Ehrlich7c966a82010-02-24 10:29:16 +010027#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000
Ilko Iliev32949232009-06-12 21:20:39 +020028
Asen Dimovf47316a2011-07-26 04:48:41 +000029#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261"
Ilko Iliev32949232009-06-12 21:20:39 +020030#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */
31#define CONFIG_ARCH_CPU_INIT
Asen Dimov4f81bf42010-12-12 12:41:30 +020032#define CONFIG_SYS_TEXT_BASE 0
Ilko Iliev32949232009-06-12 21:20:39 +020033
Asen Dimova3e09cc2011-10-31 08:54:20 +000034#define CONFIG_MACH_TYPE MACH_TYPE_PM9261
35
Ilko Iliev32949232009-06-12 21:20:39 +020036/* clocks */
37/* CKGR_MOR - enable main osc. */
38#define CONFIG_SYS_MOR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030039 (AT91_PMC_MOR_MOSCEN | \
Ilko Iliev32949232009-06-12 21:20:39 +020040 (255 << 8)) /* Main Oscillator Start-up Time */
41#define CONFIG_SYS_PLLAR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030042 (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \
43 AT91_PMC_PLLXR_OUT(3) | \
Ilko Iliev32949232009-06-12 21:20:39 +020044 ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV))
45
46/* PCK/2 = MCK Master Clock from PLLA */
47#define CONFIG_SYS_MCKR1_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030048 (AT91_PMC_MCKR_CSS_SLOW | \
49 AT91_PMC_MCKR_PRES_1 | \
Bo Shen7ac2e7c2013-11-15 11:12:33 +080050 AT91_PMC_MCKR_MDIV_2)
Ilko Iliev32949232009-06-12 21:20:39 +020051
52/* PCK/2 = MCK Master Clock from PLLA */
53#define CONFIG_SYS_MCKR2_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030054 (AT91_PMC_MCKR_CSS_PLLA | \
55 AT91_PMC_MCKR_PRES_1 | \
Bo Shen7ac2e7c2013-11-15 11:12:33 +080056 AT91_PMC_MCKR_MDIV_2)
Ilko Iliev32949232009-06-12 21:20:39 +020057
58/* define PDC[31:16] as DATA[31:16] */
59#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000
60/* no pull-up for D[31:16] */
61#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000
62
63/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */
64#define CONFIG_SYS_MATRIX_EBICSA_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +030065 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A)
Ilko Iliev32949232009-06-12 21:20:39 +020066
67/* SDRAM */
68/* SDRAMC_MR Mode register */
69#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL
70/* SDRAMC_TR - Refresh Timer register */
71#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
72/* SDRAMC_CR - Configuration register*/
73#define CONFIG_SYS_SDRC_CR_VAL \
74 (AT91_SDRAMC_NC_9 | \
75 AT91_SDRAMC_NR_13 | \
76 AT91_SDRAMC_NB_4 | \
77 AT91_SDRAMC_CAS_3 | \
78 AT91_SDRAMC_DBW_32 | \
79 (1 << 8) | /* Write Recovery Delay */ \
80 (7 << 12) | /* Row Cycle Delay */ \
81 (3 << 16) | /* Row Precharge Delay */ \
82 (2 << 20) | /* Row to Column Delay */ \
83 (5 << 24) | /* Active to Precharge Delay */ \
84 (1 << 28)) /* Exit Self Refresh to Active Delay */
85
86/* Memory Device Register -> SDRAM */
87#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
88#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
89#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
90#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
91#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
92#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
93#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
94#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
95#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
96#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
97#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
98#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
99#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
100#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
101#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
102#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
103#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
104#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
105
106/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
107#define CONFIG_SYS_SMC0_SETUP0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300108 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
109 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
Ilko Iliev32949232009-06-12 21:20:39 +0200110#define CONFIG_SYS_SMC0_PULSE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300111 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
112 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Ilko Iliev32949232009-06-12 21:20:39 +0200113#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300114 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Ilko Iliev32949232009-06-12 21:20:39 +0200115#define CONFIG_SYS_SMC0_MODE0_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300116 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
117 AT91_SMC_MODE_DBW_16 | \
118 AT91_SMC_MODE_TDF | \
119 AT91_SMC_MODE_TDF_CYCLE(6))
Ilko Iliev32949232009-06-12 21:20:39 +0200120
121/* user reset enable */
122#define CONFIG_SYS_RSTC_RMR_VAL \
123 (AT91_RSTC_KEY | \
Asen Dimove3150c72010-04-06 16:18:04 +0300124 AT91_RSTC_CR_PROCRST | \
125 AT91_RSTC_MR_ERSTL(1) | \
126 AT91_RSTC_MR_ERSTL(2))
Ilko Iliev32949232009-06-12 21:20:39 +0200127
128/* Disable Watchdog */
129#define CONFIG_SYS_WDTC_WDMR_VAL \
Asen Dimove3150c72010-04-06 16:18:04 +0300130 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
131 AT91_WDT_MR_WDV(0xfff) | \
132 AT91_WDT_MR_WDDIS | \
133 AT91_WDT_MR_WDD(0xfff))
Ilko Iliev32949232009-06-12 21:20:39 +0200134
135#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
136#define CONFIG_SETUP_MEMORY_TAGS 1
137#define CONFIG_INITRD_TAG 1
138
139#undef CONFIG_SKIP_LOWLEVEL_INIT
Ilko Iliev32949232009-06-12 21:20:39 +0200140
141/*
142 * Hardware drivers
143 */
Ilko Iliev32949232009-06-12 21:20:39 +0200144
145/* LCD */
Ilko Iliev32949232009-06-12 21:20:39 +0200146#define LCD_BPP LCD_COLOR8
147#define CONFIG_LCD_LOGO 1
148#undef LCD_TEST_PATTERN
149#define CONFIG_LCD_INFO 1
150#define CONFIG_LCD_INFO_BELOW_LOGO 1
Ilko Iliev32949232009-06-12 21:20:39 +0200151#define CONFIG_ATMEL_LCD 1
152#define CONFIG_ATMEL_LCD_BGR555 1
Ilko Iliev32949232009-06-12 21:20:39 +0200153
Ilko Iliev32949232009-06-12 21:20:39 +0200154/*
155 * BOOTP options
156 */
157#define CONFIG_BOOTP_BOOTFILESIZE 1
158#define CONFIG_BOOTP_BOOTPATH 1
159#define CONFIG_BOOTP_GATEWAY 1
160#define CONFIG_BOOTP_HOSTNAME 1
161
Ilko Iliev32949232009-06-12 21:20:39 +0200162/* SDRAM */
163#define CONFIG_NR_DRAM_BANKS 1
164#define PHYS_SDRAM 0x20000000
165#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
166
Ilko Iliev32949232009-06-12 21:20:39 +0200167/* NAND flash */
168#define CONFIG_NAND_ATMEL
Ilko Iliev32949232009-06-12 21:20:39 +0200169#define CONFIG_SYS_MAX_NAND_DEVICE 1
170#define CONFIG_SYS_NAND_BASE 0x40000000
171#define CONFIG_SYS_NAND_DBW_8 1
172/* our ALE is AD22 */
173#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
174/* our CLE is AD21 */
175#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
Andreas Bießmannac45bb12013-11-29 12:13:45 +0100176#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
177#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
Ilko Iliev32949232009-06-12 21:20:39 +0200178
Ilko Iliev32949232009-06-12 21:20:39 +0200179/* NOR flash */
180#define CONFIG_SYS_FLASH_CFI 1
181#define CONFIG_FLASH_CFI_DRIVER 1
182#define PHYS_FLASH_1 0x10000000
183#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
184#define CONFIG_SYS_MAX_FLASH_SECT 256
185#define CONFIG_SYS_MAX_FLASH_BANKS 1
186
187/* Ethernet */
188#define CONFIG_DRIVER_DM9000 1
189#define CONFIG_DM9000_BASE 0x30000000
190#define DM9000_IO CONFIG_DM9000_BASE
191#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
192#define CONFIG_DM9000_USE_16BIT 1
193#define CONFIG_NET_RETRY_COUNT 20
194#define CONFIG_RESET_PHY_R 1
Ilko Iliev32949232009-06-12 21:20:39 +0200195
196/* USB */
197#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800198#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ilko Iliev32949232009-06-12 21:20:39 +0200199#define CONFIG_USB_OHCI_NEW 1
Ilko Iliev32949232009-06-12 21:20:39 +0200200#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
201#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
202#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
203#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Ilko Iliev32949232009-06-12 21:20:39 +0200204
205#define CONFIG_SYS_LOAD_ADDR 0x22000000
206
207#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
208#define CONFIG_SYS_MEMTEST_END 0x23e00000
209
210#undef CONFIG_SYS_USE_DATAFLASH_CS0
211#undef CONFIG_SYS_USE_NANDFLASH
212#define CONFIG_SYS_USE_FLASH 1
213
214#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
215
216/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Ilko Iliev32949232009-06-12 21:20:39 +0200217#define CONFIG_ENV_OFFSET 0x4200
Ilko Iliev32949232009-06-12 21:20:39 +0200218#define CONFIG_ENV_SIZE 0x4200
Wenyou.Yang@microchip.comc53a8252017-07-21 17:04:56 +0800219#define CONFIG_ENV_SECT_SIZE 0x210
220#define CONFIG_ENV_SPI_MAX_HZ 15000000
221#define CONFIG_BOOTCOMMAND "sf probe 0; " \
222 "sf read 0x22000000 0x84000 0x210000; " \
223 "bootm 0x22000000"
Ilko Iliev32949232009-06-12 21:20:39 +0200224
225#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */
226
227/* bootstrap + u-boot + env + linux in nandflash */
Ilko Iliev32949232009-06-12 21:20:39 +0200228#define CONFIG_ENV_OFFSET 0x60000
229#define CONFIG_ENV_OFFSET_REDUND 0x80000
230#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
231#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
Ilko Iliev32949232009-06-12 21:20:39 +0200232
233#elif defined (CONFIG_SYS_USE_FLASH)
234
Ilko Iliev32949232009-06-12 21:20:39 +0200235#define CONFIG_ENV_OFFSET 0x40000
236#define CONFIG_ENV_SECT_SIZE 0x10000
237#define CONFIG_ENV_SIZE 0x10000
238#define CONFIG_ENV_OVERWRITE 1
239
240/* JFFS Partition offset set */
241#define CONFIG_SYS_JFFS2_FIRST_BANK 0
242#define CONFIG_SYS_JFFS2_NUM_BANKS 1
243
244/* 512k reserved for u-boot */
245#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11
246
247#define CONFIG_BOOTCOMMAND "run flashboot"
248
249#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand"
250#define MTDPARTS_DEFAULT \
251 "mtdparts=physmap-flash.0:" \
252 "256k(u-boot)ro," \
253 "64k(u-boot-env)ro," \
254 "1408k(kernel)," \
255 "-(rootfs);" \
256 "nand:-(nand)"
257
258#define CONFIG_CON_ROT "fbcon=rotate:3 "
Ilko Iliev32949232009-06-12 21:20:39 +0200259
260#define CONFIG_EXTRA_ENV_SETTINGS \
261 "mtdids=" MTDIDS_DEFAULT "\0" \
262 "mtdparts=" MTDPARTS_DEFAULT "\0" \
263 "partition=nand0,0\0" \
264 "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \
265 "nfsargs=setenv bootargs root=/dev/nfs rw " \
266 CONFIG_CON_ROT \
267 "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \
268 "addip=setenv bootargs $(bootargs) " \
269 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\
270 ":$(hostname):eth0:off\0" \
271 "ramboot=tftpboot 0x22000000 vmImage;" \
272 "run ramargs;run addip;bootm 22000000\0" \
273 "nfsboot=tftpboot 0x22000000 vmImage;" \
274 "run nfsargs;run addip;bootm 22000000\0" \
275 "flashboot=run ramargs;run addip;bootm 0x10050000\0" \
276 ""
277#else
278#error "Undefined memory device"
279#endif
280
Ilko Iliev32949232009-06-12 21:20:39 +0200281#define CONFIG_SYS_CBSIZE 256
282#define CONFIG_SYS_MAXARGS 16
283#define CONFIG_SYS_PBSIZE \
284 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
285#define CONFIG_SYS_LONGHELP 1
286#define CONFIG_CMDLINE_EDITING 1
287
Ilko Iliev32949232009-06-12 21:20:39 +0200288/*
289 * Size of malloc() pool
290 */
291#define CONFIG_SYS_MALLOC_LEN \
292 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
Ilko Iliev32949232009-06-12 21:20:39 +0200293
Asen Dimov4f81bf42010-12-12 12:41:30 +0200294#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
Wenyou.Yang@microchip.comc53a8252017-07-21 17:04:56 +0800295#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \
Asen Dimov4f81bf42010-12-12 12:41:30 +0200296 GENERATED_GBL_DATA_SIZE)
297
Ilko Iliev32949232009-06-12 21:20:39 +0200298#endif