blob: a4128cbd11255bb1be83bd6e5c248d11f0d063e0 [file] [log] [blame]
Scott Wood96b8a052007-04-16 14:54:15 -05001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 *
4 * Authors: Nick.Spence@freescale.com
5 * Wilson.Lo@freescale.com
6 * scottwood@freescale.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Scott Wood96b8a052007-04-16 14:54:15 -05009 */
10
11#include <common.h>
12#include <mpc83xx.h>
13#include <spd_sdram.h>
14
15#include <asm/bitops.h>
16#include <asm/io.h>
17
18#include <asm/processor.h>
19
Wolfgang Denk1218abf2007-09-15 20:48:41 +020020DECLARE_GLOBAL_DATA_PTR;
21
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -050023static void resume_from_sleep(void)
24{
Scott Wood96b8a052007-04-16 14:54:15 -050025 u32 magic = *(u32 *)0;
26
27 typedef void (*func_t)(void);
28 func_t resume = *(func_t *)4;
29
30 if (magic == 0xf5153ae5)
31 resume();
32
33 gd->flags &= ~GD_FLG_SILENT;
34 puts("\nResume from sleep failed: bad magic word\n");
35}
36#endif
37
38/* Fixed sdram init -- doesn't use serial presence detect.
39 *
40 * This is useful for faster booting in configs where the RAM is unlikely
41 * to be changed, or for things like NAND booting where space is tight.
42 */
43static long fixed_sdram(void)
44{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
Scott Woode4c09502008-06-30 14:13:28 -050046
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#ifndef CONFIG_SYS_RAMBOOT
48 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Scott Wood96b8a052007-04-16 14:54:15 -050049 u32 msize_log2 = __ilog2(msize);
50
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Scott Wood96b8a052007-04-16 14:54:15 -050052 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Scott Wood96b8a052007-04-16 14:54:15 -050054
55 /*
56 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
57 * or the DDR2 controller may fail to initialize correctly.
58 */
Ingo van Lil3eb90ba2009-11-24 14:09:21 +010059 __udelay(50000);
Scott Wood96b8a052007-04-16 14:54:15 -050060
Joe Hershberger2e651b22011-10-11 23:57:31 -050061#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
62#warning Chip select bounds is only configurable in 16MB increments
63#endif
64 im->ddr.csbnds[0].csbnds =
65 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
66 (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
67 CSBNDS_EA);
68 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
Scott Wood96b8a052007-04-16 14:54:15 -050069
70 /* Currently we use only one CS, so disable the other bank. */
71 im->ddr.cs_config[1] = 0;
72
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
74 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
75 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
76 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
77 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
Scott Wood96b8a052007-04-16 14:54:15 -050078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -050080 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
Scott Wood96b8a052007-04-16 14:54:15 -050082 else
83#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
Scott Wood96b8a052007-04-16 14:54:15 -050085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
87 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
88 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
Scott Wood96b8a052007-04-16 14:54:15 -050089
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Scott Wood96b8a052007-04-16 14:54:15 -050091 sync();
92
93 /* enable DDR controller */
94 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
Scott Woode4c09502008-06-30 14:13:28 -050095#endif
Scott Wood96b8a052007-04-16 14:54:15 -050096
97 return msize;
98}
99
Simon Glassf1683aa2017-04-06 12:47:05 -0600100int dram_init(void)
Scott Wood96b8a052007-04-16 14:54:15 -0500101{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500103 volatile fsl_lbc_t *lbc = &im->im_lbc;
Scott Wood96b8a052007-04-16 14:54:15 -0500104 u32 msize;
105
106 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
Simon Glass088454c2017-03-31 08:40:25 -0600107 return -ENXIO;
Scott Wood96b8a052007-04-16 14:54:15 -0500108
Scott Wood96b8a052007-04-16 14:54:15 -0500109 /* DDR SDRAM - Main SODIMM */
110 msize = fixed_sdram();
111
112 /* Local Bus setup lbcr and mrtpr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
114 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Scott Wood96b8a052007-04-16 14:54:15 -0500115 sync();
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -0500118 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
119 resume_from_sleep();
120#endif
121
Scott Wood96b8a052007-04-16 14:54:15 -0500122 /* return total bus SDRAM size(bytes) -- DDR */
Simon Glass088454c2017-03-31 08:40:25 -0600123 gd->ram_size = msize;
124
125 return 0;
Scott Wood96b8a052007-04-16 14:54:15 -0500126}