blob: 7aede136d6e236c5bdd4ceaccda3ca58598b4abc [file] [log] [blame]
Scott Wood96b8a052007-04-16 14:54:15 -05001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 *
4 * Authors: Nick.Spence@freescale.com
5 * Wilson.Lo@freescale.com
6 * scottwood@freescale.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc83xx.h>
29#include <spd_sdram.h>
30
31#include <asm/bitops.h>
32#include <asm/io.h>
33
34#include <asm/processor.h>
35
Wolfgang Denk1218abf2007-09-15 20:48:41 +020036DECLARE_GLOBAL_DATA_PTR;
37
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020038#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -050039static void resume_from_sleep(void)
40{
Scott Wood96b8a052007-04-16 14:54:15 -050041 u32 magic = *(u32 *)0;
42
43 typedef void (*func_t)(void);
44 func_t resume = *(func_t *)4;
45
46 if (magic == 0xf5153ae5)
47 resume();
48
49 gd->flags &= ~GD_FLG_SILENT;
50 puts("\nResume from sleep failed: bad magic word\n");
51}
52#endif
53
54/* Fixed sdram init -- doesn't use serial presence detect.
55 *
56 * This is useful for faster booting in configs where the RAM is unlikely
57 * to be changed, or for things like NAND booting where space is tight.
58 */
59static long fixed_sdram(void)
60{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
Scott Woode4c09502008-06-30 14:13:28 -050062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#ifndef CONFIG_SYS_RAMBOOT
64 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Scott Wood96b8a052007-04-16 14:54:15 -050065 u32 msize_log2 = __ilog2(msize);
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Scott Wood96b8a052007-04-16 14:54:15 -050068 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Scott Wood96b8a052007-04-16 14:54:15 -050070
71 /*
72 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
73 * or the DDR2 controller may fail to initialize correctly.
74 */
Ingo van Lil3eb90ba2009-11-24 14:09:21 +010075 __udelay(50000);
Scott Wood96b8a052007-04-16 14:54:15 -050076
77 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
Scott Wood96b8a052007-04-16 14:54:15 -050079
80 /* Currently we use only one CS, so disable the other bank. */
81 im->ddr.cs_config[1] = 0;
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
84 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
85 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
86 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
87 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
Scott Wood96b8a052007-04-16 14:54:15 -050088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -050090 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
Scott Wood96b8a052007-04-16 14:54:15 -050092 else
93#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
Scott Wood96b8a052007-04-16 14:54:15 -050095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
97 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
98 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
Scott Wood96b8a052007-04-16 14:54:15 -050099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Scott Wood96b8a052007-04-16 14:54:15 -0500101 sync();
102
103 /* enable DDR controller */
104 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
Scott Woode4c09502008-06-30 14:13:28 -0500105#endif
Scott Wood96b8a052007-04-16 14:54:15 -0500106
107 return msize;
108}
109
Becky Bruce9973e3c2008-06-09 16:03:40 -0500110phys_size_t initdram(int board_type)
Scott Wood96b8a052007-04-16 14:54:15 -0500111{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500113 volatile fsl_lbc_t *lbc = &im->im_lbc;
Scott Wood96b8a052007-04-16 14:54:15 -0500114 u32 msize;
115
116 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
117 return -1;
118
Scott Wood96b8a052007-04-16 14:54:15 -0500119 /* DDR SDRAM - Main SODIMM */
120 msize = fixed_sdram();
121
122 /* Local Bus setup lbcr and mrtpr */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
124 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Scott Wood96b8a052007-04-16 14:54:15 -0500125 sync();
126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -0500128 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
129 resume_from_sleep();
130#endif
131
Scott Wood96b8a052007-04-16 14:54:15 -0500132 /* return total bus SDRAM size(bytes) -- DDR */
133 return msize;
134}