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Michal Simek18a952c2018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simek08ac3862016-05-26 08:06:38 +02002/*
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 *
Michal Simek18a952c2018-03-27 10:36:39 +02005 * (C) Copyright 2015 - 2018, Xilinx, Inc.
Michal Simek08ac3862016-05-26 08:06:38 +02006 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simek08ac3862016-05-26 08:06:38 +02008 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
Michal Simekee4983f2017-12-08 14:50:42 +010013#include "zynqmp-clk-ccf.dtsi"
Michal Simek08ac3862016-05-26 08:06:38 +020014
15/ {
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18
19 aliases {
20 can0 = &can0;
21 can1 = &can1;
22 ethernet0 = &gem0;
23 ethernet1 = &gem1;
24 ethernet2 = &gem2;
25 ethernet3 = &gem3;
26 gpio0 = &gpio;
27 i2c0 = &i2c0;
28 i2c1 = &i2c1;
29 rtc0 = &rtc;
30 serial0 = &uart0;
31 serial1 = &uart1;
32 spi0 = &qspi;
33 };
34
35 chosen {
36 bootargs = "earlycon";
37 stdout-path = "serial0:115200n8";
38 };
39
Michal Simekc926e6f2016-11-11 13:21:04 +010040 memory@0 {
Michal Simek08ac3862016-05-26 08:06:38 +020041 device_type = "memory";
42 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
43 };
44};
45
46&can0 {
47 status = "okay";
48};
49
50&can1 {
51 status = "okay";
52};
53
Michal Simek08ac3862016-05-26 08:06:38 +020054&fpd_dma_chan1 {
55 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +020056};
57
58&fpd_dma_chan2 {
59 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +020060};
61
62&fpd_dma_chan3 {
63 status = "okay";
64};
65
66&fpd_dma_chan4 {
67 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +020068};
69
70&fpd_dma_chan5 {
71 status = "okay";
72};
73
74&fpd_dma_chan6 {
75 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +020076};
77
78&fpd_dma_chan7 {
79 status = "okay";
80};
81
82&fpd_dma_chan8 {
83 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +020084};
85
86&lpd_dma_chan1 {
87 status = "okay";
88};
89
90&lpd_dma_chan2 {
91 status = "okay";
92};
93
94&lpd_dma_chan3 {
95 status = "okay";
96};
97
98&lpd_dma_chan4 {
99 status = "okay";
100};
101
102&lpd_dma_chan5 {
103 status = "okay";
104};
105
106&lpd_dma_chan6 {
107 status = "okay";
108};
109
110&lpd_dma_chan7 {
111 status = "okay";
112};
113
114&lpd_dma_chan8 {
115 status = "okay";
116};
117
118&xlnx_dp {
119 status = "okay";
120};
121
122&xlnx_dpdma {
123 status = "okay";
124};
125
126&gem0 {
127 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200128 phy-mode = "rgmii-id";
129 phy-handle = <&ethernet_phy0>;
130 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
131 reg = <0>;
132 };
133 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
134 reg = <7>;
135 };
136 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
137 reg = <3>;
138 };
139 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
140 reg = <8>;
141 };
142};
143
144&gem1 {
145 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200146 phy-mode = "rgmii-id";
147 phy-handle = <&ethernet_phy7>;
148};
149
150&gem2 {
151 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200152 phy-mode = "rgmii-id";
153 phy-handle = <&ethernet_phy3>;
154};
155
156&gem3 {
157 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200158 phy-mode = "rgmii-id";
159 phy-handle = <&ethernet_phy8>;
160};
161
162&gpio {
163 status = "okay";
164};
165
166&gpu {
167 status = "okay";
168};
169
170&i2c0 {
171 clock-frequency = <400000>;
172 status = "okay";
173};
174
175&i2c1 {
176 clock-frequency = <400000>;
177 status = "okay";
178};
179
Siva Durga Prasad Paladugu9cd26aa2017-03-04 12:16:47 +0530180&qspi {
181 status = "okay";
182 flash@0 {
Neil Armstrongffd4c7c2019-02-10 10:16:20 +0000183 compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
Siva Durga Prasad Paladugu9cd26aa2017-03-04 12:16:47 +0530184 #address-cells = <1>;
185 #size-cells = <1>;
186 reg = <0x0>;
187 spi-tx-bus-width = <1>;
188 spi-rx-bus-width = <4>; /* also DUAL configuration possible */
189 spi-max-frequency = <108000000>; /* Based on DC1 spec */
190 partition@qspi-fsbl-uboot { /* for testing purpose */
191 label = "qspi-fsbl-uboot";
192 reg = <0x0 0x100000>;
193 };
194 partition@qspi-linux { /* for testing purpose */
195 label = "qspi-linux";
196 reg = <0x100000 0x500000>;
197 };
198 partition@qspi-device-tree { /* for testing purpose */
199 label = "qspi-device-tree";
200 reg = <0x600000 0x20000>;
201 };
202 partition@qspi-rootfs { /* for testing purpose */
203 label = "qspi-rootfs";
204 reg = <0x620000 0x5E0000>;
205 };
206 };
207};
208
Michal Simek08ac3862016-05-26 08:06:38 +0200209&rtc {
210 status = "okay";
211};
212
213&uart0 {
214 status = "okay";
215};
216
217&uart1 {
218 status = "okay";
219};
220
221&watchdog0 {
222 status = "okay";
223};