blob: 3a9e7807c6904bfdb90743c3018a158a9f3cc991 [file] [log] [blame]
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00001/*
2 * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
Paul Burtonbaf37f02013-11-08 11:18:50 +00003 * Copyright (C) 2013 Imagination Technologies
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00004 *
Tom Rini0b179982013-07-24 09:34:30 -04005 * SPDX-License-Identifier: GPL-2.0
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +00006 */
7
8#include <common.h>
Paul Burtonba21a452015-01-29 10:38:20 +00009#include <ide.h>
Gabor Juhosf1957492013-05-22 03:57:44 +000010#include <netdev.h>
Paul Burton81f98bb2013-11-08 11:18:57 +000011#include <pci.h>
Paul Burtonbaf37f02013-11-08 11:18:50 +000012#include <pci_gt64120.h>
13#include <pci_msc01.h>
Paul Burton3ced12a2013-11-08 11:18:55 +000014#include <rtc.h>
Paul Burtonbaf37f02013-11-08 11:18:50 +000015#include <serial.h>
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000016
Gabor Juhosfeaa6062013-05-22 03:57:42 +000017#include <asm/addrspace.h>
Gabor Juhos01564312013-05-22 03:57:38 +000018#include <asm/io.h>
19#include <asm/malta.h>
20
Paul Burtona257f622013-11-08 11:18:49 +000021#include "superio.h"
22
Paul Burtonbaf37f02013-11-08 11:18:50 +000023enum core_card {
24 CORE_UNKNOWN,
25 CORE_LV,
26 CORE_FPGA6,
27};
28
29enum sys_con {
30 SYSCON_UNKNOWN,
31 SYSCON_GT64120,
32 SYSCON_MSC01,
33};
34
Paul Burtone0ada632013-11-08 11:18:51 +000035static void malta_lcd_puts(const char *str)
36{
37 int i;
38 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0);
39
40 /* print up to 8 characters of the string */
Masahiro Yamadab4141192014-11-07 03:03:31 +090041 for (i = 0; i < min((int)strlen(str), 8); i++) {
Paul Burtone0ada632013-11-08 11:18:51 +000042 __raw_writel(str[i], reg);
43 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
44 }
45
46 /* fill the rest of the display with spaces */
47 for (; i < 8; i++) {
48 __raw_writel(' ', reg);
49 reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0;
50 }
51}
52
Paul Burtonbaf37f02013-11-08 11:18:50 +000053static enum core_card malta_core_card(void)
54{
55 u32 corid, rev;
Daniel Schwierzeck8061cfc2016-01-09 17:32:45 +010056 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION);
Paul Burtonbaf37f02013-11-08 11:18:50 +000057
Daniel Schwierzeck8061cfc2016-01-09 17:32:45 +010058 rev = __raw_readl(reg);
Paul Burtonbaf37f02013-11-08 11:18:50 +000059 corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF;
60
61 switch (corid) {
62 case MALTA_REVISION_CORID_CORE_LV:
63 return CORE_LV;
64
65 case MALTA_REVISION_CORID_CORE_FPGA6:
66 return CORE_FPGA6;
67
68 default:
69 return CORE_UNKNOWN;
70 }
71}
72
73static enum sys_con malta_sys_con(void)
74{
75 switch (malta_core_card()) {
76 case CORE_LV:
77 return SYSCON_GT64120;
78
79 case CORE_FPGA6:
80 return SYSCON_MSC01;
81
82 default:
83 return SYSCON_UNKNOWN;
84 }
85}
86
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +000087phys_size_t initdram(int board_type)
88{
89 return CONFIG_SYS_MEM_SIZE;
90}
91
92int checkboard(void)
93{
Paul Burtonbaf37f02013-11-08 11:18:50 +000094 enum core_card core;
95
Bin Menga1875592016-02-05 19:30:11 -080096 malta_lcd_puts("U-Boot");
Paul Burtonbaf37f02013-11-08 11:18:50 +000097 puts("Board: MIPS Malta");
98
99 core = malta_core_card();
100 switch (core) {
101 case CORE_LV:
102 puts(" CoreLV");
103 break;
104
105 case CORE_FPGA6:
106 puts(" CoreFPGA6");
107 break;
108
109 default:
110 puts(" CoreUnknown");
111 }
112
113 putc('\n');
Gabor Juhos5a4dcfa2013-05-22 03:57:37 +0000114 return 0;
115}
Gabor Juhos01564312013-05-22 03:57:38 +0000116
Gabor Juhosf1957492013-05-22 03:57:44 +0000117int board_eth_init(bd_t *bis)
118{
119 return pci_eth_init(bis);
120}
121
Gabor Juhos01564312013-05-22 03:57:38 +0000122void _machine_restart(void)
123{
124 void __iomem *reset_base;
125
126 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
127 __raw_writel(GORESET, reset_base);
Paul Burton28c8c3d2015-01-29 10:38:21 +0000128 mdelay(1000);
Gabor Juhos01564312013-05-22 03:57:38 +0000129}
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000130
Paul Burtona257f622013-11-08 11:18:49 +0000131int board_early_init_f(void)
132{
Paul Burton91ec6152016-01-29 13:54:54 +0000133 ulong io_base;
Paul Burtonbaf37f02013-11-08 11:18:50 +0000134
135 /* choose correct PCI I/O base */
136 switch (malta_sys_con()) {
137 case SYSCON_GT64120:
Paul Burton91ec6152016-01-29 13:54:54 +0000138 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE);
Paul Burtonbaf37f02013-11-08 11:18:50 +0000139 break;
140
141 case SYSCON_MSC01:
Paul Burton91ec6152016-01-29 13:54:54 +0000142 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE);
Paul Burtonbaf37f02013-11-08 11:18:50 +0000143 break;
144
145 default:
146 return -1;
147 }
148
Paul Burton91ec6152016-01-29 13:54:54 +0000149 set_io_port_base(io_base);
Paul Burton19a5ef62016-01-29 13:54:53 +0000150
Paul Burtona257f622013-11-08 11:18:49 +0000151 /* setup FDC37M817 super I/O controller */
Paul Burton91ec6152016-01-29 13:54:54 +0000152 malta_superio_init();
Paul Burtona257f622013-11-08 11:18:49 +0000153
154 return 0;
155}
156
Paul Burton3ced12a2013-11-08 11:18:55 +0000157int misc_init_r(void)
158{
159 rtc_reset();
160
161 return 0;
162}
163
Paul Burtonbaf37f02013-11-08 11:18:50 +0000164struct serial_device *default_serial_console(void)
165{
166 switch (malta_sys_con()) {
167 case SYSCON_GT64120:
168 return &eserial1_device;
169
170 default:
171 case SYSCON_MSC01:
172 return &eserial2_device;
173 }
174}
175
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000176void pci_init_board(void)
177{
Paul Burton81f98bb2013-11-08 11:18:57 +0000178 pci_dev_t bdf;
Paul Burtonbea12b72013-11-26 17:45:27 +0000179 u32 val32;
180 u8 val8;
Paul Burton81f98bb2013-11-08 11:18:57 +0000181
Paul Burtonbaf37f02013-11-08 11:18:50 +0000182 switch (malta_sys_con()) {
183 case SYSCON_GT64120:
Paul Burtonbaf37f02013-11-08 11:18:50 +0000184 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
185 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
186 0x10000000, 0x10000000, 128 * 1024 * 1024,
187 0x00000000, 0x00000000, 0x20000);
188 break;
189
190 default:
191 case SYSCON_MSC01:
Paul Burtonbaf37f02013-11-08 11:18:50 +0000192 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
193 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
194 MALTA_MSC01_PCIMEM_MAP,
195 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
196 MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
197 0x00000000, MALTA_MSC01_PCIIO_SIZE);
198 break;
199 }
Paul Burton81f98bb2013-11-08 11:18:57 +0000200
201 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
202 PCI_DEVICE_ID_INTEL_82371AB_0, 0);
203 if (bdf == -1)
204 panic("Failed to find PIIX4 PCI bridge\n");
205
206 /* setup PCI interrupt routing */
207 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
208 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
209 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
210 pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
Paul Burtonbea12b72013-11-26 17:45:27 +0000211
212 /* mux SERIRQ onto SERIRQ pin */
213 pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
214 val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
215 pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
216
217 /* enable SERIRQ - Linux currently depends upon this */
218 pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
219 val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
220 pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
Paul Burtonba21a452015-01-29 10:38:20 +0000221
222 bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
223 PCI_DEVICE_ID_INTEL_82371AB, 0);
224 if (bdf == -1)
225 panic("Failed to find PIIX4 IDE controller\n");
226
227 /* enable bus master & IO access */
228 val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
229 pci_write_config_dword(bdf, PCI_COMMAND, val32);
230
231 /* set latency */
232 pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
233
234 /* enable IDE/ATA */
235 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
236 PCI_CFG_PIIX4_IDETIM_IDE);
237 pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
238 PCI_CFG_PIIX4_IDETIM_IDE);
Gabor Juhosfeaa6062013-05-22 03:57:42 +0000239}