Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org> |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 3 | * Copyright (C) 2013 Imagination Technologies |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 4 | * |
Tom Rini | 0b17998 | 2013-07-24 09:34:30 -0400 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0 |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Gabor Juhos | f195749 | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 9 | #include <netdev.h> |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 10 | #include <pci_gt64120.h> |
| 11 | #include <pci_msc01.h> |
Paul Burton | 3ced12a | 2013-11-08 11:18:55 +0000 | [diff] [blame^] | 12 | #include <rtc.h> |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 13 | #include <serial.h> |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 14 | |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 15 | #include <asm/addrspace.h> |
Gabor Juhos | 0156431 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <asm/malta.h> |
| 18 | |
Paul Burton | a257f62 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 19 | #include "superio.h" |
| 20 | |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 21 | enum core_card { |
| 22 | CORE_UNKNOWN, |
| 23 | CORE_LV, |
| 24 | CORE_FPGA6, |
| 25 | }; |
| 26 | |
| 27 | enum sys_con { |
| 28 | SYSCON_UNKNOWN, |
| 29 | SYSCON_GT64120, |
| 30 | SYSCON_MSC01, |
| 31 | }; |
| 32 | |
Paul Burton | e0ada63 | 2013-11-08 11:18:51 +0000 | [diff] [blame] | 33 | static void malta_lcd_puts(const char *str) |
| 34 | { |
| 35 | int i; |
| 36 | void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); |
| 37 | |
| 38 | /* print up to 8 characters of the string */ |
| 39 | for (i = 0; i < min(strlen(str), 8); i++) { |
| 40 | __raw_writel(str[i], reg); |
| 41 | reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; |
| 42 | } |
| 43 | |
| 44 | /* fill the rest of the display with spaces */ |
| 45 | for (; i < 8; i++) { |
| 46 | __raw_writel(' ', reg); |
| 47 | reg += MALTA_ASCIIPOS1 - MALTA_ASCIIPOS0; |
| 48 | } |
| 49 | } |
| 50 | |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 51 | static enum core_card malta_core_card(void) |
| 52 | { |
| 53 | u32 corid, rev; |
| 54 | |
| 55 | rev = __raw_readl(CKSEG1ADDR(MALTA_REVISION)); |
| 56 | corid = (rev & MALTA_REVISION_CORID_MSK) >> MALTA_REVISION_CORID_SHF; |
| 57 | |
| 58 | switch (corid) { |
| 59 | case MALTA_REVISION_CORID_CORE_LV: |
| 60 | return CORE_LV; |
| 61 | |
| 62 | case MALTA_REVISION_CORID_CORE_FPGA6: |
| 63 | return CORE_FPGA6; |
| 64 | |
| 65 | default: |
| 66 | return CORE_UNKNOWN; |
| 67 | } |
| 68 | } |
| 69 | |
| 70 | static enum sys_con malta_sys_con(void) |
| 71 | { |
| 72 | switch (malta_core_card()) { |
| 73 | case CORE_LV: |
| 74 | return SYSCON_GT64120; |
| 75 | |
| 76 | case CORE_FPGA6: |
| 77 | return SYSCON_MSC01; |
| 78 | |
| 79 | default: |
| 80 | return SYSCON_UNKNOWN; |
| 81 | } |
| 82 | } |
| 83 | |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 84 | phys_size_t initdram(int board_type) |
| 85 | { |
| 86 | return CONFIG_SYS_MEM_SIZE; |
| 87 | } |
| 88 | |
| 89 | int checkboard(void) |
| 90 | { |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 91 | enum core_card core; |
| 92 | |
Paul Burton | e0ada63 | 2013-11-08 11:18:51 +0000 | [diff] [blame] | 93 | malta_lcd_puts("U-boot"); |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 94 | puts("Board: MIPS Malta"); |
| 95 | |
| 96 | core = malta_core_card(); |
| 97 | switch (core) { |
| 98 | case CORE_LV: |
| 99 | puts(" CoreLV"); |
| 100 | break; |
| 101 | |
| 102 | case CORE_FPGA6: |
| 103 | puts(" CoreFPGA6"); |
| 104 | break; |
| 105 | |
| 106 | default: |
| 107 | puts(" CoreUnknown"); |
| 108 | } |
| 109 | |
| 110 | putc('\n'); |
Gabor Juhos | 5a4dcfa | 2013-05-22 03:57:37 +0000 | [diff] [blame] | 111 | return 0; |
| 112 | } |
Gabor Juhos | 0156431 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 113 | |
Gabor Juhos | f195749 | 2013-05-22 03:57:44 +0000 | [diff] [blame] | 114 | int board_eth_init(bd_t *bis) |
| 115 | { |
| 116 | return pci_eth_init(bis); |
| 117 | } |
| 118 | |
Gabor Juhos | 0156431 | 2013-05-22 03:57:38 +0000 | [diff] [blame] | 119 | void _machine_restart(void) |
| 120 | { |
| 121 | void __iomem *reset_base; |
| 122 | |
| 123 | reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); |
| 124 | __raw_writel(GORESET, reset_base); |
| 125 | } |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 126 | |
Paul Burton | a257f62 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 127 | int board_early_init_f(void) |
| 128 | { |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 129 | void *io_base; |
| 130 | |
| 131 | /* choose correct PCI I/O base */ |
| 132 | switch (malta_sys_con()) { |
| 133 | case SYSCON_GT64120: |
| 134 | io_base = (void *)CKSEG1ADDR(MALTA_GT_PCIIO_BASE); |
| 135 | break; |
| 136 | |
| 137 | case SYSCON_MSC01: |
| 138 | io_base = (void *)CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); |
| 139 | break; |
| 140 | |
| 141 | default: |
| 142 | return -1; |
| 143 | } |
| 144 | |
Paul Burton | a257f62 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 145 | /* setup FDC37M817 super I/O controller */ |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 146 | malta_superio_init(io_base); |
Paul Burton | a257f62 | 2013-11-08 11:18:49 +0000 | [diff] [blame] | 147 | |
| 148 | return 0; |
| 149 | } |
| 150 | |
Paul Burton | 3ced12a | 2013-11-08 11:18:55 +0000 | [diff] [blame^] | 151 | int misc_init_r(void) |
| 152 | { |
| 153 | rtc_reset(); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 158 | struct serial_device *default_serial_console(void) |
| 159 | { |
| 160 | switch (malta_sys_con()) { |
| 161 | case SYSCON_GT64120: |
| 162 | return &eserial1_device; |
| 163 | |
| 164 | default: |
| 165 | case SYSCON_MSC01: |
| 166 | return &eserial2_device; |
| 167 | } |
| 168 | } |
| 169 | |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 170 | void pci_init_board(void) |
| 171 | { |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 172 | switch (malta_sys_con()) { |
| 173 | case SYSCON_GT64120: |
| 174 | set_io_port_base(CKSEG1ADDR(MALTA_GT_PCIIO_BASE)); |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 175 | |
Paul Burton | baf37f0 | 2013-11-08 11:18:50 +0000 | [diff] [blame] | 176 | gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), |
| 177 | 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, |
| 178 | 0x10000000, 0x10000000, 128 * 1024 * 1024, |
| 179 | 0x00000000, 0x00000000, 0x20000); |
| 180 | break; |
| 181 | |
| 182 | default: |
| 183 | case SYSCON_MSC01: |
| 184 | set_io_port_base(CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE)); |
| 185 | |
| 186 | msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), |
| 187 | 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE, |
| 188 | MALTA_MSC01_PCIMEM_MAP, |
| 189 | CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), |
| 190 | MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP, |
| 191 | 0x00000000, MALTA_MSC01_PCIIO_SIZE); |
| 192 | break; |
| 193 | } |
Gabor Juhos | feaa606 | 2013-05-22 03:57:42 +0000 | [diff] [blame] | 194 | } |