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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek84c72042015-01-15 10:01:51 +01002/*
3 * (C) Copyright 2014 - 2015 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek84c72042015-01-15 10:01:51 +01005 */
6
7#include <common.h>
8#include <asm/arch/hardware.h>
9#include <asm/arch/sys_proto.h>
Alexander Graf96519f32016-03-04 01:09:49 +010010#include <asm/armv8/mmu.h>
Michal Simek84c72042015-01-15 10:01:51 +010011#include <asm/io.h>
12
13#define ZYNQ_SILICON_VER_MASK 0xF000
14#define ZYNQ_SILICON_VER_SHIFT 12
15
16DECLARE_GLOBAL_DATA_PTR;
17
Nitin Jain06789412018-04-20 12:30:40 +053018/*
19 * Number of filled static entries and also the first empty
20 * slot in zynqmp_mem_map.
21 */
22#define ZYNQMP_MEM_MAP_USED 4
23
Siva Durga Prasad Paladugu3b644a32018-01-12 15:35:46 +053024#if !defined(CONFIG_ZYNQMP_NO_DDR)
Nitin Jain06789412018-04-20 12:30:40 +053025#define DRAM_BANKS CONFIG_NR_DRAM_BANKS
26#else
27#define DRAM_BANKS 0
Siva Durga Prasad Paladugu3b644a32018-01-12 15:35:46 +053028#endif
Nitin Jain06789412018-04-20 12:30:40 +053029
30#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
31#define TCM_MAP 1
32#else
33#define TCM_MAP 0
34#endif
35
36/* +1 is end of list which needs to be empty */
37#define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1)
38
39static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = {
Siva Durga Prasad Paladugu3b644a32018-01-12 15:35:46 +053040 {
York Suncd4b0c52016-06-24 16:46:22 -070041 .virt = 0x80000000UL,
42 .phys = 0x80000000UL,
Alexander Graf96519f32016-03-04 01:09:49 +010043 .size = 0x70000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 PTE_BLOCK_NON_SHARE |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
Nitin Jain06789412018-04-20 12:30:40 +053047 }, {
York Suncd4b0c52016-06-24 16:46:22 -070048 .virt = 0xf8000000UL,
49 .phys = 0xf8000000UL,
Alexander Graf96519f32016-03-04 01:09:49 +010050 .size = 0x07e00000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
54 }, {
York Suncd4b0c52016-06-24 16:46:22 -070055 .virt = 0x400000000UL,
56 .phys = 0x400000000UL,
Anders Hedlund501fbc62017-12-19 17:24:41 +010057 .size = 0x400000000UL,
Alexander Graf96519f32016-03-04 01:09:49 +010058 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
59 PTE_BLOCK_NON_SHARE |
60 PTE_BLOCK_PXN | PTE_BLOCK_UXN
Nitin Jain06789412018-04-20 12:30:40 +053061 }, {
Anders Hedlund501fbc62017-12-19 17:24:41 +010062 .virt = 0x1000000000UL,
63 .phys = 0x1000000000UL,
64 .size = 0xf000000000UL,
Alexander Graf96519f32016-03-04 01:09:49 +010065 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
66 PTE_BLOCK_NON_SHARE |
67 PTE_BLOCK_PXN | PTE_BLOCK_UXN
Alexander Graf96519f32016-03-04 01:09:49 +010068 }
69};
Nitin Jain06789412018-04-20 12:30:40 +053070
71void mem_map_fill(void)
72{
73 int banks = ZYNQMP_MEM_MAP_USED;
74
75#if defined(CONFIG_DEFINE_TCM_OCM_MMAP)
76 zynqmp_mem_map[banks].virt = 0xffe00000UL;
77 zynqmp_mem_map[banks].phys = 0xffe00000UL;
78 zynqmp_mem_map[banks].size = 0x00200000UL;
79 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
80 PTE_BLOCK_INNER_SHARE;
81 banks = banks + 1;
82#endif
83
84#if !defined(CONFIG_ZYNQMP_NO_DDR)
85 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
86 /* Zero size means no more DDR that's this is end */
87 if (!gd->bd->bi_dram[i].size)
88 break;
89
90 zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start;
91 zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start;
92 zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size;
93 zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
94 PTE_BLOCK_INNER_SHARE;
95 banks = banks + 1;
96 }
97#endif
98}
99
Alexander Graf96519f32016-03-04 01:09:49 +0100100struct mm_region *mem_map = zynqmp_mem_map;
101
Michal Simek9c152ed2016-05-30 10:41:26 +0200102u64 get_page_table_size(void)
103{
104 return 0x14000;
105}
106
Siva Durga Prasad Paladugu5860bc12018-10-05 15:09:05 +0530107#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
108void tcm_init(u8 mode)
Siva Durga Prasad Paladugu12ad2992018-10-05 15:09:04 +0530109{
110 puts("WARNING: Initializing TCM overwrites TCM content\n");
111 initialize_tcm(mode);
112 memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE);
113}
Siva Durga Prasad Paladugu5860bc12018-10-05 15:09:05 +0530114#endif
Siva Durga Prasad Paladugu12ad2992018-10-05 15:09:04 +0530115
Siva Durga Prasad Paladugu5860bc12018-10-05 15:09:05 +0530116#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
Siva Durga Prasad Paladugue042d362017-07-13 19:01:11 +0530117int reserve_mmu(void)
118{
Siva Durga Prasad Paladugu12ad2992018-10-05 15:09:04 +0530119 tcm_init(TCM_LOCK);
Siva Durga Prasad Paladugue042d362017-07-13 19:01:11 +0530120 gd->arch.tlb_size = PGTABLE_SIZE;
121 gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR;
122
123 return 0;
124}
125#endif
126
Michal Simek0785dfd2015-11-05 08:34:35 +0100127static unsigned int zynqmp_get_silicon_version_secure(void)
128{
129 u32 ver;
130
131 ver = readl(&csu_base->version);
132 ver &= ZYNQMP_SILICON_VER_MASK;
133 ver >>= ZYNQMP_SILICON_VER_SHIFT;
134
135 return ver;
136}
137
Michal Simek84c72042015-01-15 10:01:51 +0100138unsigned int zynqmp_get_silicon_version(void)
139{
Michal Simek0785dfd2015-11-05 08:34:35 +0100140 if (current_el() == 3)
141 return zynqmp_get_silicon_version_secure();
142
Michal Simek84c72042015-01-15 10:01:51 +0100143 gd->cpu_clk = get_tbclk();
144
145 switch (gd->cpu_clk) {
146 case 50000000:
147 return ZYNQMP_CSU_VERSION_QEMU;
148 }
149
Michal Simekbe6f6af2015-08-20 14:01:39 +0200150 return ZYNQMP_CSU_VERSION_SILICON;
Michal Simek84c72042015-01-15 10:01:51 +0100151}
Siva Durga Prasad Paladugue0752bc2017-02-02 01:10:46 +0530152
153#define ZYNQMP_MMIO_READ 0xC2000014
154#define ZYNQMP_MMIO_WRITE 0xC2000013
155
Siva Durga Prasad Paladugucb186e72017-07-13 19:01:12 +0530156int __maybe_unused invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2,
157 u32 arg3, u32 *ret_payload)
Siva Durga Prasad Paladugue0752bc2017-02-02 01:10:46 +0530158{
159 /*
160 * Added SIP service call Function Identifier
161 * Make sure to stay in x0 register
162 */
163 struct pt_regs regs;
164
165 regs.regs[0] = pm_api_id;
166 regs.regs[1] = ((u64)arg1 << 32) | arg0;
167 regs.regs[2] = ((u64)arg3 << 32) | arg2;
168
169 smc_call(&regs);
170
171 if (ret_payload != NULL) {
172 ret_payload[0] = (u32)regs.regs[0];
173 ret_payload[1] = upper_32_bits(regs.regs[0]);
174 ret_payload[2] = (u32)regs.regs[1];
175 ret_payload[3] = upper_32_bits(regs.regs[1]);
176 ret_payload[4] = (u32)regs.regs[2];
177 }
178
179 return regs.regs[0];
180}
181
Michal Simekf11d4ab2018-12-20 09:41:12 +0100182unsigned int __maybe_unused zynqmp_pmufw_version(void)
Michal Simekfb4000e2017-02-07 14:32:26 +0100183{
184 int ret;
185 u32 ret_payload[PAYLOAD_ARG_CNT];
Siva Durga Prasad Paladugub94a8272018-08-21 15:44:49 +0530186 static u32 pm_api_version = ZYNQMP_PM_VERSION_INVALID;
Michal Simekfb4000e2017-02-07 14:32:26 +0100187
Siva Durga Prasad Paladugub94a8272018-08-21 15:44:49 +0530188 /*
189 * Get PMU version only once and later
190 * just return stored values instead of
191 * asking PMUFW again.
192 */
193 if (pm_api_version == ZYNQMP_PM_VERSION_INVALID) {
194 ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
195 ret_payload);
196 pm_api_version = ret_payload[1];
Michal Simekfb4000e2017-02-07 14:32:26 +0100197
Siva Durga Prasad Paladugub94a8272018-08-21 15:44:49 +0530198 if (ret)
199 panic("PMUFW is not found - Please load it!\n");
200 }
Michal Simekfb4000e2017-02-07 14:32:26 +0100201
Siva Durga Prasad Paladugub94a8272018-08-21 15:44:49 +0530202 return pm_api_version;
Michal Simekfb4000e2017-02-07 14:32:26 +0100203}
Michal Simekfb4000e2017-02-07 14:32:26 +0100204
Siva Durga Prasad Paladugucb186e72017-07-13 19:01:12 +0530205static int zynqmp_mmio_rawwrite(const u32 address,
Siva Durga Prasad Paladugue0752bc2017-02-02 01:10:46 +0530206 const u32 mask,
207 const u32 value)
208{
209 u32 data;
210 u32 value_local = value;
Michal Simeke3c26b82018-06-13 10:38:33 +0200211 int ret;
Siva Durga Prasad Paladugue0752bc2017-02-02 01:10:46 +0530212
Michal Simeke3c26b82018-06-13 10:38:33 +0200213 ret = zynqmp_mmio_read(address, &data);
214 if (ret)
215 return ret;
216
Siva Durga Prasad Paladugue0752bc2017-02-02 01:10:46 +0530217 data &= ~mask;
218 value_local &= mask;
219 value_local |= data;
220 writel(value_local, (ulong)address);
221 return 0;
222}
223
Siva Durga Prasad Paladugucb186e72017-07-13 19:01:12 +0530224static int zynqmp_mmio_rawread(const u32 address, u32 *value)
Siva Durga Prasad Paladugue0752bc2017-02-02 01:10:46 +0530225{
226 *value = readl((ulong)address);
227 return 0;
228}
Siva Durga Prasad Paladugucb186e72017-07-13 19:01:12 +0530229
230int zynqmp_mmio_write(const u32 address,
231 const u32 mask,
232 const u32 value)
233{
234 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3)
235 return zynqmp_mmio_rawwrite(address, mask, value);
Heinrich Schuchardt549d6842017-10-13 01:14:27 +0200236 else
Siva Durga Prasad Paladugucb186e72017-07-13 19:01:12 +0530237 return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask,
238 value, 0, NULL);
239
240 return -EINVAL;
241}
242
243int zynqmp_mmio_read(const u32 address, u32 *value)
244{
245 u32 ret_payload[PAYLOAD_ARG_CNT];
246 u32 ret;
247
248 if (!value)
249 return -EINVAL;
250
251 if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) {
252 ret = zynqmp_mmio_rawread(address, value);
Heinrich Schuchardt549d6842017-10-13 01:14:27 +0200253 } else {
Siva Durga Prasad Paladugucb186e72017-07-13 19:01:12 +0530254 ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0,
255 0, ret_payload);
256 *value = ret_payload[1];
257 }
258
259 return ret;
260}