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wdenk42d1f032003-10-15 23:53:47 +00001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2004, 2011 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenk42d1f032003-10-15 23:53:47 +00007 */
8
wdenk0ac6f8b2004-07-09 23:27:13 +00009/*
10 * mpc8540ads board configuration file
11 *
12 * Please refer to doc/README.mpc85xx for more info.
13 *
14 * Make sure you change the MAC address and other network params first,
Joe Hershberger92ac5202015-05-04 14:55:14 -050015 * search for CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
York Sun9ae14ca2015-08-18 12:35:52 -070021#define CONFIG_SYS_GENERIC_BOARD
22#define CONFIG_DISPLAY_BOARDINFO
23
wdenk42d1f032003-10-15 23:53:47 +000024/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000025#define CONFIG_BOOKE 1 /* BOOKE */
26#define CONFIG_E500 1 /* BOOKE e500 family */
wdenk0ac6f8b2004-07-09 23:27:13 +000027#define CONFIG_MPC8540 1 /* MPC8540 specific */
28#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
wdenk42d1f032003-10-15 23:53:47 +000029
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030/*
31 * default CCARBAR is at 0xff700000
32 * assume U-Boot is less than 0.5MB
33 */
34#define CONFIG_SYS_TEXT_BASE 0xfff80000
35
Jon Loeliger288693a2005-07-25 12:14:54 -050036#ifndef CONFIG_HAS_FEC
37#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
38#endif
39
wdenk0ac6f8b2004-07-09 23:27:13 +000040#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000041#define CONFIG_PCI_INDIRECT_BRIDGE
Kumar Gala0151cba2008-10-21 11:33:58 -050042#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000044#define CONFIG_ENV_OVERWRITE
Kumar Gala7232a272008-01-16 01:32:06 -060045#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
wdenk42d1f032003-10-15 23:53:47 +000046
wdenk0ac6f8b2004-07-09 23:27:13 +000047/*
48 * sysclk for MPC85xx
49 *
50 * Two valid values are:
51 * 33000000
52 * 66000000
53 *
54 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000055 * is likely the desired value here, so that is now the default.
56 * The board, however, can run at 66MHz. In any event, this value
57 * must match the settings of some switches. Details can be found
58 * in the README.mpc85xxads.
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050059 *
60 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
61 * 33MHz to accommodate, based on a PCI pin.
62 * Note that PCI-X won't work at 33MHz.
wdenk0ac6f8b2004-07-09 23:27:13 +000063 */
64
wdenk9aea9532004-08-01 23:02:45 +000065#ifndef CONFIG_SYS_CLK_FREQ
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050066#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000067#endif
68
wdenk9aea9532004-08-01 23:02:45 +000069
wdenk0ac6f8b2004-07-09 23:27:13 +000070/*
71 * These can be toggled for performance analysis, otherwise use default.
72 */
73#define CONFIG_L2_CACHE /* toggle L2 cache */
74#define CONFIG_BTB /* toggle branch predition */
wdenk42d1f032003-10-15 23:53:47 +000075
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
77#define CONFIG_SYS_MEMTEST_END 0x00400000
wdenk42d1f032003-10-15 23:53:47 +000078
Timur Tabie46fedf2011-08-04 18:03:41 -050079#define CONFIG_SYS_CCSRBAR 0xe0000000
80#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
wdenk42d1f032003-10-15 23:53:47 +000081
Kumar Gala9617c8d2008-06-06 13:12:18 -050082/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070083#define CONFIG_SYS_FSL_DDR1
Kumar Gala9617c8d2008-06-06 13:12:18 -050084#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
85#define CONFIG_DDR_SPD
86#undef CONFIG_FSL_DDR_INTERACTIVE
wdenk9aea9532004-08-01 23:02:45 +000087
Kumar Gala9617c8d2008-06-06 13:12:18 -050088#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
89
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +000092
Kumar Gala9617c8d2008-06-06 13:12:18 -050093#define CONFIG_NUM_DDR_CONTROLLERS 1
94#define CONFIG_DIMM_SLOTS_PER_CTLR 1
95#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
wdenk9aea9532004-08-01 23:02:45 +000096
Kumar Gala9617c8d2008-06-06 13:12:18 -050097/* I2C addresses of SPD EEPROMs */
98#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
wdenk9aea9532004-08-01 23:02:45 +000099
Kumar Gala9617c8d2008-06-06 13:12:18 -0500100/* These are used when DDR doesn't use SPD. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
102#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
103#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
104#define CONFIG_SYS_DDR_TIMING_1 0x37344321
105#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
106#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
107#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
108#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
wdenk42d1f032003-10-15 23:53:47 +0000109
wdenk0ac6f8b2004-07-09 23:27:13 +0000110/*
111 * SDRAM on the Local Bus
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
114#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000115
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
117#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
120#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
121#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
122#undef CONFIG_SYS_FLASH_CHECKSUM
123#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
124#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000125
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200126#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
wdenk0ac6f8b2004-07-09 23:27:13 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
129#define CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000130#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#undef CONFIG_SYS_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000132#endif
133
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200134#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_FLASH_CFI
136#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000137
wdenk42d1f032003-10-15 23:53:47 +0000138#undef CONFIG_CLOCKS_IN_MHZ
139
wdenk0ac6f8b2004-07-09 23:27:13 +0000140
141/*
142 * Local Bus Definitions
143 */
144
145/*
146 * Base Register 2 and Option Register 2 configure SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
wdenk0ac6f8b2004-07-09 23:27:13 +0000148 *
149 * For BR2, need:
150 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
151 * port-size = 32-bits = BR2[19:20] = 11
152 * no parity checking = BR2[21:22] = 00
153 * SDRAM for MSEL = BR2[24:26] = 011
154 * Valid = BR[31] = 1
155 *
156 * 0 4 8 12 16 20 24 28
157 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
158 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
wdenk0ac6f8b2004-07-09 23:27:13 +0000160 * FIXME: the top 17 bits of BR2.
161 */
162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BR2_PRELIM 0xf0001861
wdenk0ac6f8b2004-07-09 23:27:13 +0000164
165/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
wdenk0ac6f8b2004-07-09 23:27:13 +0000167 *
168 * For OR2, need:
169 * 64MB mask for AM, OR2[0:7] = 1111 1100
170 * XAM, OR2[17:18] = 11
171 * 9 columns OR2[19-21] = 010
172 * 13 rows OR2[23-25] = 100
173 * EAD set for extra time OR[31] = 1
174 *
175 * 0 4 8 12 16 20 24 28
176 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
177 */
178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
182#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
183#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
184#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000185
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500186#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
187 | LSDMR_RFCR5 \
188 | LSDMR_PRETOACT3 \
189 | LSDMR_ACTTORW3 \
190 | LSDMR_BL8 \
191 | LSDMR_WRC2 \
192 | LSDMR_CL3 \
193 | LSDMR_RFEN \
wdenk0ac6f8b2004-07-09 23:27:13 +0000194 )
195
196/*
197 * SDRAM Controller configuration sequence.
198 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500199#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
200#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
201#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
202#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
203#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000204
wdenk42d1f032003-10-15 23:53:47 +0000205
wdenk9aea9532004-08-01 23:02:45 +0000206/*
207 * 32KB, 8-bit wide for ADS config reg
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_BR4_PRELIM 0xf8000801
210#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
211#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_INIT_RAM_LOCK 1
214#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200215#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000216
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200217#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk42d1f032003-10-15 23:53:47 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
221#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000222
223/* Serial Port */
224#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_NS16550
226#define CONFIG_SYS_NS16550_SERIAL
227#define CONFIG_SYS_NS16550_REG_SIZE 1
228#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk42d1f032003-10-15 23:53:47 +0000231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
234#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000235
236/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_HUSH_PARSER
238#ifdef CONFIG_SYS_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000239#endif
240
Matthew McClintock0e163872006-06-28 10:43:36 -0500241/* pass open firmware flat tree */
Kumar Gala0fd5ec62007-11-28 22:54:27 -0600242#define CONFIG_OF_LIBFDT 1
243#define CONFIG_OF_BOARD_SETUP 1
244#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Matthew McClintock0e163872006-06-28 10:43:36 -0500245
Jon Loeliger20476722006-10-20 15:50:15 -0500246/*
247 * I2C
248 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200249#define CONFIG_SYS_I2C
250#define CONFIG_SYS_I2C_FSL
251#define CONFIG_SYS_FSL_I2C_SPEED 400000
252#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
253#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
254#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
wdenk42d1f032003-10-15 23:53:47 +0000255
wdenk0ac6f8b2004-07-09 23:27:13 +0000256/* RapidIO MMU */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600257#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
Kumar Gala10795f42008-12-02 16:08:36 -0600258#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600259#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000261
262/*
263 * General PCI
Sergei Shtylyov362dd832006-12-27 22:07:15 +0300264 * Memory space is mapped 1-1, but I/O space must start from 0.
wdenk0ac6f8b2004-07-09 23:27:13 +0000265 */
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600266#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
Kumar Gala10795f42008-12-02 16:08:36 -0600267#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
Kumar Gala5af0fdd2008-12-02 16:08:39 -0600268#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Galaaca5f012008-12-02 16:08:40 -0600270#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
Kumar Gala5f91ef62008-12-02 16:08:37 -0600271#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
273#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000274
wdenk42d1f032003-10-15 23:53:47 +0000275#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000276
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200277#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000278
wdenk42d1f032003-10-15 23:53:47 +0000279#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000280#undef CONFIG_TULIP
281
282#if !defined(CONFIG_PCI_PNP)
283 #define PCI_ENET0_IOADDR 0xe0000000
284 #define PCI_ENET0_MEMADDR 0xe0000000
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200285 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000286#endif
287
wdenk0ac6f8b2004-07-09 23:27:13 +0000288#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
wdenk0ac6f8b2004-07-09 23:27:13 +0000290
291#endif /* CONFIG_PCI */
292
293
294#if defined(CONFIG_TSEC_ENET)
295
wdenk0ac6f8b2004-07-09 23:27:13 +0000296#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500297#define CONFIG_TSEC1 1
298#define CONFIG_TSEC1_NAME "TSEC0"
299#define CONFIG_TSEC2 1
300#define CONFIG_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000301#define TSEC1_PHY_ADDR 0
302#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000303#define TSEC1_PHYIDX 0
304#define TSEC2_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500305#define TSEC1_FLAGS TSEC_GIGABIT
306#define TSEC2_FLAGS TSEC_GIGABIT
wdenk9aea9532004-08-01 23:02:45 +0000307
Jon Loeliger288693a2005-07-25 12:14:54 -0500308
309#if CONFIG_HAS_FEC
wdenk9aea9532004-08-01 23:02:45 +0000310#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500311#define CONFIG_MPC85XX_FEC_NAME "FEC"
wdenk9aea9532004-08-01 23:02:45 +0000312#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000313#define FEC_PHYIDX 0
Andy Fleming3a790132007-08-15 20:03:25 -0500314#define FEC_FLAGS 0
Jon Loeliger288693a2005-07-25 12:14:54 -0500315#endif
wdenk9aea9532004-08-01 23:02:45 +0000316
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500317/* Options are: TSEC[0-1], FEC */
318#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000319
320#endif /* CONFIG_TSEC_ENET */
321
322
323/*
324 * Environment
325 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200327 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200329 #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
330 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000331#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200333 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200335 #define CONFIG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000336#endif
337
wdenk0ac6f8b2004-07-09 23:27:13 +0000338#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000340
Jon Loeliger2835e512007-06-13 13:22:08 -0500341
342/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500343 * BOOTP options
344 */
345#define CONFIG_BOOTP_BOOTFILESIZE
346#define CONFIG_BOOTP_BOOTPATH
347#define CONFIG_BOOTP_GATEWAY
348#define CONFIG_BOOTP_HOSTNAME
349
350
351/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500352 * Command line configuration.
353 */
Jon Loeliger2835e512007-06-13 13:22:08 -0500354#define CONFIG_CMD_PING
355#define CONFIG_CMD_I2C
Kumar Gala82ac8c92007-12-07 12:04:30 -0600356#define CONFIG_CMD_ELF
Kumar Gala1c9aa762008-09-22 23:40:42 -0500357#define CONFIG_CMD_IRQ
Jon Loeliger2835e512007-06-13 13:22:08 -0500358
359#if defined(CONFIG_PCI)
360 #define CONFIG_CMD_PCI
wdenk42d1f032003-10-15 23:53:47 +0000361#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000362
wdenk0ac6f8b2004-07-09 23:27:13 +0000363#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000364
365/*
366 * Miscellaneous configurable options
367 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500369#define CONFIG_CMDLINE_EDITING /* Command-line editing */
370#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000372
Jon Loeliger2835e512007-06-13 13:22:08 -0500373#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200374 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000375#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000377#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000378
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
380#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
381#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000382
383/*
384 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500385 * have to be in the first 64 MB of memory, since this is
wdenk42d1f032003-10-15 23:53:47 +0000386 * the maximum mapped by the Linux kernel during initialization.
387 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500388#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
389#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
wdenk42d1f032003-10-15 23:53:47 +0000390
Jon Loeliger2835e512007-06-13 13:22:08 -0500391#if defined(CONFIG_CMD_KGDB)
wdenk42d1f032003-10-15 23:53:47 +0000392#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
wdenk42d1f032003-10-15 23:53:47 +0000393#endif
394
wdenk9aea9532004-08-01 23:02:45 +0000395
396/*
397 * Environment Configuration
398 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000399
400/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000401#if defined(CONFIG_TSEC_ENET)
Andy Fleming10327dc2007-08-16 16:35:02 -0500402#define CONFIG_HAS_ETH0
wdenke2ffd592004-12-31 09:32:47 +0000403#define CONFIG_HAS_ETH1
wdenke2ffd592004-12-31 09:32:47 +0000404#define CONFIG_HAS_ETH2
wdenk42d1f032003-10-15 23:53:47 +0000405#endif
406
wdenk0ac6f8b2004-07-09 23:27:13 +0000407#define CONFIG_IPADDR 192.168.1.253
408
409#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000410#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000411#define CONFIG_BOOTFILE "your.uImage"
wdenk0ac6f8b2004-07-09 23:27:13 +0000412
413#define CONFIG_SERVERIP 192.168.1.1
414#define CONFIG_GATEWAYIP 192.168.1.1
415#define CONFIG_NETMASK 255.255.255.0
416
417#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
418
419#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
420#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
421
422#define CONFIG_BAUDRATE 115200
423
wdenk9aea9532004-08-01 23:02:45 +0000424#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000425 "netdev=eth0\0" \
426 "consoledev=ttyS0\0" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500427 "ramdiskaddr=1000000\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500428 "ramdiskfile=your.ramdisk.u-boot\0" \
429 "fdtaddr=400000\0" \
430 "fdtfile=your.fdt.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000431
wdenk9aea9532004-08-01 23:02:45 +0000432#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000433 "setenv bootargs root=/dev/nfs rw " \
434 "nfsroot=$serverip:$rootpath " \
435 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
436 "console=$consoledev,$baudrate $othbootargs;" \
437 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500438 "tftp $fdtaddr $fdtfile;" \
439 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000440
441#define CONFIG_RAMBOOTCOMMAND \
442 "setenv bootargs root=/dev/ram rw " \
443 "console=$consoledev,$baudrate $othbootargs;" \
444 "tftp $ramdiskaddr $ramdiskfile;" \
445 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500446 "tftp $fdtaddr $fdtfile;" \
Andy Flemingd3ec0d92007-05-10 17:50:01 -0500447 "bootm $loadaddr $ramdiskaddr $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000448
449#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000450
451#endif /* __CONFIG_H */