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Marek Vasut0d4e8502011-11-08 23:18:16 +00001/*
2 * Freescale i.MX28 NAND flash driver
3 *
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
6 *
7 * Based on code from LTIB:
8 * Freescale GPMI NFC NAND Flash Driver
9 *
10 * Copyright (C) 2010 Freescale Semiconductor, Inc.
11 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
12 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Marek Vasut0d4e8502011-11-08 23:18:16 +000014 */
15
Tom Warren651eb732012-09-10 08:47:51 -070016#include <common.h>
Marek Vasut0d4e8502011-11-08 23:18:16 +000017#include <linux/mtd/mtd.h>
18#include <linux/mtd/nand.h>
19#include <linux/types.h>
Marek Vasut0d4e8502011-11-08 23:18:16 +000020#include <malloc.h>
21#include <asm/errno.h>
22#include <asm/io.h>
23#include <asm/arch/clock.h>
24#include <asm/arch/imx-regs.h>
Stefan Roese04992182013-04-09 21:06:07 +000025#include <asm/imx-common/regs-bch.h>
26#include <asm/imx-common/regs-gpmi.h>
Marek Vasut0d4e8502011-11-08 23:18:16 +000027#include <asm/arch/sys_proto.h>
Stefan Roese04992182013-04-09 21:06:07 +000028#include <asm/imx-common/dma.h>
Marek Vasut0d4e8502011-11-08 23:18:16 +000029
30#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
31
32#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
Peng Fanbedaa842015-12-22 17:04:23 +080033#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
Stefan Roeseae695b12013-04-15 21:14:12 +000034#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
35#else
36#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
37#endif
Marek Vasut0d4e8502011-11-08 23:18:16 +000038#define MXS_NAND_METADATA_SIZE 10
Jörg Krause1fbdb702015-04-15 09:27:22 +020039#define MXS_NAND_BITS_PER_ECC_LEVEL 13
Marek Vasut0d4e8502011-11-08 23:18:16 +000040#define MXS_NAND_COMMAND_BUFFER_SIZE 32
41
42#define MXS_NAND_BCH_TIMEOUT 10000
43
44struct mxs_nand_info {
45 int cur_chip;
46
47 uint32_t cmd_queue_len;
Marek Vasut6b9408e2012-03-15 18:33:19 +000048 uint32_t data_buf_size;
Marek Vasut0d4e8502011-11-08 23:18:16 +000049
50 uint8_t *cmd_buf;
51 uint8_t *data_buf;
52 uint8_t *oob_buf;
53
54 uint8_t marking_block_bad;
55 uint8_t raw_oob_mode;
56
57 /* Functions with altered behaviour */
58 int (*hooked_read_oob)(struct mtd_info *mtd,
59 loff_t from, struct mtd_oob_ops *ops);
60 int (*hooked_write_oob)(struct mtd_info *mtd,
61 loff_t to, struct mtd_oob_ops *ops);
62 int (*hooked_block_markbad)(struct mtd_info *mtd,
63 loff_t ofs);
64
65 /* DMA descriptors */
66 struct mxs_dma_desc **desc;
67 uint32_t desc_index;
68};
69
70struct nand_ecclayout fake_ecc_layout;
Peng Fan63b29d82015-07-21 16:15:19 +080071static int chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE;
72static int galois_field = 13;
Marek Vasut0d4e8502011-11-08 23:18:16 +000073
Marek Vasut6b9408e2012-03-15 18:33:19 +000074/*
75 * Cache management functions
76 */
77#ifndef CONFIG_SYS_DCACHE_OFF
78static void mxs_nand_flush_data_buf(struct mxs_nand_info *info)
79{
80 uint32_t addr = (uint32_t)info->data_buf;
81
82 flush_dcache_range(addr, addr + info->data_buf_size);
83}
84
85static void mxs_nand_inval_data_buf(struct mxs_nand_info *info)
86{
87 uint32_t addr = (uint32_t)info->data_buf;
88
89 invalidate_dcache_range(addr, addr + info->data_buf_size);
90}
91
92static void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info)
93{
94 uint32_t addr = (uint32_t)info->cmd_buf;
95
96 flush_dcache_range(addr, addr + MXS_NAND_COMMAND_BUFFER_SIZE);
97}
98#else
99static inline void mxs_nand_flush_data_buf(struct mxs_nand_info *info) {}
100static inline void mxs_nand_inval_data_buf(struct mxs_nand_info *info) {}
101static inline void mxs_nand_flush_cmd_buf(struct mxs_nand_info *info) {}
102#endif
103
Marek Vasut0d4e8502011-11-08 23:18:16 +0000104static struct mxs_dma_desc *mxs_nand_get_dma_desc(struct mxs_nand_info *info)
105{
106 struct mxs_dma_desc *desc;
107
108 if (info->desc_index >= MXS_NAND_DMA_DESCRIPTOR_COUNT) {
109 printf("MXS NAND: Too many DMA descriptors requested\n");
110 return NULL;
111 }
112
113 desc = info->desc[info->desc_index];
114 info->desc_index++;
115
116 return desc;
117}
118
119static void mxs_nand_return_dma_descs(struct mxs_nand_info *info)
120{
121 int i;
122 struct mxs_dma_desc *desc;
123
124 for (i = 0; i < info->desc_index; i++) {
125 desc = info->desc[i];
126 memset(desc, 0, sizeof(struct mxs_dma_desc));
127 desc->address = (dma_addr_t)desc;
128 }
129
130 info->desc_index = 0;
131}
132
133static uint32_t mxs_nand_ecc_chunk_cnt(uint32_t page_data_size)
134{
Peng Fan63b29d82015-07-21 16:15:19 +0800135 return page_data_size / chunk_data_size;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000136}
137
138static uint32_t mxs_nand_ecc_size_in_bits(uint32_t ecc_strength)
139{
Peng Fan63b29d82015-07-21 16:15:19 +0800140 return ecc_strength * galois_field;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000141}
142
143static uint32_t mxs_nand_aux_status_offset(void)
144{
145 return (MXS_NAND_METADATA_SIZE + 0x3) & ~0x3;
146}
147
148static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
149 uint32_t page_oob_size)
150{
Peng Fanbd38da12015-04-15 09:27:21 +0200151 int ecc_strength;
Peng Fan168617c2015-09-07 16:12:11 +0800152 int max_ecc_strength_supported;
153
154 /* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
Peng Fan9aa550d2016-05-23 18:36:02 +0800155 if (is_mx6sx() || is_mx7())
Peng Fan168617c2015-09-07 16:12:11 +0800156 max_ecc_strength_supported = 62;
157 else
158 max_ecc_strength_supported = 40;
Marek Vasutf9cfe172014-09-25 21:13:36 +0200159
Peng Fanbd38da12015-04-15 09:27:21 +0200160 /*
161 * Determine the ECC layout with the formula:
162 * ECC bits per chunk = (total page spare data bits) /
163 * (bits per ECC level) / (chunks per page)
164 * where:
165 * total page spare data bits =
166 * (page oob size - meta data size) * (bits per byte)
167 */
168 ecc_strength = ((page_oob_size - MXS_NAND_METADATA_SIZE) * 8)
Peng Fan63b29d82015-07-21 16:15:19 +0800169 / (galois_field *
170 mxs_nand_ecc_chunk_cnt(page_data_size));
Marek Vasut0d4e8502011-11-08 23:18:16 +0000171
Peng Fan168617c2015-09-07 16:12:11 +0800172 return min(round_down(ecc_strength, 2), max_ecc_strength_supported);
Marek Vasut0d4e8502011-11-08 23:18:16 +0000173}
174
175static inline uint32_t mxs_nand_get_mark_offset(uint32_t page_data_size,
176 uint32_t ecc_strength)
177{
178 uint32_t chunk_data_size_in_bits;
179 uint32_t chunk_ecc_size_in_bits;
180 uint32_t chunk_total_size_in_bits;
181 uint32_t block_mark_chunk_number;
182 uint32_t block_mark_chunk_bit_offset;
183 uint32_t block_mark_bit_offset;
184
Peng Fan63b29d82015-07-21 16:15:19 +0800185 chunk_data_size_in_bits = chunk_data_size * 8;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000186 chunk_ecc_size_in_bits = mxs_nand_ecc_size_in_bits(ecc_strength);
187
188 chunk_total_size_in_bits =
189 chunk_data_size_in_bits + chunk_ecc_size_in_bits;
190
191 /* Compute the bit offset of the block mark within the physical page. */
192 block_mark_bit_offset = page_data_size * 8;
193
194 /* Subtract the metadata bits. */
195 block_mark_bit_offset -= MXS_NAND_METADATA_SIZE * 8;
196
197 /*
198 * Compute the chunk number (starting at zero) in which the block mark
199 * appears.
200 */
201 block_mark_chunk_number =
202 block_mark_bit_offset / chunk_total_size_in_bits;
203
204 /*
205 * Compute the bit offset of the block mark within its chunk, and
206 * validate it.
207 */
208 block_mark_chunk_bit_offset = block_mark_bit_offset -
209 (block_mark_chunk_number * chunk_total_size_in_bits);
210
211 if (block_mark_chunk_bit_offset > chunk_data_size_in_bits)
212 return 1;
213
214 /*
215 * Now that we know the chunk number in which the block mark appears,
216 * we can subtract all the ECC bits that appear before it.
217 */
218 block_mark_bit_offset -=
219 block_mark_chunk_number * chunk_ecc_size_in_bits;
220
221 return block_mark_bit_offset;
222}
223
224static uint32_t mxs_nand_mark_byte_offset(struct mtd_info *mtd)
225{
226 uint32_t ecc_strength;
227 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
228 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) >> 3;
229}
230
231static uint32_t mxs_nand_mark_bit_offset(struct mtd_info *mtd)
232{
233 uint32_t ecc_strength;
234 ecc_strength = mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize);
235 return mxs_nand_get_mark_offset(mtd->writesize, ecc_strength) & 0x7;
236}
237
238/*
239 * Wait for BCH complete IRQ and clear the IRQ
240 */
241static int mxs_nand_wait_for_bch_complete(void)
242{
Otavio Salvador9c471142012-08-05 09:05:31 +0000243 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000244 int timeout = MXS_NAND_BCH_TIMEOUT;
245 int ret;
246
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +0000247 ret = mxs_wait_mask_set(&bch_regs->hw_bch_ctrl_reg,
Marek Vasut0d4e8502011-11-08 23:18:16 +0000248 BCH_CTRL_COMPLETE_IRQ, timeout);
249
250 writel(BCH_CTRL_COMPLETE_IRQ, &bch_regs->hw_bch_ctrl_clr);
251
252 return ret;
253}
254
255/*
256 * This is the function that we install in the cmd_ctrl function pointer of the
257 * owning struct nand_chip. The only functions in the reference implementation
258 * that use these functions pointers are cmdfunc and select_chip.
259 *
260 * In this driver, we implement our own select_chip, so this function will only
261 * be called by the reference implementation's cmdfunc. For this reason, we can
262 * ignore the chip enable bit and concentrate only on sending bytes to the NAND
263 * Flash.
264 */
265static void mxs_nand_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl)
266{
267 struct nand_chip *nand = mtd->priv;
268 struct mxs_nand_info *nand_info = nand->priv;
269 struct mxs_dma_desc *d;
270 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
271 int ret;
272
273 /*
274 * If this condition is true, something is _VERY_ wrong in MTD
275 * subsystem!
276 */
277 if (nand_info->cmd_queue_len == MXS_NAND_COMMAND_BUFFER_SIZE) {
278 printf("MXS NAND: Command queue too long\n");
279 return;
280 }
281
282 /*
283 * Every operation begins with a command byte and a series of zero or
284 * more address bytes. These are distinguished by either the Address
285 * Latch Enable (ALE) or Command Latch Enable (CLE) signals being
286 * asserted. When MTD is ready to execute the command, it will
287 * deasert both latch enables.
288 *
289 * Rather than run a separate DMA operation for every single byte, we
290 * queue them up and run a single DMA operation for the entire series
291 * of command and data bytes.
292 */
293 if (ctrl & (NAND_ALE | NAND_CLE)) {
294 if (data != NAND_CMD_NONE)
295 nand_info->cmd_buf[nand_info->cmd_queue_len++] = data;
296 return;
297 }
298
299 /*
300 * If control arrives here, MTD has deasserted both the ALE and CLE,
301 * which means it's ready to run an operation. Check if we have any
302 * bytes to send.
303 */
304 if (nand_info->cmd_queue_len == 0)
305 return;
306
307 /* Compile the DMA descriptor -- a descriptor that sends command. */
308 d = mxs_nand_get_dma_desc(nand_info);
309 d->cmd.data =
310 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
311 MXS_DMA_DESC_CHAIN | MXS_DMA_DESC_DEC_SEM |
312 MXS_DMA_DESC_WAIT4END | (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
313 (nand_info->cmd_queue_len << MXS_DMA_DESC_BYTES_OFFSET);
314
315 d->cmd.address = (dma_addr_t)nand_info->cmd_buf;
316
317 d->cmd.pio_words[0] =
318 GPMI_CTRL0_COMMAND_MODE_WRITE |
319 GPMI_CTRL0_WORD_LENGTH |
320 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
321 GPMI_CTRL0_ADDRESS_NAND_CLE |
322 GPMI_CTRL0_ADDRESS_INCREMENT |
323 nand_info->cmd_queue_len;
324
325 mxs_dma_desc_append(channel, d);
326
Marek Vasut6b9408e2012-03-15 18:33:19 +0000327 /* Flush caches */
328 mxs_nand_flush_cmd_buf(nand_info);
329
Marek Vasut0d4e8502011-11-08 23:18:16 +0000330 /* Execute the DMA chain. */
331 ret = mxs_dma_go(channel);
332 if (ret)
333 printf("MXS NAND: Error sending command\n");
334
335 mxs_nand_return_dma_descs(nand_info);
336
337 /* Reset the command queue. */
338 nand_info->cmd_queue_len = 0;
339}
340
341/*
342 * Test if the NAND flash is ready.
343 */
344static int mxs_nand_device_ready(struct mtd_info *mtd)
345{
346 struct nand_chip *chip = mtd->priv;
347 struct mxs_nand_info *nand_info = chip->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000348 struct mxs_gpmi_regs *gpmi_regs =
349 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000350 uint32_t tmp;
351
352 tmp = readl(&gpmi_regs->hw_gpmi_stat);
353 tmp >>= (GPMI_STAT_READY_BUSY_OFFSET + nand_info->cur_chip);
354
355 return tmp & 1;
356}
357
358/*
359 * Select the NAND chip.
360 */
361static void mxs_nand_select_chip(struct mtd_info *mtd, int chip)
362{
363 struct nand_chip *nand = mtd->priv;
364 struct mxs_nand_info *nand_info = nand->priv;
365
366 nand_info->cur_chip = chip;
367}
368
369/*
370 * Handle block mark swapping.
371 *
372 * Note that, when this function is called, it doesn't know whether it's
373 * swapping the block mark, or swapping it *back* -- but it doesn't matter
374 * because the the operation is the same.
375 */
376static void mxs_nand_swap_block_mark(struct mtd_info *mtd,
377 uint8_t *data_buf, uint8_t *oob_buf)
378{
379 uint32_t bit_offset;
380 uint32_t buf_offset;
381
382 uint32_t src;
383 uint32_t dst;
384
385 bit_offset = mxs_nand_mark_bit_offset(mtd);
386 buf_offset = mxs_nand_mark_byte_offset(mtd);
387
388 /*
389 * Get the byte from the data area that overlays the block mark. Since
390 * the ECC engine applies its own view to the bits in the page, the
391 * physical block mark won't (in general) appear on a byte boundary in
392 * the data.
393 */
394 src = data_buf[buf_offset] >> bit_offset;
395 src |= data_buf[buf_offset + 1] << (8 - bit_offset);
396
397 dst = oob_buf[0];
398
399 oob_buf[0] = src;
400
401 data_buf[buf_offset] &= ~(0xff << bit_offset);
402 data_buf[buf_offset + 1] &= 0xff << bit_offset;
403
404 data_buf[buf_offset] |= dst << bit_offset;
405 data_buf[buf_offset + 1] |= dst >> (8 - bit_offset);
406}
407
408/*
409 * Read data from NAND.
410 */
411static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
412{
413 struct nand_chip *nand = mtd->priv;
414 struct mxs_nand_info *nand_info = nand->priv;
415 struct mxs_dma_desc *d;
416 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
417 int ret;
418
419 if (length > NAND_MAX_PAGESIZE) {
420 printf("MXS NAND: DMA buffer too big\n");
421 return;
422 }
423
424 if (!buf) {
425 printf("MXS NAND: DMA buffer is NULL\n");
426 return;
427 }
428
429 /* Compile the DMA descriptor - a descriptor that reads data. */
430 d = mxs_nand_get_dma_desc(nand_info);
431 d->cmd.data =
432 MXS_DMA_DESC_COMMAND_DMA_WRITE | MXS_DMA_DESC_IRQ |
433 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
434 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
435 (length << MXS_DMA_DESC_BYTES_OFFSET);
436
437 d->cmd.address = (dma_addr_t)nand_info->data_buf;
438
439 d->cmd.pio_words[0] =
440 GPMI_CTRL0_COMMAND_MODE_READ |
441 GPMI_CTRL0_WORD_LENGTH |
442 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
443 GPMI_CTRL0_ADDRESS_NAND_DATA |
444 length;
445
446 mxs_dma_desc_append(channel, d);
447
448 /*
449 * A DMA descriptor that waits for the command to end and the chip to
450 * become ready.
451 *
452 * I think we actually should *not* be waiting for the chip to become
453 * ready because, after all, we don't care. I think the original code
454 * did that and no one has re-thought it yet.
455 */
456 d = mxs_nand_get_dma_desc(nand_info);
457 d->cmd.data =
458 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
459 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_DEC_SEM |
Luca Ellero5263a022014-12-16 15:36:14 +0100460 MXS_DMA_DESC_WAIT4END | (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
Marek Vasut0d4e8502011-11-08 23:18:16 +0000461
462 d->cmd.address = 0;
463
464 d->cmd.pio_words[0] =
465 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
466 GPMI_CTRL0_WORD_LENGTH |
467 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
468 GPMI_CTRL0_ADDRESS_NAND_DATA;
469
470 mxs_dma_desc_append(channel, d);
471
Peng Fanecfb8762015-07-21 16:15:21 +0800472 /* Invalidate caches */
473 mxs_nand_inval_data_buf(nand_info);
474
Marek Vasut0d4e8502011-11-08 23:18:16 +0000475 /* Execute the DMA chain. */
476 ret = mxs_dma_go(channel);
477 if (ret) {
478 printf("MXS NAND: DMA read error\n");
479 goto rtn;
480 }
481
Marek Vasut6b9408e2012-03-15 18:33:19 +0000482 /* Invalidate caches */
483 mxs_nand_inval_data_buf(nand_info);
484
Marek Vasut0d4e8502011-11-08 23:18:16 +0000485 memcpy(buf, nand_info->data_buf, length);
486
487rtn:
488 mxs_nand_return_dma_descs(nand_info);
489}
490
491/*
492 * Write data to NAND.
493 */
494static void mxs_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
495 int length)
496{
497 struct nand_chip *nand = mtd->priv;
498 struct mxs_nand_info *nand_info = nand->priv;
499 struct mxs_dma_desc *d;
500 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
501 int ret;
502
503 if (length > NAND_MAX_PAGESIZE) {
504 printf("MXS NAND: DMA buffer too big\n");
505 return;
506 }
507
508 if (!buf) {
509 printf("MXS NAND: DMA buffer is NULL\n");
510 return;
511 }
512
513 memcpy(nand_info->data_buf, buf, length);
514
515 /* Compile the DMA descriptor - a descriptor that writes data. */
516 d = mxs_nand_get_dma_desc(nand_info);
517 d->cmd.data =
518 MXS_DMA_DESC_COMMAND_DMA_READ | MXS_DMA_DESC_IRQ |
519 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
Luca Ellero88a2cbb2014-12-16 15:36:15 +0100520 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET) |
Marek Vasut0d4e8502011-11-08 23:18:16 +0000521 (length << MXS_DMA_DESC_BYTES_OFFSET);
522
523 d->cmd.address = (dma_addr_t)nand_info->data_buf;
524
525 d->cmd.pio_words[0] =
526 GPMI_CTRL0_COMMAND_MODE_WRITE |
527 GPMI_CTRL0_WORD_LENGTH |
528 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
529 GPMI_CTRL0_ADDRESS_NAND_DATA |
530 length;
531
532 mxs_dma_desc_append(channel, d);
533
Marek Vasut6b9408e2012-03-15 18:33:19 +0000534 /* Flush caches */
535 mxs_nand_flush_data_buf(nand_info);
536
Marek Vasut0d4e8502011-11-08 23:18:16 +0000537 /* Execute the DMA chain. */
538 ret = mxs_dma_go(channel);
539 if (ret)
540 printf("MXS NAND: DMA write error\n");
541
542 mxs_nand_return_dma_descs(nand_info);
543}
544
545/*
546 * Read a single byte from NAND.
547 */
548static uint8_t mxs_nand_read_byte(struct mtd_info *mtd)
549{
550 uint8_t buf;
551 mxs_nand_read_buf(mtd, &buf, 1);
552 return buf;
553}
554
555/*
556 * Read a page from NAND.
557 */
558static int mxs_nand_ecc_read_page(struct mtd_info *mtd, struct nand_chip *nand,
Sergey Lapindfe64e22013-01-14 03:46:50 +0000559 uint8_t *buf, int oob_required,
560 int page)
Marek Vasut0d4e8502011-11-08 23:18:16 +0000561{
562 struct mxs_nand_info *nand_info = nand->priv;
563 struct mxs_dma_desc *d;
564 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
565 uint32_t corrected = 0, failed = 0;
566 uint8_t *status;
567 int i, ret;
568
569 /* Compile the DMA descriptor - wait for ready. */
570 d = mxs_nand_get_dma_desc(nand_info);
571 d->cmd.data =
572 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
573 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
574 (1 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
575
576 d->cmd.address = 0;
577
578 d->cmd.pio_words[0] =
579 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
580 GPMI_CTRL0_WORD_LENGTH |
581 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
582 GPMI_CTRL0_ADDRESS_NAND_DATA;
583
584 mxs_dma_desc_append(channel, d);
585
586 /* Compile the DMA descriptor - enable the BCH block and read. */
587 d = mxs_nand_get_dma_desc(nand_info);
588 d->cmd.data =
589 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
590 MXS_DMA_DESC_WAIT4END | (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
591
592 d->cmd.address = 0;
593
594 d->cmd.pio_words[0] =
595 GPMI_CTRL0_COMMAND_MODE_READ |
596 GPMI_CTRL0_WORD_LENGTH |
597 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
598 GPMI_CTRL0_ADDRESS_NAND_DATA |
599 (mtd->writesize + mtd->oobsize);
600 d->cmd.pio_words[1] = 0;
601 d->cmd.pio_words[2] =
602 GPMI_ECCCTRL_ENABLE_ECC |
603 GPMI_ECCCTRL_ECC_CMD_DECODE |
604 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
605 d->cmd.pio_words[3] = mtd->writesize + mtd->oobsize;
606 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
607 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
608
609 mxs_dma_desc_append(channel, d);
610
611 /* Compile the DMA descriptor - disable the BCH block. */
612 d = mxs_nand_get_dma_desc(nand_info);
613 d->cmd.data =
614 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_CHAIN |
615 MXS_DMA_DESC_NAND_WAIT_4_READY | MXS_DMA_DESC_WAIT4END |
616 (3 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
617
618 d->cmd.address = 0;
619
620 d->cmd.pio_words[0] =
621 GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY |
622 GPMI_CTRL0_WORD_LENGTH |
623 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
624 GPMI_CTRL0_ADDRESS_NAND_DATA |
625 (mtd->writesize + mtd->oobsize);
626 d->cmd.pio_words[1] = 0;
627 d->cmd.pio_words[2] = 0;
628
629 mxs_dma_desc_append(channel, d);
630
631 /* Compile the DMA descriptor - deassert the NAND lock and interrupt. */
632 d = mxs_nand_get_dma_desc(nand_info);
633 d->cmd.data =
634 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
635 MXS_DMA_DESC_DEC_SEM;
636
637 d->cmd.address = 0;
638
639 mxs_dma_desc_append(channel, d);
640
Peng Fanecfb8762015-07-21 16:15:21 +0800641 /* Invalidate caches */
642 mxs_nand_inval_data_buf(nand_info);
643
Marek Vasut0d4e8502011-11-08 23:18:16 +0000644 /* Execute the DMA chain. */
645 ret = mxs_dma_go(channel);
646 if (ret) {
647 printf("MXS NAND: DMA read error\n");
648 goto rtn;
649 }
650
651 ret = mxs_nand_wait_for_bch_complete();
652 if (ret) {
653 printf("MXS NAND: BCH read timeout\n");
654 goto rtn;
655 }
656
Marek Vasut6b9408e2012-03-15 18:33:19 +0000657 /* Invalidate caches */
658 mxs_nand_inval_data_buf(nand_info);
659
Marek Vasut0d4e8502011-11-08 23:18:16 +0000660 /* Read DMA completed, now do the mark swapping. */
661 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
662
663 /* Loop over status bytes, accumulating ECC status. */
664 status = nand_info->oob_buf + mxs_nand_aux_status_offset();
665 for (i = 0; i < mxs_nand_ecc_chunk_cnt(mtd->writesize); i++) {
666 if (status[i] == 0x00)
667 continue;
668
669 if (status[i] == 0xff)
670 continue;
671
672 if (status[i] == 0xfe) {
673 failed++;
674 continue;
675 }
676
677 corrected += status[i];
678 }
679
680 /* Propagate ECC status to the owning MTD. */
681 mtd->ecc_stats.failed += failed;
682 mtd->ecc_stats.corrected += corrected;
683
684 /*
685 * It's time to deliver the OOB bytes. See mxs_nand_ecc_read_oob() for
686 * details about our policy for delivering the OOB.
687 *
688 * We fill the caller's buffer with set bits, and then copy the block
689 * mark to the caller's buffer. Note that, if block mark swapping was
690 * necessary, it has already been done, so we can rely on the first
691 * byte of the auxiliary buffer to contain the block mark.
692 */
693 memset(nand->oob_poi, 0xff, mtd->oobsize);
694
695 nand->oob_poi[0] = nand_info->oob_buf[0];
696
697 memcpy(buf, nand_info->data_buf, mtd->writesize);
698
699rtn:
700 mxs_nand_return_dma_descs(nand_info);
701
702 return ret;
703}
704
705/*
706 * Write a page to NAND.
707 */
Sergey Lapindfe64e22013-01-14 03:46:50 +0000708static int mxs_nand_ecc_write_page(struct mtd_info *mtd,
709 struct nand_chip *nand, const uint8_t *buf,
710 int oob_required)
Marek Vasut0d4e8502011-11-08 23:18:16 +0000711{
712 struct mxs_nand_info *nand_info = nand->priv;
713 struct mxs_dma_desc *d;
714 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
715 int ret;
716
717 memcpy(nand_info->data_buf, buf, mtd->writesize);
718 memcpy(nand_info->oob_buf, nand->oob_poi, mtd->oobsize);
719
720 /* Handle block mark swapping. */
721 mxs_nand_swap_block_mark(mtd, nand_info->data_buf, nand_info->oob_buf);
722
723 /* Compile the DMA descriptor - write data. */
724 d = mxs_nand_get_dma_desc(nand_info);
725 d->cmd.data =
726 MXS_DMA_DESC_COMMAND_NO_DMAXFER | MXS_DMA_DESC_IRQ |
727 MXS_DMA_DESC_DEC_SEM | MXS_DMA_DESC_WAIT4END |
728 (6 << MXS_DMA_DESC_PIO_WORDS_OFFSET);
729
730 d->cmd.address = 0;
731
732 d->cmd.pio_words[0] =
733 GPMI_CTRL0_COMMAND_MODE_WRITE |
734 GPMI_CTRL0_WORD_LENGTH |
735 (nand_info->cur_chip << GPMI_CTRL0_CS_OFFSET) |
736 GPMI_CTRL0_ADDRESS_NAND_DATA;
737 d->cmd.pio_words[1] = 0;
738 d->cmd.pio_words[2] =
739 GPMI_ECCCTRL_ENABLE_ECC |
740 GPMI_ECCCTRL_ECC_CMD_ENCODE |
741 GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE;
742 d->cmd.pio_words[3] = (mtd->writesize + mtd->oobsize);
743 d->cmd.pio_words[4] = (dma_addr_t)nand_info->data_buf;
744 d->cmd.pio_words[5] = (dma_addr_t)nand_info->oob_buf;
745
746 mxs_dma_desc_append(channel, d);
747
Marek Vasut6b9408e2012-03-15 18:33:19 +0000748 /* Flush caches */
749 mxs_nand_flush_data_buf(nand_info);
750
Marek Vasut0d4e8502011-11-08 23:18:16 +0000751 /* Execute the DMA chain. */
752 ret = mxs_dma_go(channel);
753 if (ret) {
754 printf("MXS NAND: DMA write error\n");
755 goto rtn;
756 }
757
758 ret = mxs_nand_wait_for_bch_complete();
759 if (ret) {
760 printf("MXS NAND: BCH write timeout\n");
761 goto rtn;
762 }
763
764rtn:
765 mxs_nand_return_dma_descs(nand_info);
Sergey Lapindfe64e22013-01-14 03:46:50 +0000766 return 0;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000767}
768
769/*
770 * Read OOB from NAND.
771 *
772 * This function is a veneer that replaces the function originally installed by
773 * the NAND Flash MTD code.
774 */
775static int mxs_nand_hook_read_oob(struct mtd_info *mtd, loff_t from,
776 struct mtd_oob_ops *ops)
777{
778 struct nand_chip *chip = mtd->priv;
779 struct mxs_nand_info *nand_info = chip->priv;
780 int ret;
781
Sergey Lapindfe64e22013-01-14 03:46:50 +0000782 if (ops->mode == MTD_OPS_RAW)
Marek Vasut0d4e8502011-11-08 23:18:16 +0000783 nand_info->raw_oob_mode = 1;
784 else
785 nand_info->raw_oob_mode = 0;
786
787 ret = nand_info->hooked_read_oob(mtd, from, ops);
788
789 nand_info->raw_oob_mode = 0;
790
791 return ret;
792}
793
794/*
795 * Write OOB to NAND.
796 *
797 * This function is a veneer that replaces the function originally installed by
798 * the NAND Flash MTD code.
799 */
800static int mxs_nand_hook_write_oob(struct mtd_info *mtd, loff_t to,
801 struct mtd_oob_ops *ops)
802{
803 struct nand_chip *chip = mtd->priv;
804 struct mxs_nand_info *nand_info = chip->priv;
805 int ret;
806
Sergey Lapindfe64e22013-01-14 03:46:50 +0000807 if (ops->mode == MTD_OPS_RAW)
Marek Vasut0d4e8502011-11-08 23:18:16 +0000808 nand_info->raw_oob_mode = 1;
809 else
810 nand_info->raw_oob_mode = 0;
811
812 ret = nand_info->hooked_write_oob(mtd, to, ops);
813
814 nand_info->raw_oob_mode = 0;
815
816 return ret;
817}
818
819/*
820 * Mark a block bad in NAND.
821 *
822 * This function is a veneer that replaces the function originally installed by
823 * the NAND Flash MTD code.
824 */
825static int mxs_nand_hook_block_markbad(struct mtd_info *mtd, loff_t ofs)
826{
827 struct nand_chip *chip = mtd->priv;
828 struct mxs_nand_info *nand_info = chip->priv;
829 int ret;
830
831 nand_info->marking_block_bad = 1;
832
833 ret = nand_info->hooked_block_markbad(mtd, ofs);
834
835 nand_info->marking_block_bad = 0;
836
837 return ret;
838}
839
840/*
841 * There are several places in this driver where we have to handle the OOB and
842 * block marks. This is the function where things are the most complicated, so
843 * this is where we try to explain it all. All the other places refer back to
844 * here.
845 *
846 * These are the rules, in order of decreasing importance:
847 *
848 * 1) Nothing the caller does can be allowed to imperil the block mark, so all
849 * write operations take measures to protect it.
850 *
851 * 2) In read operations, the first byte of the OOB we return must reflect the
852 * true state of the block mark, no matter where that block mark appears in
853 * the physical page.
854 *
855 * 3) ECC-based read operations return an OOB full of set bits (since we never
856 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
857 * return).
858 *
859 * 4) "Raw" read operations return a direct view of the physical bytes in the
860 * page, using the conventional definition of which bytes are data and which
861 * are OOB. This gives the caller a way to see the actual, physical bytes
862 * in the page, without the distortions applied by our ECC engine.
863 *
864 * What we do for this specific read operation depends on whether we're doing
865 * "raw" read, or an ECC-based read.
866 *
867 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
868 * easy. When reading a page, for example, the NAND Flash MTD code calls our
869 * ecc.read_page or ecc.read_page_raw function. Thus, the fact that MTD wants an
870 * ECC-based or raw view of the page is implicit in which function it calls
871 * (there is a similar pair of ECC-based/raw functions for writing).
872 *
873 * Since MTD assumes the OOB is not covered by ECC, there is no pair of
874 * ECC-based/raw functions for reading or or writing the OOB. The fact that the
875 * caller wants an ECC-based or raw view of the page is not propagated down to
876 * this driver.
877 *
878 * Since our OOB *is* covered by ECC, we need this information. So, we hook the
879 * ecc.read_oob and ecc.write_oob function pointers in the owning
880 * struct mtd_info with our own functions. These hook functions set the
881 * raw_oob_mode field so that, when control finally arrives here, we'll know
882 * what to do.
883 */
884static int mxs_nand_ecc_read_oob(struct mtd_info *mtd, struct nand_chip *nand,
Sergey Lapindfe64e22013-01-14 03:46:50 +0000885 int page)
Marek Vasut0d4e8502011-11-08 23:18:16 +0000886{
887 struct mxs_nand_info *nand_info = nand->priv;
888
889 /*
890 * First, fill in the OOB buffer. If we're doing a raw read, we need to
891 * get the bytes from the physical page. If we're not doing a raw read,
892 * we need to fill the buffer with set bits.
893 */
894 if (nand_info->raw_oob_mode) {
895 /*
896 * If control arrives here, we're doing a "raw" read. Send the
897 * command to read the conventional OOB and read it.
898 */
899 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
900 nand->read_buf(mtd, nand->oob_poi, mtd->oobsize);
901 } else {
902 /*
903 * If control arrives here, we're not doing a "raw" read. Fill
904 * the OOB buffer with set bits and correct the block mark.
905 */
906 memset(nand->oob_poi, 0xff, mtd->oobsize);
907
908 nand->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
909 mxs_nand_read_buf(mtd, nand->oob_poi, 1);
910 }
911
912 return 0;
913
914}
915
916/*
917 * Write OOB data to NAND.
918 */
919static int mxs_nand_ecc_write_oob(struct mtd_info *mtd, struct nand_chip *nand,
920 int page)
921{
922 struct mxs_nand_info *nand_info = nand->priv;
923 uint8_t block_mark = 0;
924
925 /*
926 * There are fundamental incompatibilities between the i.MX GPMI NFC and
927 * the NAND Flash MTD model that make it essentially impossible to write
928 * the out-of-band bytes.
929 *
930 * We permit *ONE* exception. If the *intent* of writing the OOB is to
931 * mark a block bad, we can do that.
932 */
933
934 if (!nand_info->marking_block_bad) {
935 printf("NXS NAND: Writing OOB isn't supported\n");
936 return -EIO;
937 }
938
939 /* Write the block mark. */
940 nand->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
941 nand->write_buf(mtd, &block_mark, 1);
942 nand->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
943
944 /* Check if it worked. */
945 if (nand->waitfunc(mtd, nand) & NAND_STATUS_FAIL)
946 return -EIO;
947
948 return 0;
949}
950
951/*
952 * Claims all blocks are good.
953 *
954 * In principle, this function is *only* called when the NAND Flash MTD system
955 * isn't allowed to keep an in-memory bad block table, so it is forced to ask
956 * the driver for bad block information.
957 *
958 * In fact, we permit the NAND Flash MTD system to have an in-memory BBT, so
959 * this function is *only* called when we take it away.
960 *
961 * Thus, this function is only called when we want *all* blocks to look good,
962 * so it *always* return success.
963 */
964static int mxs_nand_block_bad(struct mtd_info *mtd, loff_t ofs, int getchip)
965{
966 return 0;
967}
968
969/*
970 * Nominally, the purpose of this function is to look for or create the bad
971 * block table. In fact, since the we call this function at the very end of
972 * the initialization process started by nand_scan(), and we doesn't have a
973 * more formal mechanism, we "hook" this function to continue init process.
974 *
975 * At this point, the physical NAND Flash chips have been identified and
976 * counted, so we know the physical geometry. This enables us to make some
977 * important configuration decisions.
978 *
979 * The return value of this function propogates directly back to this driver's
980 * call to nand_scan(). Anything other than zero will cause this driver to
981 * tear everything down and declare failure.
982 */
983static int mxs_nand_scan_bbt(struct mtd_info *mtd)
984{
985 struct nand_chip *nand = mtd->priv;
986 struct mxs_nand_info *nand_info = nand->priv;
Otavio Salvador9c471142012-08-05 09:05:31 +0000987 struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
Marek Vasut0d4e8502011-11-08 23:18:16 +0000988 uint32_t tmp;
989
Peng Fan63b29d82015-07-21 16:15:19 +0800990 if (mtd->oobsize > MXS_NAND_CHUNK_DATA_CHUNK_SIZE) {
991 galois_field = 14;
992 chunk_data_size = MXS_NAND_CHUNK_DATA_CHUNK_SIZE * 2;
993 }
994
995 if (mtd->oobsize > chunk_data_size) {
996 printf("Not support the NAND chips whose oob size is larger then %d bytes!\n", chunk_data_size);
997 return -EINVAL;
998 }
999
Marek Vasut0d4e8502011-11-08 23:18:16 +00001000 /* Configure BCH and set NFC geometry */
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +00001001 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
Marek Vasut0d4e8502011-11-08 23:18:16 +00001002
1003 /* Configure layout 0 */
1004 tmp = (mxs_nand_ecc_chunk_cnt(mtd->writesize) - 1)
1005 << BCH_FLASHLAYOUT0_NBLOCKS_OFFSET;
1006 tmp |= MXS_NAND_METADATA_SIZE << BCH_FLASHLAYOUT0_META_SIZE_OFFSET;
1007 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1008 << BCH_FLASHLAYOUT0_ECC0_OFFSET;
Peng Fan63b29d82015-07-21 16:15:19 +08001009 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1010 tmp |= (14 == galois_field ? 1 : 0) <<
1011 BCH_FLASHLAYOUT0_GF13_0_GF14_1_OFFSET;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001012 writel(tmp, &bch_regs->hw_bch_flash0layout0);
1013
1014 tmp = (mtd->writesize + mtd->oobsize)
1015 << BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET;
1016 tmp |= (mxs_nand_get_ecc_strength(mtd->writesize, mtd->oobsize) >> 1)
1017 << BCH_FLASHLAYOUT1_ECCN_OFFSET;
Peng Fan63b29d82015-07-21 16:15:19 +08001018 tmp |= chunk_data_size >> MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT;
1019 tmp |= (14 == galois_field ? 1 : 0) <<
1020 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001021 writel(tmp, &bch_regs->hw_bch_flash0layout1);
1022
1023 /* Set *all* chip selects to use layout 0 */
1024 writel(0, &bch_regs->hw_bch_layoutselect);
1025
1026 /* Enable BCH complete interrupt */
1027 writel(BCH_CTRL_COMPLETE_IRQ_EN, &bch_regs->hw_bch_ctrl_set);
1028
1029 /* Hook some operations at the MTD level. */
Sergey Lapindfe64e22013-01-14 03:46:50 +00001030 if (mtd->_read_oob != mxs_nand_hook_read_oob) {
1031 nand_info->hooked_read_oob = mtd->_read_oob;
1032 mtd->_read_oob = mxs_nand_hook_read_oob;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001033 }
1034
Sergey Lapindfe64e22013-01-14 03:46:50 +00001035 if (mtd->_write_oob != mxs_nand_hook_write_oob) {
1036 nand_info->hooked_write_oob = mtd->_write_oob;
1037 mtd->_write_oob = mxs_nand_hook_write_oob;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001038 }
1039
Sergey Lapindfe64e22013-01-14 03:46:50 +00001040 if (mtd->_block_markbad != mxs_nand_hook_block_markbad) {
1041 nand_info->hooked_block_markbad = mtd->_block_markbad;
1042 mtd->_block_markbad = mxs_nand_hook_block_markbad;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001043 }
1044
1045 /* We use the reference implementation for bad block management. */
1046 return nand_default_bbt(mtd);
1047}
1048
1049/*
1050 * Allocate DMA buffers
1051 */
1052int mxs_nand_alloc_buffers(struct mxs_nand_info *nand_info)
1053{
1054 uint8_t *buf;
1055 const int size = NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE;
1056
Marek Vasut6b9408e2012-03-15 18:33:19 +00001057 nand_info->data_buf_size = roundup(size, MXS_DMA_ALIGNMENT);
1058
Marek Vasut0d4e8502011-11-08 23:18:16 +00001059 /* DMA buffers */
Marek Vasut6b9408e2012-03-15 18:33:19 +00001060 buf = memalign(MXS_DMA_ALIGNMENT, nand_info->data_buf_size);
Marek Vasut0d4e8502011-11-08 23:18:16 +00001061 if (!buf) {
1062 printf("MXS NAND: Error allocating DMA buffers\n");
1063 return -ENOMEM;
1064 }
1065
Marek Vasut6b9408e2012-03-15 18:33:19 +00001066 memset(buf, 0, nand_info->data_buf_size);
Marek Vasut0d4e8502011-11-08 23:18:16 +00001067
1068 nand_info->data_buf = buf;
1069 nand_info->oob_buf = buf + NAND_MAX_PAGESIZE;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001070 /* Command buffers */
1071 nand_info->cmd_buf = memalign(MXS_DMA_ALIGNMENT,
1072 MXS_NAND_COMMAND_BUFFER_SIZE);
1073 if (!nand_info->cmd_buf) {
1074 free(buf);
1075 printf("MXS NAND: Error allocating command buffers\n");
1076 return -ENOMEM;
1077 }
1078 memset(nand_info->cmd_buf, 0, MXS_NAND_COMMAND_BUFFER_SIZE);
1079 nand_info->cmd_queue_len = 0;
1080
1081 return 0;
1082}
1083
1084/*
1085 * Initializes the NFC hardware.
1086 */
1087int mxs_nand_init(struct mxs_nand_info *info)
1088{
Otavio Salvador9c471142012-08-05 09:05:31 +00001089 struct mxs_gpmi_regs *gpmi_regs =
1090 (struct mxs_gpmi_regs *)MXS_GPMI_BASE;
Wolfram Sang0b38fff2012-12-05 10:48:47 +00001091 struct mxs_bch_regs *bch_regs =
1092 (struct mxs_bch_regs *)MXS_BCH_BASE;
Peng Fan549d7c02016-01-27 10:38:02 +08001093 int i = 0, j, ret = 0;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001094
1095 info->desc = malloc(sizeof(struct mxs_dma_desc *) *
1096 MXS_NAND_DMA_DESCRIPTOR_COUNT);
Peng Fan549d7c02016-01-27 10:38:02 +08001097 if (!info->desc) {
1098 ret = -ENOMEM;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001099 goto err1;
Peng Fan549d7c02016-01-27 10:38:02 +08001100 }
Marek Vasut0d4e8502011-11-08 23:18:16 +00001101
1102 /* Allocate the DMA descriptors. */
1103 for (i = 0; i < MXS_NAND_DMA_DESCRIPTOR_COUNT; i++) {
1104 info->desc[i] = mxs_dma_desc_alloc();
Peng Fan549d7c02016-01-27 10:38:02 +08001105 if (!info->desc[i]) {
1106 ret = -ENOMEM;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001107 goto err2;
Peng Fan549d7c02016-01-27 10:38:02 +08001108 }
Marek Vasut0d4e8502011-11-08 23:18:16 +00001109 }
1110
1111 /* Init the DMA controller. */
Marek Vasut96666a32012-04-08 17:34:46 +00001112 for (j = MXS_DMA_CHANNEL_AHB_APBH_GPMI0;
1113 j <= MXS_DMA_CHANNEL_AHB_APBH_GPMI7; j++) {
Peng Fan549d7c02016-01-27 10:38:02 +08001114 ret = mxs_dma_init_channel(j);
1115 if (ret)
Marek Vasut96666a32012-04-08 17:34:46 +00001116 goto err3;
1117 }
Marek Vasut0d4e8502011-11-08 23:18:16 +00001118
1119 /* Reset the GPMI block. */
Otavio Salvadorfa7a51c2012-08-13 09:53:12 +00001120 mxs_reset_block(&gpmi_regs->hw_gpmi_ctrl0_reg);
Wolfram Sang0b38fff2012-12-05 10:48:47 +00001121 mxs_reset_block(&bch_regs->hw_bch_ctrl_reg);
Marek Vasut0d4e8502011-11-08 23:18:16 +00001122
1123 /*
1124 * Choose NAND mode, set IRQ polarity, disable write protection and
1125 * select BCH ECC.
1126 */
1127 clrsetbits_le32(&gpmi_regs->hw_gpmi_ctrl1,
1128 GPMI_CTRL1_GPMI_MODE,
1129 GPMI_CTRL1_ATA_IRQRDY_POLARITY | GPMI_CTRL1_DEV_RESET |
1130 GPMI_CTRL1_BCH_MODE);
1131
1132 return 0;
1133
Marek Vasut96666a32012-04-08 17:34:46 +00001134err3:
Peng Fan549d7c02016-01-27 10:38:02 +08001135 for (--j; j >= MXS_DMA_CHANNEL_AHB_APBH_GPMI0; j--)
Marek Vasut96666a32012-04-08 17:34:46 +00001136 mxs_dma_release(j);
Marek Vasut0d4e8502011-11-08 23:18:16 +00001137err2:
Marek Vasut0d4e8502011-11-08 23:18:16 +00001138 for (--i; i >= 0; i--)
1139 mxs_dma_desc_free(info->desc[i]);
Peng Fan549d7c02016-01-27 10:38:02 +08001140 free(info->desc);
1141err1:
1142 if (ret == -ENOMEM)
1143 printf("MXS NAND: Unable to allocate DMA descriptors\n");
1144 return ret;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001145}
1146
1147/*!
1148 * This function is called during the driver binding process.
1149 *
1150 * @param pdev the device structure used to store device specific
1151 * information that is used by the suspend, resume and
1152 * remove functions
1153 *
1154 * @return The function always returns 0.
1155 */
1156int board_nand_init(struct nand_chip *nand)
1157{
1158 struct mxs_nand_info *nand_info;
1159 int err;
1160
1161 nand_info = malloc(sizeof(struct mxs_nand_info));
1162 if (!nand_info) {
1163 printf("MXS NAND: Failed to allocate private data\n");
1164 return -ENOMEM;
1165 }
1166 memset(nand_info, 0, sizeof(struct mxs_nand_info));
1167
1168 err = mxs_nand_alloc_buffers(nand_info);
1169 if (err)
1170 goto err1;
1171
1172 err = mxs_nand_init(nand_info);
1173 if (err)
1174 goto err2;
1175
1176 memset(&fake_ecc_layout, 0, sizeof(fake_ecc_layout));
1177
1178 nand->priv = nand_info;
1179 nand->options |= NAND_NO_SUBPAGE_WRITE;
1180
1181 nand->cmd_ctrl = mxs_nand_cmd_ctrl;
1182
1183 nand->dev_ready = mxs_nand_device_ready;
1184 nand->select_chip = mxs_nand_select_chip;
1185 nand->block_bad = mxs_nand_block_bad;
1186 nand->scan_bbt = mxs_nand_scan_bbt;
1187
1188 nand->read_byte = mxs_nand_read_byte;
1189
1190 nand->read_buf = mxs_nand_read_buf;
1191 nand->write_buf = mxs_nand_write_buf;
1192
1193 nand->ecc.read_page = mxs_nand_ecc_read_page;
1194 nand->ecc.write_page = mxs_nand_ecc_write_page;
1195 nand->ecc.read_oob = mxs_nand_ecc_read_oob;
1196 nand->ecc.write_oob = mxs_nand_ecc_write_oob;
1197
1198 nand->ecc.layout = &fake_ecc_layout;
1199 nand->ecc.mode = NAND_ECC_HW;
1200 nand->ecc.bytes = 9;
1201 nand->ecc.size = 512;
Sergey Lapindfe64e22013-01-14 03:46:50 +00001202 nand->ecc.strength = 8;
Marek Vasut0d4e8502011-11-08 23:18:16 +00001203
1204 return 0;
1205
1206err2:
1207 free(nand_info->data_buf);
1208 free(nand_info->cmd_buf);
1209err1:
1210 free(nand_info);
1211 return err;
1212}