blob: 7ee1160e0d8ccc863cd05265af1f249c8d765f85 [file] [log] [blame]
Philip, Avinashb04601a2013-08-30 16:28:43 -04001/*
2 * (C) Copyright 2011-2013
3 * Texas Instruments, <www.ti.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <i2c.h>
10#include <power/tps65910.h>
11
12/*
13 * tps65910_set_i2c_control() - Set the TPS65910 to be controlled via the I2C
14 * interface.
15 * @return: 0 on success, not 0 on failure
16 */
17int tps65910_set_i2c_control(void)
18{
19 int ret;
20 uchar buf;
21
22 /* VDD1/2 voltage selection register access by control i/f */
23 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
24 &buf, 1);
25
26 if (ret)
27 return ret;
28
29 buf |= TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C;
30
31 return i2c_write(TPS65910_CTRL_I2C_ADDR, TPS65910_DEVCTRL_REG, 1,
32 &buf, 1);
33}
34
35/*
36 * tps65910_voltage_update() - Voltage switching for MPU frequency switching.
37 * @module: mpu - 0, core - 1
38 * @vddx_op_vol_sel: vdd voltage to set
39 * @return: 0 on success, not 0 on failure
40 */
41int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel)
42{
43 uchar buf;
44 unsigned int reg_offset;
45 int ret;
46
47 if (module == MPU)
48 reg_offset = TPS65910_VDD1_OP_REG;
49 else
50 reg_offset = TPS65910_VDD2_OP_REG;
51
52 /* Select VDDx OP */
53 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
54 if (ret)
55 return ret;
56
57 buf &= ~TPS65910_OP_REG_CMD_MASK;
58
59 ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
60 if (ret)
61 return ret;
62
63 /* Configure VDDx OP Voltage */
64 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
65 if (ret)
66 return ret;
67
68 buf &= ~TPS65910_OP_REG_SEL_MASK;
69 buf |= vddx_op_vol_sel;
70
71 ret = i2c_write(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
72 if (ret)
73 return ret;
74
75 ret = i2c_read(TPS65910_CTRL_I2C_ADDR, reg_offset, 1, &buf, 1);
76 if (ret)
77 return ret;
78
79 if ((buf & TPS65910_OP_REG_SEL_MASK) != vddx_op_vol_sel)
80 return 1;
81
82 return 0;
83}