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wdenkb4676a22003-12-07 19:24:00 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28#define MV_VERSION "v0.2.0"
29
30/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020031#define ERR_NONE 0
32#define ERR_ENV 1
33#define ERR_BOOTM_BADMAGIC 2
34#define ERR_BOOTM_BADCRC 3
35#define ERR_BOOTM_GUNZIP 4
wdenkb4676a22003-12-07 19:24:00 +000036#define ERR_BOOTP_TIMEOUT 5
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037#define ERR_DHCP 6
38#define ERR_TFTP 7
39#define ERR_NOLAN 8
40#define ERR_LANDRV 9
wdenkb4676a22003-12-07 19:24:00 +000041
42#define CONFIG_BOARD_TYPES 1
43#define MVBLUE_BOARD_BOX 1
44#define MVBLUE_BOARD_LYNX 2
45
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xFFF00000
47
wdenkb4676a22003-12-07 19:24:00 +000048#if 0
49#define ERR_LED(code) do { if (code) \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020050 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
51 else \
52 *(volatile char *)(0xff000003) = ( 1 ); \
53} while(0)
wdenkb4676a22003-12-07 19:24:00 +000054#else
55#define ERR_LED(code)
56#endif
57
wdenkb4676a22003-12-07 19:24:00 +000058#define CONFIG_MPC824X 1
59#define CONFIG_MPC8245 1
60#define CONFIG_MVBLUE 1
61
62#define CONFIG_CLOCKS_IN_MHZ 1
63
Stefan Roesef2302d42008-08-06 14:05:38 +020064#define CONFIG_BOARD_TYPES 1
wdenkb4676a22003-12-07 19:24:00 +000065
66#define CONFIG_CONS_INDEX 1
67#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkb4676a22003-12-07 19:24:00 +000069
Stefan Roesef2302d42008-08-06 14:05:38 +020070#define CONFIG_BOOTDELAY 3
wdenkb4676a22003-12-07 19:24:00 +000071#define CONFIG_BOOT_RETRY_TIME -1
72
73#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +020074#define CONFIG_AUTOBOOT_PROMPT \
75 "autoboot in %d seconds (stop with 's')...\n", bootdelay
wdenkd4ca31c2004-01-02 14:00:00 +000076#define CONFIG_AUTOBOOT_STOP_STR "s"
wdenkb4676a22003-12-07 19:24:00 +000077#define CONFIG_ZERO_BOOTDELAY_CHECK
78#define CONFIG_RESET_TO_RETRY 60
79
Jon Loeliger8353e132007-07-08 14:14:17 -050080
81/*
82 * Command line configuration.
83 */
84
85#define CONFIG_CMD_ASKENV
86#define CONFIG_CMD_BOOTD
87#define CONFIG_CMD_CACHE
88#define CONFIG_CMD_DHCP
89#define CONFIG_CMD_ECHO
Mike Frysingerbdab39d2009-01-28 19:08:14 -050090#define CONFIG_CMD_SAVEENV
Jon Loeliger8353e132007-07-08 14:14:17 -050091#define CONFIG_CMD_FLASH
92#define CONFIG_CMD_IMI
Jon Loeliger8353e132007-07-08 14:14:17 -050093#define CONFIG_CMD_NET
94#define CONFIG_CMD_PCI
95#define CONFIG_CMD_RUN
wdenkb4676a22003-12-07 19:24:00 +000096
97
Jon Loeliger7be044e2007-07-09 21:24:19 -050098/*
99 * BOOTP options
100 */
101#define CONFIG_BOOTP_SUBNETMASK
102#define CONFIG_BOOTP_GATEWAY
103#define CONFIG_BOOTP_HOSTNAME
104#define CONFIG_BOOTP_BOOTPATH
105#define CONFIG_BOOTP_BOOTFILESIZE
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_NISDOMAIN
110#define CONFIG_BOOTP_BOOTPATH
111#define CONFIG_BOOTP_DNS
112#define CONFIG_BOOTP_DNS2
113#define CONFIG_BOOTP_SEND_HOSTNAME
114#define CONFIG_BOOTP_NTPSERVER
115#define CONFIG_BOOTP_TIMEOFFSET
116
wdenkb4676a22003-12-07 19:24:00 +0000117
wdenkb4676a22003-12-07 19:24:00 +0000118/*
119 * Miscellaneous configurable options
120 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LONGHELP /* undef to save memory */
122#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
123#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkb4676a22003-12-07 19:24:00 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
126#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
128#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkb4676a22003-12-07 19:24:00 +0000129
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200130#define CONFIG_BOOTCOMMAND "run nfsboot"
wdenkb4676a22003-12-07 19:24:00 +0000131#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
132
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200133#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
wdenkb4676a22003-12-07 19:24:00 +0000134
wdenkd4ca31c2004-01-02 14:00:00 +0000135#define CONFIG_EXTRA_ENV_SETTINGS \
136 "console_nr=0\0" \
137 "dhcp_client_id=mvBOX-XP\0" \
138 "dhcp_vendor-class-identifier=mvBOX\0" \
139 "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
140 "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
141 "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
142 "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100143 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
144 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
145 "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
wdenkb4676a22003-12-07 19:24:00 +0000146 "mv_version=" MV_VERSION "\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000147 "bootretry=30\0"
wdenkb4676a22003-12-07 19:24:00 +0000148
149#define CONFIG_OVERWRITE_ETHADDR_ONCE
150
151/*-----------------------------------------------------------------------
152 * PCI stuff
153 *-----------------------------------------------------------------------
154 */
155
wdenkd4ca31c2004-01-02 14:00:00 +0000156#define CONFIG_PCI
wdenkb4676a22003-12-07 19:24:00 +0000157#define CONFIG_PCI_PNP
158#define CONFIG_PCI_SCAN_SHOW
159
wdenkd4ca31c2004-01-02 14:00:00 +0000160#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200161#define CONFIG_NET_RETRY_COUNT 5
wdenkb4676a22003-12-07 19:24:00 +0000162
163#define CONFIG_TULIP
164#define CONFIG_TULIP_FIX_DAVICOM 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200165#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
wdenkb4676a22003-12-07 19:24:00 +0000166
167#define CONFIG_HW_WATCHDOG
168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkb4676a22003-12-07 19:24:00 +0000173 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkb4676a22003-12-07 19:24:00 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BASE 0xFFF00000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200177#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkb4676a22003-12-07 19:24:00 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
180#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkb4676a22003-12-07 19:24:00 +0000181
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_MONITOR_LEN 0x00100000
183#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
wdenkb4676a22003-12-07 19:24:00 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
186#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
wdenkb4676a22003-12-07 19:24:00 +0000187
188/* Maximum amount of RAM. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
wdenkb4676a22003-12-07 19:24:00 +0000190
191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
193#undef CONFIG_SYS_RAMBOOT
wdenkb4676a22003-12-07 19:24:00 +0000194#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_RAMBOOT
wdenkb4676a22003-12-07 19:24:00 +0000196#endif
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkb4676a22003-12-07 19:24:00 +0000199
200/*
201 * serial configuration
202 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_NS16550
204#define CONFIG_SYS_NS16550_SERIAL
wdenkb4676a22003-12-07 19:24:00 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkb4676a22003-12-07 19:24:00 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenkb4676a22003-12-07 19:24:00 +0000209
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenkb4676a22003-12-07 19:24:00 +0000212
213/*-----------------------------------------------------------------------
214 * Definitions for initial stack pointer and data area
215 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
217#define CONFIG_SYS_INIT_RAM_END 0x1000
218#define CONFIG_SYS_GBL_DATA_SIZE 128
219#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
wdenkb4676a22003-12-07 19:24:00 +0000220
221/*
222 * Low Level Configuration Settings
223 * (address mappings, register initial values, etc.)
224 * You should know what you are doing if you make changes here.
225 * For the detail description refer to the MPC8240 user's manual.
226 */
227
wdenkd4ca31c2004-01-02 14:00:00 +0000228#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_HZ 10000
wdenkb4676a22003-12-07 19:24:00 +0000230
231/* Bit-field values for MCCR1. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_ROMNAL 7
233#define CONFIG_SYS_ROMFAL 11
wdenkb4676a22003-12-07 19:24:00 +0000234
235/* Bit-field values for MCCR2. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_TSWAIT 0x5
237#define CONFIG_SYS_REFINT 430
wdenkb4676a22003-12-07 19:24:00 +0000238
239/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_BSTOPRE 121
wdenkb4676a22003-12-07 19:24:00 +0000241
242/* Bit-field values for MCCR3. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_REFREC 8
wdenkb4676a22003-12-07 19:24:00 +0000244
245/* Bit-field values for MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_PRETOACT 3
247#define CONFIG_SYS_ACTTOPRE 5
248#define CONFIG_SYS_ACTORW 3
249#define CONFIG_SYS_SDMODE_CAS_LAT 3
250#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
251#define CONFIG_SYS_EXTROM 1
252#define CONFIG_SYS_REGDIMM 0
253#define CONFIG_SYS_DBUS_SIZE2 1
254#define CONFIG_SYS_SDMODE_WRAP 0
wdenkb4676a22003-12-07 19:24:00 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PGMAX 0x32
257#define CONFIG_SYS_SDRAM_DSCD 0x20
wdenkb4676a22003-12-07 19:24:00 +0000258
259/* Memory bank settings.
260 * Only bits 20-29 are actually used from these vales to set the
261 * start/end addresses. The upper two bits will always be 0, and the lower
262 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
263 * address. Refer to the MPC8240 book.
264 */
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_BANK0_START 0x00000000
267#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
268#define CONFIG_SYS_BANK0_ENABLE 1
269#define CONFIG_SYS_BANK1_START 0x3ff00000
270#define CONFIG_SYS_BANK1_END 0x3fffffff
271#define CONFIG_SYS_BANK1_ENABLE 0
272#define CONFIG_SYS_BANK2_START 0x3ff00000
273#define CONFIG_SYS_BANK2_END 0x3fffffff
274#define CONFIG_SYS_BANK2_ENABLE 0
275#define CONFIG_SYS_BANK3_START 0x3ff00000
276#define CONFIG_SYS_BANK3_END 0x3fffffff
277#define CONFIG_SYS_BANK3_ENABLE 0
278#define CONFIG_SYS_BANK4_START 0x3ff00000
279#define CONFIG_SYS_BANK4_END 0x3fffffff
280#define CONFIG_SYS_BANK4_ENABLE 0
281#define CONFIG_SYS_BANK5_START 0x3ff00000
282#define CONFIG_SYS_BANK5_END 0x3fffffff
283#define CONFIG_SYS_BANK5_ENABLE 0
284#define CONFIG_SYS_BANK6_START 0x3ff00000
285#define CONFIG_SYS_BANK6_END 0x3fffffff
286#define CONFIG_SYS_BANK6_ENABLE 0
287#define CONFIG_SYS_BANK7_START 0x3ff00000
288#define CONFIG_SYS_BANK7_END 0x3fffffff
289#define CONFIG_SYS_BANK7_ENABLE 0
wdenkb4676a22003-12-07 19:24:00 +0000290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_ODCR 0xff
wdenkb4676a22003-12-07 19:24:00 +0000292
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
294#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
297#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
300#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
303#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
306#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
307#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
308#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
309#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
310#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
311#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
312#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkb4676a22003-12-07 19:24:00 +0000313
314/*
315 * For booting Linux, the board info and command line data
316 * have to be in the first 8 MB of memory, since this is
317 * the maximum mapped by the Linux kernel during initialization.
318 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkb4676a22003-12-07 19:24:00 +0000320
321/*-----------------------------------------------------------------------
322 * FLASH organization
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#undef CONFIG_SYS_FLASH_PROTECTION
325#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
326#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
wdenkb4676a22003-12-07 19:24:00 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
329#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
wdenkb4676a22003-12-07 19:24:00 +0000330
331
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200332#define CONFIG_ENV_IS_IN_FLASH
wdenkb4676a22003-12-07 19:24:00 +0000333
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200334#define CONFIG_ENV_OFFSET 0x00010000
335#define CONFIG_ENV_SIZE 0x00010000
336#define CONFIG_ENV_SECT_SIZE 0x00010000
wdenkb4676a22003-12-07 19:24:00 +0000337
338/*-----------------------------------------------------------------------
339 * Cache Configuration
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger8353e132007-07-08 14:14:17 -0500342#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkb4676a22003-12-07 19:24:00 +0000344#endif
wdenkb4676a22003-12-07 19:24:00 +0000345#endif /* __CONFIG_H */