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wdenkb4676a22003-12-07 19:24:00 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28#define MV_VERSION "v0.2.0"
29
30/* LED0 = Power , LED1 = Error , LED2-5 = error code, LED6-7=00 -->PPCBoot error */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020031#define ERR_NONE 0
32#define ERR_ENV 1
33#define ERR_BOOTM_BADMAGIC 2
34#define ERR_BOOTM_BADCRC 3
35#define ERR_BOOTM_GUNZIP 4
wdenkb4676a22003-12-07 19:24:00 +000036#define ERR_BOOTP_TIMEOUT 5
Wolfgang Denk53677ef2008-05-20 16:00:29 +020037#define ERR_DHCP 6
38#define ERR_TFTP 7
39#define ERR_NOLAN 8
40#define ERR_LANDRV 9
wdenkb4676a22003-12-07 19:24:00 +000041
42#define CONFIG_BOARD_TYPES 1
43#define MVBLUE_BOARD_BOX 1
44#define MVBLUE_BOARD_LYNX 2
45
46#if 0
47#define ERR_LED(code) do { if (code) \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020048 *(volatile char *)(0xff000003) = ( 3 | (code<<4) ) & 0xf3; \
49 else \
50 *(volatile char *)(0xff000003) = ( 1 ); \
51} while(0)
wdenkb4676a22003-12-07 19:24:00 +000052#else
53#define ERR_LED(code)
54#endif
55
wdenkb4676a22003-12-07 19:24:00 +000056#define CONFIG_MPC824X 1
57#define CONFIG_MPC8245 1
58#define CONFIG_MVBLUE 1
59
60#define CONFIG_CLOCKS_IN_MHZ 1
61
Stefan Roesef2302d42008-08-06 14:05:38 +020062#define CONFIG_BOARD_TYPES 1
wdenkb4676a22003-12-07 19:24:00 +000063
64#define CONFIG_CONS_INDEX 1
65#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkb4676a22003-12-07 19:24:00 +000067
Stefan Roesef2302d42008-08-06 14:05:38 +020068#define CONFIG_BOOTDELAY 3
wdenkb4676a22003-12-07 19:24:00 +000069#define CONFIG_BOOT_RETRY_TIME -1
70
71#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +020072#define CONFIG_AUTOBOOT_PROMPT \
73 "autoboot in %d seconds (stop with 's')...\n", bootdelay
wdenkd4ca31c2004-01-02 14:00:00 +000074#define CONFIG_AUTOBOOT_STOP_STR "s"
wdenkb4676a22003-12-07 19:24:00 +000075#define CONFIG_ZERO_BOOTDELAY_CHECK
76#define CONFIG_RESET_TO_RETRY 60
77
Jon Loeliger8353e132007-07-08 14:14:17 -050078
79/*
80 * Command line configuration.
81 */
82
83#define CONFIG_CMD_ASKENV
84#define CONFIG_CMD_BOOTD
85#define CONFIG_CMD_CACHE
86#define CONFIG_CMD_DHCP
87#define CONFIG_CMD_ECHO
Mike Frysingerbdab39d2009-01-28 19:08:14 -050088#define CONFIG_CMD_SAVEENV
Jon Loeliger8353e132007-07-08 14:14:17 -050089#define CONFIG_CMD_FLASH
90#define CONFIG_CMD_IMI
Jon Loeliger8353e132007-07-08 14:14:17 -050091#define CONFIG_CMD_NET
92#define CONFIG_CMD_PCI
93#define CONFIG_CMD_RUN
wdenkb4676a22003-12-07 19:24:00 +000094
95
Jon Loeliger7be044e2007-07-09 21:24:19 -050096/*
97 * BOOTP options
98 */
99#define CONFIG_BOOTP_SUBNETMASK
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102#define CONFIG_BOOTP_BOOTPATH
103#define CONFIG_BOOTP_BOOTFILESIZE
104#define CONFIG_BOOTP_SUBNETMASK
105#define CONFIG_BOOTP_GATEWAY
106#define CONFIG_BOOTP_HOSTNAME
107#define CONFIG_BOOTP_NISDOMAIN
108#define CONFIG_BOOTP_BOOTPATH
109#define CONFIG_BOOTP_DNS
110#define CONFIG_BOOTP_DNS2
111#define CONFIG_BOOTP_SEND_HOSTNAME
112#define CONFIG_BOOTP_NTPSERVER
113#define CONFIG_BOOTP_TIMEOFFSET
114
wdenkb4676a22003-12-07 19:24:00 +0000115
wdenkb4676a22003-12-07 19:24:00 +0000116/*
117 * Miscellaneous configurable options
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_LONGHELP /* undef to save memory */
120#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkb4676a22003-12-07 19:24:00 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
124#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
126#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenkb4676a22003-12-07 19:24:00 +0000127
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200128#define CONFIG_BOOTCOMMAND "run nfsboot"
wdenkb4676a22003-12-07 19:24:00 +0000129#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ro rootfstype=jffs2"
130
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200131#define CONFIG_NFSBOOTCOMMAND "bootp; run nfsargs addcons;bootm"
wdenkb4676a22003-12-07 19:24:00 +0000132
wdenkd4ca31c2004-01-02 14:00:00 +0000133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "console_nr=0\0" \
135 "dhcp_client_id=mvBOX-XP\0" \
136 "dhcp_vendor-class-identifier=mvBOX\0" \
137 "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" \
138 "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" \
139 "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" \
140 "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100141 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
142 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
143 "addcons=setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8\0" \
wdenkb4676a22003-12-07 19:24:00 +0000144 "mv_version=" MV_VERSION "\0" \
wdenkd4ca31c2004-01-02 14:00:00 +0000145 "bootretry=30\0"
wdenkb4676a22003-12-07 19:24:00 +0000146
147#define CONFIG_OVERWRITE_ETHADDR_ONCE
148
149/*-----------------------------------------------------------------------
150 * PCI stuff
151 *-----------------------------------------------------------------------
152 */
153
wdenkd4ca31c2004-01-02 14:00:00 +0000154#define CONFIG_PCI
wdenkb4676a22003-12-07 19:24:00 +0000155#define CONFIG_PCI_PNP
156#define CONFIG_PCI_SCAN_SHOW
157
wdenkd4ca31c2004-01-02 14:00:00 +0000158#define CONFIG_NET_MULTI
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200159#define CONFIG_NET_RETRY_COUNT 5
wdenkb4676a22003-12-07 19:24:00 +0000160
161#define CONFIG_TULIP
162#define CONFIG_TULIP_FIX_DAVICOM 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200163#define CONFIG_ETHADDR b6:b4:45:eb:fb:c0
wdenkb4676a22003-12-07 19:24:00 +0000164
165#define CONFIG_HW_WATCHDOG
166
167/*-----------------------------------------------------------------------
168 * Start addresses for the final memory configuration
169 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkb4676a22003-12-07 19:24:00 +0000171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkb4676a22003-12-07 19:24:00 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_FLASH_BASE 0xFFF00000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200175#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkb4676a22003-12-07 19:24:00 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
178#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkb4676a22003-12-07 19:24:00 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MONITOR_LEN 0x00100000
181#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve some kB for malloc() */
wdenkb4676a22003-12-07 19:24:00 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
184#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 1M ... 8M in DRAM */
wdenkb4676a22003-12-07 19:24:00 +0000185
186/* Maximum amount of RAM. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 0 .. 256MB of (S)DRAM */
wdenkb4676a22003-12-07 19:24:00 +0000188
189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
191#undef CONFIG_SYS_RAMBOOT
wdenkb4676a22003-12-07 19:24:00 +0000192#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_RAMBOOT
wdenkb4676a22003-12-07 19:24:00 +0000194#endif
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkb4676a22003-12-07 19:24:00 +0000197
198/*
199 * serial configuration
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_NS16550
202#define CONFIG_SYS_NS16550_SERIAL
wdenkb4676a22003-12-07 19:24:00 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkb4676a22003-12-07 19:24:00 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenkb4676a22003-12-07 19:24:00 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
209#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenkb4676a22003-12-07 19:24:00 +0000210
211/*-----------------------------------------------------------------------
212 * Definitions for initial stack pointer and data area
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
215#define CONFIG_SYS_INIT_RAM_END 0x1000
216#define CONFIG_SYS_GBL_DATA_SIZE 128
217#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
wdenkb4676a22003-12-07 19:24:00 +0000218
219/*
220 * Low Level Configuration Settings
221 * (address mappings, register initial values, etc.)
222 * You should know what you are doing if you make changes here.
223 * For the detail description refer to the MPC8240 user's manual.
224 */
225
wdenkd4ca31c2004-01-02 14:00:00 +0000226#define CONFIG_SYS_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_HZ 10000
wdenkb4676a22003-12-07 19:24:00 +0000228
229/* Bit-field values for MCCR1. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_ROMNAL 7
231#define CONFIG_SYS_ROMFAL 11
wdenkb4676a22003-12-07 19:24:00 +0000232
233/* Bit-field values for MCCR2. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_TSWAIT 0x5
235#define CONFIG_SYS_REFINT 430
wdenkb4676a22003-12-07 19:24:00 +0000236
237/* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_BSTOPRE 121
wdenkb4676a22003-12-07 19:24:00 +0000239
240/* Bit-field values for MCCR3. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_REFREC 8
wdenkb4676a22003-12-07 19:24:00 +0000242
243/* Bit-field values for MCCR4. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_PRETOACT 3
245#define CONFIG_SYS_ACTTOPRE 5
246#define CONFIG_SYS_ACTORW 3
247#define CONFIG_SYS_SDMODE_CAS_LAT 3
248#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
249#define CONFIG_SYS_EXTROM 1
250#define CONFIG_SYS_REGDIMM 0
251#define CONFIG_SYS_DBUS_SIZE2 1
252#define CONFIG_SYS_SDMODE_WRAP 0
wdenkb4676a22003-12-07 19:24:00 +0000253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PGMAX 0x32
255#define CONFIG_SYS_SDRAM_DSCD 0x20
wdenkb4676a22003-12-07 19:24:00 +0000256
257/* Memory bank settings.
258 * Only bits 20-29 are actually used from these vales to set the
259 * start/end addresses. The upper two bits will always be 0, and the lower
260 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
261 * address. Refer to the MPC8240 book.
262 */
263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_BANK0_START 0x00000000
265#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
266#define CONFIG_SYS_BANK0_ENABLE 1
267#define CONFIG_SYS_BANK1_START 0x3ff00000
268#define CONFIG_SYS_BANK1_END 0x3fffffff
269#define CONFIG_SYS_BANK1_ENABLE 0
270#define CONFIG_SYS_BANK2_START 0x3ff00000
271#define CONFIG_SYS_BANK2_END 0x3fffffff
272#define CONFIG_SYS_BANK2_ENABLE 0
273#define CONFIG_SYS_BANK3_START 0x3ff00000
274#define CONFIG_SYS_BANK3_END 0x3fffffff
275#define CONFIG_SYS_BANK3_ENABLE 0
276#define CONFIG_SYS_BANK4_START 0x3ff00000
277#define CONFIG_SYS_BANK4_END 0x3fffffff
278#define CONFIG_SYS_BANK4_ENABLE 0
279#define CONFIG_SYS_BANK5_START 0x3ff00000
280#define CONFIG_SYS_BANK5_END 0x3fffffff
281#define CONFIG_SYS_BANK5_ENABLE 0
282#define CONFIG_SYS_BANK6_START 0x3ff00000
283#define CONFIG_SYS_BANK6_END 0x3fffffff
284#define CONFIG_SYS_BANK6_ENABLE 0
285#define CONFIG_SYS_BANK7_START 0x3ff00000
286#define CONFIG_SYS_BANK7_END 0x3fffffff
287#define CONFIG_SYS_BANK7_ENABLE 0
wdenkb4676a22003-12-07 19:24:00 +0000288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_ODCR 0xff
wdenkb4676a22003-12-07 19:24:00 +0000290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
292#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000293
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
295#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000296
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
298#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
301#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkb4676a22003-12-07 19:24:00 +0000302
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
304#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
305#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
306#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
307#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
308#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
309#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
310#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkb4676a22003-12-07 19:24:00 +0000311
312/*
313 * For booting Linux, the board info and command line data
314 * have to be in the first 8 MB of memory, since this is
315 * the maximum mapped by the Linux kernel during initialization.
316 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkb4676a22003-12-07 19:24:00 +0000318
319/*-----------------------------------------------------------------------
320 * FLASH organization
321 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#undef CONFIG_SYS_FLASH_PROTECTION
323#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
324#define CONFIG_SYS_MAX_FLASH_SECT 63 /* Max number of sectors per flash */
wdenkb4676a22003-12-07 19:24:00 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_FLASH_ERASE_TOUT 12000
327#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
wdenkb4676a22003-12-07 19:24:00 +0000328
329
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200330#define CONFIG_ENV_IS_IN_FLASH
wdenkb4676a22003-12-07 19:24:00 +0000331
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200332#define CONFIG_ENV_OFFSET 0x00010000
333#define CONFIG_ENV_SIZE 0x00010000
334#define CONFIG_ENV_SECT_SIZE 0x00010000
wdenkb4676a22003-12-07 19:24:00 +0000335
336/*-----------------------------------------------------------------------
337 * Cache Configuration
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger8353e132007-07-08 14:14:17 -0500340#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkb4676a22003-12-07 19:24:00 +0000342#endif
343
344/*
345 * Internal Definitions
346 *
347 * Boot Flags
348 */
349#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
350#define BOOTFLAG_WARM 0x02 /* Software reboot */
351
352#endif /* __CONFIG_H */