blob: 74a84f4e86ab259c8477c9cc4a064a20c09297dd [file] [log] [blame]
wdenk42d1f032003-10-15 23:53:47 +00001/*
wdenk0ac6f8b2004-07-09 23:27:13 +00002 * Copyright 2004 Freescale Semiconductor.
wdenk42d1f032003-10-15 23:53:47 +00003 * (C) Copyright 2002,2003 Motorola,Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
wdenk0ac6f8b2004-07-09 23:27:13 +000025/*
26 * mpc8540ads board configuration file
27 *
28 * Please refer to doc/README.mpc85xx for more info.
29 *
30 * Make sure you change the MAC address and other network params first,
31 * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
wdenk42d1f032003-10-15 23:53:47 +000032 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* High Level Configuration Options */
wdenk0ac6f8b2004-07-09 23:27:13 +000038#define CONFIG_BOOKE 1 /* BOOKE */
39#define CONFIG_E500 1 /* BOOKE e500 family */
40#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
41#define CONFIG_MPC8540 1 /* MPC8540 specific */
42#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
wdenk42d1f032003-10-15 23:53:47 +000043
Jon Loeliger288693a2005-07-25 12:14:54 -050044#ifndef CONFIG_HAS_FEC
45#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
46#endif
47
wdenk0ac6f8b2004-07-09 23:27:13 +000048#define CONFIG_PCI
49#define CONFIG_TSEC_ENET /* tsec ethernet support */
wdenk42d1f032003-10-15 23:53:47 +000050#define CONFIG_ENV_OVERWRITE
wdenk0ac6f8b2004-07-09 23:27:13 +000051#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
wdenk0ac6f8b2004-07-09 23:27:13 +000052#define CONFIG_DDR_DLL /* possible DLL fix needed */
53#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
wdenk42d1f032003-10-15 23:53:47 +000054
Jon Loeligerd9b94f22005-07-25 14:05:07 -050055#define CONFIG_DDR_ECC /* only for ECC DDR module */
56#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
57
wdenk42d1f032003-10-15 23:53:47 +000058
wdenk0ac6f8b2004-07-09 23:27:13 +000059/*
60 * sysclk for MPC85xx
61 *
62 * Two valid values are:
63 * 33000000
64 * 66000000
65 *
66 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
wdenk9aea9532004-08-01 23:02:45 +000067 * is likely the desired value here, so that is now the default.
68 * The board, however, can run at 66MHz. In any event, this value
69 * must match the settings of some switches. Details can be found
70 * in the README.mpc85xxads.
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050071 *
72 * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
73 * 33MHz to accommodate, based on a PCI pin.
74 * Note that PCI-X won't work at 33MHz.
wdenk0ac6f8b2004-07-09 23:27:13 +000075 */
76
wdenk9aea9532004-08-01 23:02:45 +000077#ifndef CONFIG_SYS_CLK_FREQ
Matthew McClintock34c3c0e2006-06-28 10:47:03 -050078#define CONFIG_SYS_CLK_FREQ 33000000
wdenk42d1f032003-10-15 23:53:47 +000079#endif
80
wdenk9aea9532004-08-01 23:02:45 +000081
wdenk0ac6f8b2004-07-09 23:27:13 +000082/*
83 * These can be toggled for performance analysis, otherwise use default.
84 */
85#define CONFIG_L2_CACHE /* toggle L2 cache */
86#define CONFIG_BTB /* toggle branch predition */
87#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
wdenk42d1f032003-10-15 23:53:47 +000088
wdenk0ac6f8b2004-07-09 23:27:13 +000089#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
wdenk42d1f032003-10-15 23:53:47 +000090
wdenk0ac6f8b2004-07-09 23:27:13 +000091#undef CFG_DRAM_TEST /* memory test, takes time */
92#define CFG_MEMTEST_START 0x00200000 /* memtest region */
wdenk42d1f032003-10-15 23:53:47 +000093#define CFG_MEMTEST_END 0x00400000
94
wdenk42d1f032003-10-15 23:53:47 +000095
96/*
97 * Base addresses -- Note these are effective addresses where the
98 * actual resources get mapped (not physical addresses)
99 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000100#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
101#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
102#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
wdenk42d1f032003-10-15 23:53:47 +0000103
wdenk9aea9532004-08-01 23:02:45 +0000104
105/*
106 * DDR Setup
107 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000108#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
wdenk42d1f032003-10-15 23:53:47 +0000109#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
wdenk9aea9532004-08-01 23:02:45 +0000110
111#if defined(CONFIG_SPD_EEPROM)
112 /*
113 * Determine DDR configuration from I2C interface.
114 */
115 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
116
117#else
118 /*
119 * Manually set up DDR parameters
120 */
121 #define CFG_SDRAM_SIZE 128 /* DDR is 128MB */
122 #define CFG_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
123 #define CFG_DDR_CS0_CONFIG 0x80000002
124 #define CFG_DDR_TIMING_1 0x37344321
125 #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
126 #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
127 #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
128 #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
129#endif
130
wdenk42d1f032003-10-15 23:53:47 +0000131
wdenk0ac6f8b2004-07-09 23:27:13 +0000132/*
133 * SDRAM on the Local Bus
134 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000135#define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
wdenk0ac6f8b2004-07-09 23:27:13 +0000136#define CFG_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
wdenk42d1f032003-10-15 23:53:47 +0000137
wdenk0ac6f8b2004-07-09 23:27:13 +0000138#define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */
139#define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */
wdenk42d1f032003-10-15 23:53:47 +0000140
wdenk0ac6f8b2004-07-09 23:27:13 +0000141#define CFG_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
142#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
143#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
wdenk42d1f032003-10-15 23:53:47 +0000144#undef CFG_FLASH_CHECKSUM
wdenk0ac6f8b2004-07-09 23:27:13 +0000145#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
146#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
wdenk42d1f032003-10-15 23:53:47 +0000147
wdenk0ac6f8b2004-07-09 23:27:13 +0000148#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
149
wdenk42d1f032003-10-15 23:53:47 +0000150#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
151#define CFG_RAMBOOT
152#else
wdenk0ac6f8b2004-07-09 23:27:13 +0000153#undef CFG_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000154#endif
155
wdenkcf336782004-10-10 20:23:57 +0000156#define CFG_FLASH_CFI_DRIVER
157#define CFG_FLASH_CFI
158#define CFG_FLASH_EMPTY_INFO
wdenk42d1f032003-10-15 23:53:47 +0000159
wdenk42d1f032003-10-15 23:53:47 +0000160#undef CONFIG_CLOCKS_IN_MHZ
161
wdenk0ac6f8b2004-07-09 23:27:13 +0000162
163/*
164 * Local Bus Definitions
165 */
166
167/*
168 * Base Register 2 and Option Register 2 configure SDRAM.
169 * The SDRAM base address, CFG_LBC_SDRAM_BASE, is 0xf0000000.
170 *
171 * For BR2, need:
172 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
173 * port-size = 32-bits = BR2[19:20] = 11
174 * no parity checking = BR2[21:22] = 00
175 * SDRAM for MSEL = BR2[24:26] = 011
176 * Valid = BR[31] = 1
177 *
178 * 0 4 8 12 16 20 24 28
179 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
180 *
181 * FIXME: CFG_LBC_SDRAM_BASE should be masked and OR'ed into
182 * FIXME: the top 17 bits of BR2.
183 */
184
185#define CFG_BR2_PRELIM 0xf0001861
186
187/*
188 * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
189 *
190 * For OR2, need:
191 * 64MB mask for AM, OR2[0:7] = 1111 1100
192 * XAM, OR2[17:18] = 11
193 * 9 columns OR2[19-21] = 010
194 * 13 rows OR2[23-25] = 100
195 * EAD set for extra time OR[31] = 1
196 *
197 * 0 4 8 12 16 20 24 28
198 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
199 */
200
wdenk42d1f032003-10-15 23:53:47 +0000201#define CFG_OR2_PRELIM 0xfc006901
wdenk0ac6f8b2004-07-09 23:27:13 +0000202
203#define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
204#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
205#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
206#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
207
208/*
209 * LSDMR masks
210 */
211#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
212#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
213#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
214#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
215#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
216#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
217#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
218#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
219#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
220#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
221#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
222#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
223#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
224#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
225#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
226
227#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
228#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
229#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
230#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
231#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
232#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
233#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
234#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
235
236#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
237 | CFG_LBC_LSDMR_RFCR5 \
238 | CFG_LBC_LSDMR_PRETOACT3 \
239 | CFG_LBC_LSDMR_ACTTORW3 \
240 | CFG_LBC_LSDMR_BL8 \
241 | CFG_LBC_LSDMR_WRC2 \
242 | CFG_LBC_LSDMR_CL3 \
243 | CFG_LBC_LSDMR_RFEN \
244 )
245
246/*
247 * SDRAM Controller configuration sequence.
248 */
249#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000250 | CFG_LBC_LSDMR_OP_PCHALL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000251#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000252 | CFG_LBC_LSDMR_OP_ARFRSH)
wdenk0ac6f8b2004-07-09 23:27:13 +0000253#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000254 | CFG_LBC_LSDMR_OP_ARFRSH)
wdenk0ac6f8b2004-07-09 23:27:13 +0000255#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000256 | CFG_LBC_LSDMR_OP_MRW)
wdenk0ac6f8b2004-07-09 23:27:13 +0000257#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
wdenk9aea9532004-08-01 23:02:45 +0000258 | CFG_LBC_LSDMR_OP_NORMAL)
wdenk0ac6f8b2004-07-09 23:27:13 +0000259
wdenk42d1f032003-10-15 23:53:47 +0000260
wdenk9aea9532004-08-01 23:02:45 +0000261/*
262 * 32KB, 8-bit wide for ADS config reg
263 */
264#define CFG_BR4_PRELIM 0xf8000801
wdenkc837dcb2004-01-20 23:12:12 +0000265#define CFG_OR4_PRELIM 0xffffe1f1
266#define CFG_BCSR (CFG_BR4_PRELIM & 0xffff8000)
wdenk42d1f032003-10-15 23:53:47 +0000267
268#define CONFIG_L1_INIT_RAM
wdenk0ac6f8b2004-07-09 23:27:13 +0000269#define CFG_INIT_RAM_LOCK 1
wdenk9aea9532004-08-01 23:02:45 +0000270#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
wdenk0ac6f8b2004-07-09 23:27:13 +0000271#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
wdenk42d1f032003-10-15 23:53:47 +0000272
wdenk0ac6f8b2004-07-09 23:27:13 +0000273#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
wdenk42d1f032003-10-15 23:53:47 +0000274#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
275#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
276
wdenka1191902005-01-09 17:12:27 +0000277#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
wdenk0ac6f8b2004-07-09 23:27:13 +0000278#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
wdenk42d1f032003-10-15 23:53:47 +0000279
280/* Serial Port */
281#define CONFIG_CONS_INDEX 1
282#undef CONFIG_SERIAL_SOFTWARE_FIFO
283#define CFG_NS16550
284#define CFG_NS16550_SERIAL
wdenk0ac6f8b2004-07-09 23:27:13 +0000285#define CFG_NS16550_REG_SIZE 1
wdenk42d1f032003-10-15 23:53:47 +0000286#define CFG_NS16550_CLK get_bus_freq(0)
wdenk42d1f032003-10-15 23:53:47 +0000287
288#define CFG_BAUDRATE_TABLE \
289 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
290
wdenk0ac6f8b2004-07-09 23:27:13 +0000291#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
292#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
wdenk42d1f032003-10-15 23:53:47 +0000293
294/* Use the HUSH parser */
295#define CFG_HUSH_PARSER
wdenk0ac6f8b2004-07-09 23:27:13 +0000296#ifdef CFG_HUSH_PARSER
wdenk42d1f032003-10-15 23:53:47 +0000297#define CFG_PROMPT_HUSH_PS2 "> "
298#endif
299
Matthew McClintock0e163872006-06-28 10:43:36 -0500300/* pass open firmware flat tree */
301#define CONFIG_OF_FLAT_TREE 1
302#define CONFIG_OF_BOARD_SETUP 1
303
304/* maximum size of the flat tree (8K) */
305#define OF_FLAT_TREE_MAX_SIZE 8192
306
307#define OF_CPU "PowerPC,8540@0"
308#define OF_SOC "soc8540@e0000000"
309#define OF_TBCLK (bd->bi_busfreq / 8)
310#define OF_STDOUT_PATH "/soc8540@e0000000/serial@4500"
311
312#define CFG_64BIT_VSPRINTF 1
313#define CFG_64BIT_STRTOUL 1
314
Jon Loeliger20476722006-10-20 15:50:15 -0500315/*
316 * I2C
317 */
318#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
319#define CONFIG_HARD_I2C /* I2C with hardware support*/
wdenk0ac6f8b2004-07-09 23:27:13 +0000320#undef CONFIG_SOFT_I2C /* I2C bit-banged */
321#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
wdenk42d1f032003-10-15 23:53:47 +0000322#define CFG_I2C_SLAVE 0x7F
wdenk0ac6f8b2004-07-09 23:27:13 +0000323#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500324#define CFG_I2C_OFFSET 0x3000
wdenk42d1f032003-10-15 23:53:47 +0000325
wdenk0ac6f8b2004-07-09 23:27:13 +0000326/* RapidIO MMU */
327#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
328#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
329#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
330
331/*
332 * General PCI
333 * Addresses are mapped 1-1.
334 */
335#define CFG_PCI1_MEM_BASE 0x80000000
336#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
337#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
Matthew McClintockc88f9fe2006-06-28 10:45:41 -0500338
339#define CFG_PCI1_IO_BASE 0x0
340#define CFG_PCI1_IO_PHYS 0xe2000000
341#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */
wdenk0ac6f8b2004-07-09 23:27:13 +0000342
wdenk42d1f032003-10-15 23:53:47 +0000343#if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000344
wdenk42d1f032003-10-15 23:53:47 +0000345#define CONFIG_NET_MULTI
wdenk9aea9532004-08-01 23:02:45 +0000346#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk0ac6f8b2004-07-09 23:27:13 +0000347
wdenk42d1f032003-10-15 23:53:47 +0000348#undef CONFIG_EEPRO100
wdenk0ac6f8b2004-07-09 23:27:13 +0000349#undef CONFIG_TULIP
350
351#if !defined(CONFIG_PCI_PNP)
352 #define PCI_ENET0_IOADDR 0xe0000000
353 #define PCI_ENET0_MEMADDR 0xe0000000
354 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
wdenk42d1f032003-10-15 23:53:47 +0000355#endif
356
wdenk0ac6f8b2004-07-09 23:27:13 +0000357#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
358#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
359
360#endif /* CONFIG_PCI */
361
362
363#if defined(CONFIG_TSEC_ENET)
364
365#ifndef CONFIG_NET_MULTI
366#define CONFIG_NET_MULTI 1
367#endif
368
369#define CONFIG_MII 1 /* MII PHY management */
370#define CONFIG_MPC85XX_TSEC1 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500371#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000372#define CONFIG_MPC85XX_TSEC2 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500373#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
wdenk0ac6f8b2004-07-09 23:27:13 +0000374#define TSEC1_PHY_ADDR 0
375#define TSEC2_PHY_ADDR 1
wdenk0ac6f8b2004-07-09 23:27:13 +0000376#define TSEC1_PHYIDX 0
377#define TSEC2_PHYIDX 0
wdenk9aea9532004-08-01 23:02:45 +0000378
Jon Loeliger288693a2005-07-25 12:14:54 -0500379
380#if CONFIG_HAS_FEC
wdenk9aea9532004-08-01 23:02:45 +0000381#define CONFIG_MPC85XX_FEC 1
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500382#define CONFIG_MPC85XX_FEC_NAME "FEC"
wdenk9aea9532004-08-01 23:02:45 +0000383#define FEC_PHY_ADDR 3
wdenk0ac6f8b2004-07-09 23:27:13 +0000384#define FEC_PHYIDX 0
Jon Loeliger288693a2005-07-25 12:14:54 -0500385#endif
wdenk9aea9532004-08-01 23:02:45 +0000386
Jon Loeligerd9b94f22005-07-25 14:05:07 -0500387/* Options are: TSEC[0-1], FEC */
388#define CONFIG_ETHPRIME "TSEC0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000389
390#endif /* CONFIG_TSEC_ENET */
391
392
393/*
394 * Environment
395 */
wdenk42d1f032003-10-15 23:53:47 +0000396#ifndef CFG_RAMBOOT
wdenk42d1f032003-10-15 23:53:47 +0000397 #define CFG_ENV_IS_IN_FLASH 1
398 #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
wdenk0ac6f8b2004-07-09 23:27:13 +0000399 #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
wdenk42d1f032003-10-15 23:53:47 +0000400 #define CFG_ENV_SIZE 0x2000
401#else
wdenk9aea9532004-08-01 23:02:45 +0000402 #define CFG_NO_FLASH 1 /* Flash is not usable now */
403 #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
404 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
405 #define CFG_ENV_SIZE 0x2000
wdenk42d1f032003-10-15 23:53:47 +0000406#endif
407
wdenk0ac6f8b2004-07-09 23:27:13 +0000408#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
409#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk42d1f032003-10-15 23:53:47 +0000410
wdenk9aea9532004-08-01 23:02:45 +0000411#if defined(CFG_RAMBOOT)
wdenk42d1f032003-10-15 23:53:47 +0000412 #if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000413 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
414 | CFG_CMD_PING \
415 | CFG_CMD_PCI \
416 | CFG_CMD_I2C) \
417 & \
418 ~(CFG_CMD_ENV \
419 | CFG_CMD_LOADS))
wdenk42d1f032003-10-15 23:53:47 +0000420 #else
wdenk0ac6f8b2004-07-09 23:27:13 +0000421 #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
422 | CFG_CMD_PING \
423 | CFG_CMD_I2C) \
424 & \
425 ~(CFG_CMD_ENV \
426 | CFG_CMD_LOADS))
wdenk42d1f032003-10-15 23:53:47 +0000427 #endif
428#else
429 #if defined(CONFIG_PCI)
wdenk0ac6f8b2004-07-09 23:27:13 +0000430 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
431 | CFG_CMD_PCI \
432 | CFG_CMD_PING \
433 | CFG_CMD_I2C)
wdenk42d1f032003-10-15 23:53:47 +0000434 #else
wdenk0ac6f8b2004-07-09 23:27:13 +0000435 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
436 | CFG_CMD_PING \
437 | CFG_CMD_I2C)
wdenk42d1f032003-10-15 23:53:47 +0000438 #endif
439#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000440
wdenk42d1f032003-10-15 23:53:47 +0000441#include <cmd_confdefs.h>
442
wdenk0ac6f8b2004-07-09 23:27:13 +0000443#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenk42d1f032003-10-15 23:53:47 +0000444
445/*
446 * Miscellaneous configurable options
447 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000448#define CFG_LONGHELP /* undef to save memory */
449#define CFG_LOAD_ADDR 0x2000000 /* default load address */
450#define CFG_PROMPT "=> " /* Monitor Command Prompt */
451
wdenk42d1f032003-10-15 23:53:47 +0000452#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk0ac6f8b2004-07-09 23:27:13 +0000453 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000454#else
wdenk0ac6f8b2004-07-09 23:27:13 +0000455 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
wdenk42d1f032003-10-15 23:53:47 +0000456#endif
wdenk0ac6f8b2004-07-09 23:27:13 +0000457
wdenk42d1f032003-10-15 23:53:47 +0000458#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
wdenk0ac6f8b2004-07-09 23:27:13 +0000459#define CFG_MAXARGS 16 /* max number of command args */
460#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
461#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
wdenk42d1f032003-10-15 23:53:47 +0000462
463/*
464 * For booting Linux, the board info and command line data
465 * have to be in the first 8 MB of memory, since this is
466 * the maximum mapped by the Linux kernel during initialization.
467 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000468#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
wdenk42d1f032003-10-15 23:53:47 +0000469
470/* Cache Configuration */
wdenk0ac6f8b2004-07-09 23:27:13 +0000471#define CFG_DCACHE_SIZE 32768
wdenk42d1f032003-10-15 23:53:47 +0000472#define CFG_CACHELINE_SIZE 32
473#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
wdenk0ac6f8b2004-07-09 23:27:13 +0000474#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
wdenk42d1f032003-10-15 23:53:47 +0000475#endif
476
477/*
478 * Internal Definitions
479 *
480 * Boot Flags
481 */
482#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
wdenk0ac6f8b2004-07-09 23:27:13 +0000483#define BOOTFLAG_WARM 0x02 /* Software reboot */
wdenk42d1f032003-10-15 23:53:47 +0000484
485#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
486#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
487#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
488#endif
489
wdenk9aea9532004-08-01 23:02:45 +0000490
491/*
492 * Environment Configuration
493 */
wdenk0ac6f8b2004-07-09 23:27:13 +0000494
495/* The mac addresses for all ethernet interface */
wdenk42d1f032003-10-15 23:53:47 +0000496#if defined(CONFIG_TSEC_ENET)
wdenk0ac6f8b2004-07-09 23:27:13 +0000497#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
wdenke2ffd592004-12-31 09:32:47 +0000498#define CONFIG_HAS_ETH1
wdenk0ac6f8b2004-07-09 23:27:13 +0000499#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
wdenke2ffd592004-12-31 09:32:47 +0000500#define CONFIG_HAS_ETH2
wdenk0ac6f8b2004-07-09 23:27:13 +0000501#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
wdenk42d1f032003-10-15 23:53:47 +0000502#endif
503
wdenk0ac6f8b2004-07-09 23:27:13 +0000504#define CONFIG_IPADDR 192.168.1.253
505
506#define CONFIG_HOSTNAME unknown
507#define CONFIG_ROOTPATH /nfsroot
508#define CONFIG_BOOTFILE your.uImage
509
510#define CONFIG_SERVERIP 192.168.1.1
511#define CONFIG_GATEWAYIP 192.168.1.1
512#define CONFIG_NETMASK 255.255.255.0
513
514#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
515
516#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
517#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
518
519#define CONFIG_BAUDRATE 115200
520
wdenk9aea9532004-08-01 23:02:45 +0000521#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk0ac6f8b2004-07-09 23:27:13 +0000522 "netdev=eth0\0" \
523 "consoledev=ttyS0\0" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500524 "ramdiskaddr=600000\0" \
525 "ramdiskfile=your.ramdisk.u-boot\0" \
526 "fdtaddr=400000\0" \
527 "fdtfile=your.fdt.dtb\0"
wdenk0ac6f8b2004-07-09 23:27:13 +0000528
wdenk9aea9532004-08-01 23:02:45 +0000529#define CONFIG_NFSBOOTCOMMAND \
wdenk0ac6f8b2004-07-09 23:27:13 +0000530 "setenv bootargs root=/dev/nfs rw " \
531 "nfsroot=$serverip:$rootpath " \
532 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
533 "console=$consoledev,$baudrate $othbootargs;" \
534 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500535 "tftp $fdtaddr $fdtfile;" \
536 "bootm $loadaddr - $fdtaddr"
wdenk0ac6f8b2004-07-09 23:27:13 +0000537
538#define CONFIG_RAMBOOTCOMMAND \
539 "setenv bootargs root=/dev/ram rw " \
540 "console=$consoledev,$baudrate $othbootargs;" \
541 "tftp $ramdiskaddr $ramdiskfile;" \
542 "tftp $loadaddr $bootfile;" \
Andy Fleming8272dc22006-09-13 10:33:35 -0500543 "tftp $fdtaddr $fdtfile;" \
wdenk0ac6f8b2004-07-09 23:27:13 +0000544 "bootm $loadaddr $ramdiskaddr"
545
546#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
wdenk42d1f032003-10-15 23:53:47 +0000547
548#endif /* __CONFIG_H */