Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 3 | * Common functions for OMAP4/5 based boards |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Author : |
| 9 | * Aneesh V <aneesh@ti.com> |
| 10 | * Steve Sakoman <steve@sakoman.com> |
| 11 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 12 | * SPDX-License-Identifier: GPL-2.0+ |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 13 | */ |
| 14 | #include <common.h> |
Tom Rini | 47f7bca | 2012-08-13 12:03:19 -0700 | [diff] [blame] | 15 | #include <spl.h> |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 16 | #include <asm/arch/sys_proto.h> |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 17 | #include <linux/sizes.h> |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 18 | #include <asm/emif.h> |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 19 | #include <asm/omap_common.h> |
Lokesh Vutla | d4d986e | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 20 | #include <linux/compiler.h> |
R Sricharan | de63ac2 | 2013-03-04 20:04:45 +0000 | [diff] [blame] | 21 | #include <asm/system.h> |
| 22 | |
Nishanth Menon | 93e3568 | 2010-11-19 11:19:40 -0500 | [diff] [blame] | 23 | DECLARE_GLOBAL_DATA_PTR; |
| 24 | |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 25 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) |
| 26 | { |
| 27 | int i; |
| 28 | struct pad_conf_entry *pad = (struct pad_conf_entry *) array; |
| 29 | |
| 30 | for (i = 0; i < size; i++, pad++) |
| 31 | writew(pad->val, base + pad->offset); |
| 32 | } |
| 33 | |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 34 | static void set_mux_conf_regs(void) |
| 35 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 36 | switch (omap_hw_init_context()) { |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 37 | case OMAP_INIT_CONTEXT_SPL: |
| 38 | set_muxconf_regs_essential(); |
| 39 | break; |
| 40 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 41 | break; |
| 42 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 43 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
| 44 | set_muxconf_regs_essential(); |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 45 | break; |
| 46 | } |
| 47 | } |
| 48 | |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 49 | u32 cortex_rev(void) |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 50 | { |
| 51 | |
| 52 | unsigned int rev; |
| 53 | |
| 54 | /* Read Main ID Register (MIDR) */ |
| 55 | asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); |
| 56 | |
| 57 | return rev; |
| 58 | } |
| 59 | |
Tom Rini | 0ac6db2 | 2013-05-31 10:44:23 -0400 | [diff] [blame] | 60 | static void omap_rev_string(void) |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 61 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 62 | u32 omap_rev = omap_revision(); |
Lokesh Vutla | de62688 | 2013-02-12 21:29:03 +0000 | [diff] [blame] | 63 | u32 soc_variant = (omap_rev & 0xF0000000) >> 28; |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 64 | u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; |
| 65 | u32 major_rev = (omap_rev & 0x00000F00) >> 8; |
| 66 | u32 minor_rev = (omap_rev & 0x000000F0) >> 4; |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 67 | |
Lokesh Vutla | de62688 | 2013-02-12 21:29:03 +0000 | [diff] [blame] | 68 | if (soc_variant) |
| 69 | printf("OMAP"); |
| 70 | else |
| 71 | printf("DRA"); |
| 72 | printf("%x ES%x.%x\n", omap_variant, major_rev, |
| 73 | minor_rev); |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 74 | } |
| 75 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 76 | #ifdef CONFIG_SPL_BUILD |
Tom Rini | 861a86f | 2012-08-13 11:37:56 -0700 | [diff] [blame] | 77 | void spl_display_print(void) |
| 78 | { |
| 79 | omap_rev_string(); |
| 80 | } |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 81 | #endif |
| 82 | |
Lokesh Vutla | d4d986e | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 83 | void __weak srcomp_enable(void) |
| 84 | { |
| 85 | } |
| 86 | |
SRICHARAN R | 47c6ea0 | 2013-04-24 00:41:25 +0000 | [diff] [blame] | 87 | #ifdef CONFIG_ARCH_CPU_INIT |
| 88 | /* |
| 89 | * SOC specific cpu init |
| 90 | */ |
| 91 | int arch_cpu_init(void) |
| 92 | { |
Paul Kocialkowski | 60c7c30 | 2015-07-15 16:02:19 +0200 | [diff] [blame] | 93 | #ifdef CONFIG_SPL |
SRICHARAN R | 47c6ea0 | 2013-04-24 00:41:25 +0000 | [diff] [blame] | 94 | save_omap_boot_params(); |
Paul Kocialkowski | 60c7c30 | 2015-07-15 16:02:19 +0200 | [diff] [blame] | 95 | #endif |
SRICHARAN R | 47c6ea0 | 2013-04-24 00:41:25 +0000 | [diff] [blame] | 96 | return 0; |
| 97 | } |
| 98 | #endif /* CONFIG_ARCH_CPU_INIT */ |
| 99 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 100 | /* |
| 101 | * Routine: s_init |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 102 | * Description: Does early system init of watchdog, muxing, andclocks |
| 103 | * Watchdog disable is done always. For the rest what gets done |
| 104 | * depends on the boot mode in which this function is executed |
| 105 | * 1. s_init of SPL running from SRAM |
| 106 | * 2. s_init of U-Boot running from FLASH |
| 107 | * 3. s_init of U-Boot loaded to SDRAM by SPL |
| 108 | * 4. s_init of U-Boot loaded to SDRAM by ROM code using the |
| 109 | * Configuration Header feature |
| 110 | * Please have a look at the respective functions to see what gets |
| 111 | * done in each of these cases |
| 112 | * This function is called with SRAM stack. |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 113 | */ |
| 114 | void s_init(void) |
| 115 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 116 | init_omap_revision(); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 117 | hw_data_init(); |
| 118 | |
Lokesh Vutla | 38f25b1 | 2012-05-29 19:26:43 +0000 | [diff] [blame] | 119 | #ifdef CONFIG_SPL_BUILD |
Rajendra Nayak | 8c16dd6 | 2014-07-18 11:18:48 +0530 | [diff] [blame] | 120 | if (warm_reset() && |
| 121 | (is_omap44xx() || (omap_revision() == OMAP5430_ES1_0))) |
Lokesh Vutla | 38f25b1 | 2012-05-29 19:26:43 +0000 | [diff] [blame] | 122 | force_emif_self_refresh(); |
| 123 | #endif |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 124 | watchdog_init(); |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 125 | set_mux_conf_regs(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 126 | #ifdef CONFIG_SPL_BUILD |
Lokesh Vutla | d4d986e | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 127 | srcomp_enable(); |
Aneesh V | 4ecfcfa | 2011-09-08 11:05:56 -0400 | [diff] [blame] | 128 | do_io_settings(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 129 | #endif |
Kipisz, Steven | 93e6253 | 2016-02-24 12:30:52 -0600 | [diff] [blame^] | 130 | setup_early_clocks(); |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 131 | prcm_init(); |
Simon Glass | 7ae8350 | 2015-03-03 08:03:02 -0700 | [diff] [blame] | 132 | } |
| 133 | |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 134 | #ifdef CONFIG_SPL_BUILD |
Simon Glass | 7ae8350 | 2015-03-03 08:03:02 -0700 | [diff] [blame] | 135 | void board_init_f(ulong dummy) |
| 136 | { |
Lokesh Vutla | 7b92252 | 2014-08-04 19:42:24 +0530 | [diff] [blame] | 137 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
| 138 | board_early_init_f(); |
| 139 | #endif |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 140 | /* For regular u-boot sdram_init() is called from dram_init() */ |
| 141 | sdram_init(); |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 142 | } |
Simon Glass | 7ae8350 | 2015-03-03 08:03:02 -0700 | [diff] [blame] | 143 | #endif |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * Routine: wait_for_command_complete |
| 147 | * Description: Wait for posting to finish on watchdog |
| 148 | */ |
| 149 | void wait_for_command_complete(struct watchdog *wd_base) |
| 150 | { |
| 151 | int pending = 1; |
| 152 | do { |
| 153 | pending = readl(&wd_base->wwps); |
| 154 | } while (pending); |
| 155 | } |
| 156 | |
| 157 | /* |
| 158 | * Routine: watchdog_init |
| 159 | * Description: Shut down watch dogs |
| 160 | */ |
| 161 | void watchdog_init(void) |
| 162 | { |
| 163 | struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; |
| 164 | |
| 165 | writel(WD_UNLOCK1, &wd2_base->wspr); |
| 166 | wait_for_command_complete(wd2_base); |
| 167 | writel(WD_UNLOCK2, &wd2_base->wspr); |
| 168 | } |
| 169 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 170 | |
| 171 | /* |
| 172 | * This function finds the SDRAM size available in the system |
| 173 | * based on DMM section configurations |
| 174 | * This is needed because the size of memory installed may be |
| 175 | * different on different versions of the board |
| 176 | */ |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 177 | u32 omap_sdram_size(void) |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 178 | { |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 179 | u32 section, i, valid; |
| 180 | u64 sdram_start = 0, sdram_end = 0, addr, |
Lokesh Vutla | d7630da | 2014-05-12 13:49:33 +0530 | [diff] [blame] | 181 | size, total_size = 0, trap_size = 0, trap_start = 0; |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 182 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 183 | for (i = 0; i < 4; i++) { |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 184 | section = __raw_readl(DMM_BASE + i*4); |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 185 | valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> |
| 186 | (EMIF_SDRC_ADDRSPC_SHIFT); |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 187 | addr = section & EMIF_SYS_ADDR_MASK; |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 188 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 189 | /* See if the address is valid */ |
Tom Rini | 939911a | 2014-05-16 13:02:24 -0400 | [diff] [blame] | 190 | if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && |
| 191 | (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 192 | size = ((section & EMIF_SYS_SIZE_MASK) >> |
| 193 | EMIF_SYS_SIZE_SHIFT); |
| 194 | size = 1 << size; |
| 195 | size *= SZ_16M; |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 196 | |
| 197 | if (valid != DMM_SDRC_ADDR_SPC_INVALID) { |
| 198 | if (!sdram_start || (addr < sdram_start)) |
| 199 | sdram_start = addr; |
| 200 | if (!sdram_end || ((addr + size) > sdram_end)) |
| 201 | sdram_end = addr + size; |
| 202 | } else { |
| 203 | trap_size = size; |
Lokesh Vutla | d7630da | 2014-05-12 13:49:33 +0530 | [diff] [blame] | 204 | trap_start = addr; |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 205 | } |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 206 | } |
| 207 | } |
Lokesh Vutla | d7630da | 2014-05-12 13:49:33 +0530 | [diff] [blame] | 208 | |
| 209 | if ((trap_start >= sdram_start) && (trap_start < sdram_end)) |
| 210 | total_size = (sdram_end - sdram_start) - (trap_size); |
| 211 | else |
| 212 | total_size = sdram_end - sdram_start; |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 213 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 214 | return total_size; |
| 215 | } |
| 216 | |
| 217 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 218 | /* |
| 219 | * Routine: dram_init |
| 220 | * Description: sets uboots idea of sdram size |
| 221 | */ |
| 222 | int dram_init(void) |
| 223 | { |
Aneesh V | 2ae610f | 2011-07-21 09:10:09 -0400 | [diff] [blame] | 224 | sdram_init(); |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 225 | gd->ram_size = omap_sdram_size(); |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 226 | return 0; |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * Print board information |
| 231 | */ |
| 232 | int checkboard(void) |
| 233 | { |
| 234 | puts(sysinfo.board_string); |
| 235 | return 0; |
| 236 | } |
| 237 | |
Steve Sakoman | 2ad853c | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 238 | /* |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 239 | * get_device_type(): tell if GP/HS/EMU/TST |
| 240 | */ |
| 241 | u32 get_device_type(void) |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 242 | { |
Lokesh Vutla | c43c833 | 2013-02-04 04:22:04 +0000 | [diff] [blame] | 243 | return (readl((*ctrl)->control_status) & |
SRICHARAN R | c1fa3c3 | 2012-03-12 02:25:43 +0000 | [diff] [blame] | 244 | (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 245 | } |
| 246 | |
Masahiro Yamada | 365475e | 2014-02-13 18:30:26 +0900 | [diff] [blame] | 247 | #if defined(CONFIG_DISPLAY_CPUINFO) |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 248 | /* |
| 249 | * Print CPU information |
| 250 | */ |
| 251 | int print_cpuinfo(void) |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 252 | { |
Andreas Müller | 761ca31 | 2012-01-04 15:26:24 +0000 | [diff] [blame] | 253 | puts("CPU : "); |
| 254 | omap_rev_string(); |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 255 | |
| 256 | return 0; |
| 257 | } |
Masahiro Yamada | 365475e | 2014-02-13 18:30:26 +0900 | [diff] [blame] | 258 | #endif |