Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 3 | * Common functions for OMAP4/5 based boards |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Author : |
| 9 | * Aneesh V <aneesh@ti.com> |
| 10 | * Steve Sakoman <steve@sakoman.com> |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | #include <common.h> |
Tom Rini | 47f7bca | 2012-08-13 12:03:19 -0700 | [diff] [blame] | 31 | #include <spl.h> |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 32 | #include <asm/arch/sys_proto.h> |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 33 | #include <asm/sizes.h> |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 34 | #include <asm/emif.h> |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 35 | #include <asm/omap_common.h> |
Lokesh Vutla | d4d986e | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 36 | #include <linux/compiler.h> |
R Sricharan | de63ac2 | 2013-03-04 20:04:45 +0000 | [diff] [blame^] | 37 | #include <asm/cache.h> |
| 38 | #include <asm/system.h> |
| 39 | |
| 40 | #define ARMV7_DCACHE_WRITEBACK 0xe |
| 41 | #define ARMV7_DOMAIN_CLIENT 1 |
| 42 | #define ARMV7_DOMAIN_MASK (0x3 << 0) |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 43 | |
Nishanth Menon | 93e3568 | 2010-11-19 11:19:40 -0500 | [diff] [blame] | 44 | DECLARE_GLOBAL_DATA_PTR; |
| 45 | |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 46 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) |
| 47 | { |
| 48 | int i; |
| 49 | struct pad_conf_entry *pad = (struct pad_conf_entry *) array; |
| 50 | |
| 51 | for (i = 0; i < size; i++, pad++) |
| 52 | writew(pad->val, base + pad->offset); |
| 53 | } |
| 54 | |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 55 | static void set_mux_conf_regs(void) |
| 56 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 57 | switch (omap_hw_init_context()) { |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 58 | case OMAP_INIT_CONTEXT_SPL: |
| 59 | set_muxconf_regs_essential(); |
| 60 | break; |
| 61 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 62 | #ifdef CONFIG_SYS_ENABLE_PADS_ALL |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 63 | set_muxconf_regs_non_essential(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 64 | #endif |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 65 | break; |
| 66 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 67 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
| 68 | set_muxconf_regs_essential(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 69 | #ifdef CONFIG_SYS_ENABLE_PADS_ALL |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 70 | set_muxconf_regs_non_essential(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 71 | #endif |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 72 | break; |
| 73 | } |
| 74 | } |
| 75 | |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 76 | u32 cortex_rev(void) |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 77 | { |
| 78 | |
| 79 | unsigned int rev; |
| 80 | |
| 81 | /* Read Main ID Register (MIDR) */ |
| 82 | asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); |
| 83 | |
| 84 | return rev; |
| 85 | } |
| 86 | |
Andreas Müller | 761ca31 | 2012-01-04 15:26:24 +0000 | [diff] [blame] | 87 | void omap_rev_string(void) |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 88 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 89 | u32 omap_rev = omap_revision(); |
Lokesh Vutla | de62688 | 2013-02-12 21:29:03 +0000 | [diff] [blame] | 90 | u32 soc_variant = (omap_rev & 0xF0000000) >> 28; |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 91 | u32 omap_variant = (omap_rev & 0xFFFF0000) >> 16; |
| 92 | u32 major_rev = (omap_rev & 0x00000F00) >> 8; |
| 93 | u32 minor_rev = (omap_rev & 0x000000F0) >> 4; |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 94 | |
Lokesh Vutla | de62688 | 2013-02-12 21:29:03 +0000 | [diff] [blame] | 95 | if (soc_variant) |
| 96 | printf("OMAP"); |
| 97 | else |
| 98 | printf("DRA"); |
| 99 | printf("%x ES%x.%x\n", omap_variant, major_rev, |
| 100 | minor_rev); |
Aneesh V | ad577c8 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 101 | } |
| 102 | |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 103 | #ifdef CONFIG_SPL_BUILD |
| 104 | static void init_boot_params(void) |
| 105 | { |
| 106 | boot_params_ptr = (u32 *) &boot_params; |
| 107 | } |
Tom Rini | 861a86f | 2012-08-13 11:37:56 -0700 | [diff] [blame] | 108 | |
| 109 | void spl_display_print(void) |
| 110 | { |
| 111 | omap_rev_string(); |
| 112 | } |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 113 | #endif |
| 114 | |
Lokesh Vutla | d4d986e | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 115 | void __weak srcomp_enable(void) |
| 116 | { |
| 117 | } |
| 118 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 119 | /* |
| 120 | * Routine: s_init |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 121 | * Description: Does early system init of watchdog, muxing, andclocks |
| 122 | * Watchdog disable is done always. For the rest what gets done |
| 123 | * depends on the boot mode in which this function is executed |
| 124 | * 1. s_init of SPL running from SRAM |
| 125 | * 2. s_init of U-Boot running from FLASH |
| 126 | * 3. s_init of U-Boot loaded to SDRAM by SPL |
| 127 | * 4. s_init of U-Boot loaded to SDRAM by ROM code using the |
| 128 | * Configuration Header feature |
| 129 | * Please have a look at the respective functions to see what gets |
| 130 | * done in each of these cases |
| 131 | * This function is called with SRAM stack. |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 132 | */ |
| 133 | void s_init(void) |
| 134 | { |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 135 | init_omap_revision(); |
SRICHARAN R | 01b753f | 2013-02-04 04:22:00 +0000 | [diff] [blame] | 136 | hw_data_init(); |
| 137 | |
Lokesh Vutla | 38f25b1 | 2012-05-29 19:26:43 +0000 | [diff] [blame] | 138 | #ifdef CONFIG_SPL_BUILD |
| 139 | if (warm_reset() && (omap_revision() <= OMAP5430_ES1_0)) |
| 140 | force_emif_self_refresh(); |
| 141 | #endif |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 142 | watchdog_init(); |
Aneesh V | 469ec1e | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 143 | set_mux_conf_regs(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 144 | #ifdef CONFIG_SPL_BUILD |
Lokesh Vutla | d4d986e | 2013-02-12 01:33:45 +0000 | [diff] [blame] | 145 | srcomp_enable(); |
Simon Schwarz | 63ffcfc | 2011-09-14 15:14:46 -0400 | [diff] [blame] | 146 | setup_clocks_for_console(); |
Tom Rini | 6507f13 | 2012-08-22 15:31:05 -0700 | [diff] [blame] | 147 | |
| 148 | gd = &gdata; |
| 149 | |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 150 | preloader_console_init(); |
Aneesh V | 4ecfcfa | 2011-09-08 11:05:56 -0400 | [diff] [blame] | 151 | do_io_settings(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 152 | #endif |
Aneesh V | 3776801 | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 153 | prcm_init(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 154 | #ifdef CONFIG_SPL_BUILD |
Dechesne, Nicolas | f590217 | 2012-01-31 07:35:40 +0000 | [diff] [blame] | 155 | timer_init(); |
| 156 | |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 157 | /* For regular u-boot sdram_init() is called from dram_init() */ |
| 158 | sdram_init(); |
Sricharan | 78f455c | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 159 | init_boot_params(); |
Aneesh V | bcae721 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 160 | #endif |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 161 | } |
| 162 | |
| 163 | /* |
| 164 | * Routine: wait_for_command_complete |
| 165 | * Description: Wait for posting to finish on watchdog |
| 166 | */ |
| 167 | void wait_for_command_complete(struct watchdog *wd_base) |
| 168 | { |
| 169 | int pending = 1; |
| 170 | do { |
| 171 | pending = readl(&wd_base->wwps); |
| 172 | } while (pending); |
| 173 | } |
| 174 | |
| 175 | /* |
| 176 | * Routine: watchdog_init |
| 177 | * Description: Shut down watch dogs |
| 178 | */ |
| 179 | void watchdog_init(void) |
| 180 | { |
| 181 | struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; |
| 182 | |
| 183 | writel(WD_UNLOCK1, &wd2_base->wspr); |
| 184 | wait_for_command_complete(wd2_base); |
| 185 | writel(WD_UNLOCK2, &wd2_base->wspr); |
| 186 | } |
| 187 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 188 | |
| 189 | /* |
| 190 | * This function finds the SDRAM size available in the system |
| 191 | * based on DMM section configurations |
| 192 | * This is needed because the size of memory installed may be |
| 193 | * different on different versions of the board |
| 194 | */ |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 195 | u32 omap_sdram_size(void) |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 196 | { |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 197 | u32 section, i, valid; |
| 198 | u64 sdram_start = 0, sdram_end = 0, addr, |
| 199 | size, total_size = 0, trap_size = 0; |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 200 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 201 | for (i = 0; i < 4; i++) { |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 202 | section = __raw_readl(DMM_BASE + i*4); |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 203 | valid = (section & EMIF_SDRC_ADDRSPC_MASK) >> |
| 204 | (EMIF_SDRC_ADDRSPC_SHIFT); |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 205 | addr = section & EMIF_SYS_ADDR_MASK; |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 206 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 207 | /* See if the address is valid */ |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 208 | if ((addr >= DRAM_ADDR_SPACE_START) && |
| 209 | (addr < DRAM_ADDR_SPACE_END)) { |
| 210 | size = ((section & EMIF_SYS_SIZE_MASK) >> |
| 211 | EMIF_SYS_SIZE_SHIFT); |
| 212 | size = 1 << size; |
| 213 | size *= SZ_16M; |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 214 | |
| 215 | if (valid != DMM_SDRC_ADDR_SPC_INVALID) { |
| 216 | if (!sdram_start || (addr < sdram_start)) |
| 217 | sdram_start = addr; |
| 218 | if (!sdram_end || ((addr + size) > sdram_end)) |
| 219 | sdram_end = addr + size; |
| 220 | } else { |
| 221 | trap_size = size; |
| 222 | } |
| 223 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 224 | } |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 225 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 226 | } |
SRICHARAN R | e06e914 | 2012-05-17 00:12:06 +0000 | [diff] [blame] | 227 | total_size = (sdram_end - sdram_start) - (trap_size); |
Sricharan | bb772a5 | 2011-11-15 09:50:00 -0500 | [diff] [blame] | 228 | |
Aneesh V | 7ca3f9c | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 229 | return total_size; |
| 230 | } |
| 231 | |
| 232 | |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 233 | /* |
| 234 | * Routine: dram_init |
| 235 | * Description: sets uboots idea of sdram size |
| 236 | */ |
| 237 | int dram_init(void) |
| 238 | { |
Aneesh V | 2ae610f | 2011-07-21 09:10:09 -0400 | [diff] [blame] | 239 | sdram_init(); |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 240 | gd->ram_size = omap_sdram_size(); |
Steve Sakoman | d34efc7 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * Print board information |
| 246 | */ |
| 247 | int checkboard(void) |
| 248 | { |
| 249 | puts(sysinfo.board_string); |
| 250 | return 0; |
| 251 | } |
| 252 | |
Steve Sakoman | 2ad853c | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 253 | /* |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 254 | * get_device_type(): tell if GP/HS/EMU/TST |
| 255 | */ |
| 256 | u32 get_device_type(void) |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 257 | { |
Lokesh Vutla | c43c833 | 2013-02-04 04:22:04 +0000 | [diff] [blame] | 258 | return (readl((*ctrl)->control_status) & |
SRICHARAN R | c1fa3c3 | 2012-03-12 02:25:43 +0000 | [diff] [blame] | 259 | (DEVICE_TYPE_MASK)) >> DEVICE_TYPE_SHIFT; |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 260 | } |
| 261 | |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 262 | /* |
| 263 | * Print CPU information |
| 264 | */ |
| 265 | int print_cpuinfo(void) |
Aneesh V | 8b457fa | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 266 | { |
Andreas Müller | 761ca31 | 2012-01-04 15:26:24 +0000 | [diff] [blame] | 267 | puts("CPU : "); |
| 268 | omap_rev_string(); |
Sricharan | 508a58f | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 269 | |
| 270 | return 0; |
| 271 | } |
Aneesh V | 13d4f9b | 2011-08-11 04:35:43 +0000 | [diff] [blame] | 272 | #ifndef CONFIG_SYS_DCACHE_OFF |
| 273 | void enable_caches(void) |
| 274 | { |
| 275 | /* Enable D-cache. I-cache is already enabled in start.S */ |
| 276 | dcache_enable(); |
| 277 | } |
R Sricharan | de63ac2 | 2013-03-04 20:04:45 +0000 | [diff] [blame^] | 278 | |
| 279 | void dram_bank_mmu_setup(int bank) |
| 280 | { |
| 281 | bd_t *bd = gd->bd; |
| 282 | int i; |
| 283 | |
| 284 | u32 start = bd->bi_dram[bank].start >> 20; |
| 285 | u32 size = bd->bi_dram[bank].size >> 20; |
| 286 | u32 end = start + size; |
| 287 | |
| 288 | debug("%s: bank: %d\n", __func__, bank); |
| 289 | for (i = start; i < end; i++) |
| 290 | set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); |
| 291 | |
| 292 | } |
| 293 | |
| 294 | void arm_init_domains(void) |
| 295 | { |
| 296 | u32 reg; |
| 297 | |
| 298 | reg = get_dacr(); |
| 299 | /* |
| 300 | * Set DOMAIN to client access so that all permissions |
| 301 | * set in pagetables are validated by the mmu. |
| 302 | */ |
| 303 | reg &= ~ARMV7_DOMAIN_MASK; |
| 304 | reg |= ARMV7_DOMAIN_CLIENT; |
| 305 | set_dacr(reg); |
| 306 | } |
Aneesh V | 13d4f9b | 2011-08-11 04:35:43 +0000 | [diff] [blame] | 307 | #endif |