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Dave Liu5f820432006-11-03 19:33:44 -06001/*
Jerry Huangd37be072011-11-03 14:46:12 +08002 * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
Dave Liu5f820432006-11-03 19:33:44 -06003 * Dave Liu <daveliu@freescale.com>
Dave Liu5f820432006-11-03 19:33:44 -06004 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Dave Liu5f820432006-11-03 19:33:44 -06006 */
7
8#include <common.h>
9#include <ioports.h>
10#include <mpc83xx.h>
11#include <i2c.h>
Dave Liu5f820432006-11-03 19:33:44 -060012#include <miiphy.h>
Andy Fleming865ff852011-04-13 00:37:12 -050013#include <phy.h>
Dave Liu5f820432006-11-03 19:33:44 -060014#if defined(CONFIG_PCI)
15#include <pci.h>
16#endif
Dave Liu5f820432006-11-03 19:33:44 -060017#include <spd_sdram.h>
Dave Liu5f820432006-11-03 19:33:44 -060018#include <asm/mmu.h>
Anton Vorontsov89da44c2009-09-16 23:21:59 +040019#include <asm/io.h>
Kumar Galaa1964ea2010-09-30 09:15:03 -050020#include <asm/fsl_enet.h>
Jerry Huangd37be072011-11-03 14:46:12 +080021#include <asm/mmu.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060022#if defined(CONFIG_OF_LIBFDT)
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040023#include <libfdt.h>
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040024#endif
Anton Vorontsovda6eea02009-09-16 23:22:08 +040025#include <hwconfig.h>
26#include <fdt_support.h>
Tony Li14778582007-08-17 10:35:59 +080027#if defined(CONFIG_PQ_MDS_PIB)
Kim Phillipse58fe952007-08-16 22:53:09 -050028#include "../common/pq-mds-pib.h"
Tony Li14778582007-08-17 10:35:59 +080029#endif
Anton Vorontsov89da44c2009-09-16 23:21:59 +040030#include "../../../drivers/qe/uec.h"
Dave Liu5f820432006-11-03 19:33:44 -060031
Dave Liu7737d5c2006-11-03 12:11:15 -060032const qe_iop_conf_t qe_iop_conf_tab[] = {
33 /* GETH1 */
34 {0, 3, 1, 0, 1}, /* TxD0 */
35 {0, 4, 1, 0, 1}, /* TxD1 */
36 {0, 5, 1, 0, 1}, /* TxD2 */
37 {0, 6, 1, 0, 1}, /* TxD3 */
38 {1, 6, 1, 0, 3}, /* TxD4 */
39 {1, 7, 1, 0, 1}, /* TxD5 */
40 {1, 9, 1, 0, 2}, /* TxD6 */
41 {1, 10, 1, 0, 2}, /* TxD7 */
42 {0, 9, 2, 0, 1}, /* RxD0 */
43 {0, 10, 2, 0, 1}, /* RxD1 */
44 {0, 11, 2, 0, 1}, /* RxD2 */
45 {0, 12, 2, 0, 1}, /* RxD3 */
46 {0, 13, 2, 0, 1}, /* RxD4 */
47 {1, 1, 2, 0, 2}, /* RxD5 */
48 {1, 0, 2, 0, 2}, /* RxD6 */
49 {1, 4, 2, 0, 2}, /* RxD7 */
50 {0, 7, 1, 0, 1}, /* TX_EN */
51 {0, 8, 1, 0, 1}, /* TX_ER */
52 {0, 15, 2, 0, 1}, /* RX_DV */
53 {0, 16, 2, 0, 1}, /* RX_ER */
54 {0, 0, 2, 0, 1}, /* RX_CLK */
55 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
56 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
57 /* GETH2 */
58 {0, 17, 1, 0, 1}, /* TxD0 */
59 {0, 18, 1, 0, 1}, /* TxD1 */
60 {0, 19, 1, 0, 1}, /* TxD2 */
61 {0, 20, 1, 0, 1}, /* TxD3 */
62 {1, 2, 1, 0, 1}, /* TxD4 */
63 {1, 3, 1, 0, 2}, /* TxD5 */
64 {1, 5, 1, 0, 3}, /* TxD6 */
65 {1, 8, 1, 0, 3}, /* TxD7 */
66 {0, 23, 2, 0, 1}, /* RxD0 */
67 {0, 24, 2, 0, 1}, /* RxD1 */
68 {0, 25, 2, 0, 1}, /* RxD2 */
69 {0, 26, 2, 0, 1}, /* RxD3 */
70 {0, 27, 2, 0, 1}, /* RxD4 */
71 {1, 12, 2, 0, 2}, /* RxD5 */
72 {1, 13, 2, 0, 3}, /* RxD6 */
73 {1, 11, 2, 0, 2}, /* RxD7 */
74 {0, 21, 1, 0, 1}, /* TX_EN */
75 {0, 22, 1, 0, 1}, /* TX_ER */
76 {0, 29, 2, 0, 1}, /* RX_DV */
77 {0, 30, 2, 0, 1}, /* RX_ER */
78 {0, 31, 2, 0, 1}, /* RX_CLK */
79 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
80 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
81
82 {0, 1, 3, 0, 2}, /* MDIO */
83 {0, 2, 1, 0, 1}, /* MDC */
84
Anton Vorontsov651d96f2007-11-14 18:54:53 +030085 {5, 0, 1, 0, 2}, /* UART2_SOUT */
86 {5, 1, 2, 0, 3}, /* UART2_CTS */
87 {5, 2, 1, 0, 1}, /* UART2_RTS */
88 {5, 3, 2, 0, 2}, /* UART2_SIN */
89
Dave Liu7737d5c2006-11-03 12:11:15 -060090 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
91};
92
Anton Vorontsov89da44c2009-09-16 23:21:59 +040093/* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
94static int board_handle_erratum2(void)
95{
96 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
97
98 return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
99 REVID_MINOR(immr->sysconf.spridr) == 1;
100}
101
Dave Liu5f820432006-11-03 19:33:44 -0600102int board_early_init_f(void)
103{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
Anton Vorontsov89da44c2009-09-16 23:21:59 +0400105 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
Dave Liu5f820432006-11-03 19:33:44 -0600106
107 /* Enable flash write */
108 bcsr[0xa] &= ~0x04;
109
Kim Phillipse5c4ade2008-03-28 10:19:07 -0500110 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
111 if (REVID_MAJOR(immr->sysconf.spridr) == 2)
Kim Phillips3fc0bd12007-02-14 19:50:53 -0600112 bcsr[0xe] = 0x30;
113
Anton Vorontsov651d96f2007-11-14 18:54:53 +0300114 /* Enable second UART */
115 bcsr[0x9] &= ~0x01;
116
Anton Vorontsov89da44c2009-09-16 23:21:59 +0400117 if (board_handle_erratum2()) {
118 void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
119
120 /*
121 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
122 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
123 */
124 setbits_be32(immap, 0x0c003000);
125
126 /*
127 * IMMR + 0x14AC[20:27] = 10101010
128 * (data delay for both UCC's)
129 */
130 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
131 }
Dave Liu5f820432006-11-03 19:33:44 -0600132 return 0;
133}
134
Tony Li14778582007-08-17 10:35:59 +0800135int board_early_init_r(void)
136{
Jerry Huangd37be072011-11-03 14:46:12 +0800137 gd_t *gd;
Tony Li14778582007-08-17 10:35:59 +0800138#ifdef CONFIG_PQ_MDS_PIB
139 pib_init();
140#endif
Jerry Huangd37be072011-11-03 14:46:12 +0800141 /*
142 * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
143 * So re-setup PCI MEM space used BAT5 after relocated to DDR
144 */
145 gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
146 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
147 write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
148 write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
149 }
150
Tony Li14778582007-08-17 10:35:59 +0800151 return 0;
152}
153
Anton Vorontsov89da44c2009-09-16 23:21:59 +0400154#ifdef CONFIG_UEC_ETH
155static uec_info_t uec_info[] = {
156#ifdef CONFIG_UEC_ETH1
157 STD_UEC_INFO(1),
158#endif
159#ifdef CONFIG_UEC_ETH2
160 STD_UEC_INFO(2),
161#endif
162};
163
164int board_eth_init(bd_t *bd)
165{
166 if (board_handle_erratum2()) {
167 int i;
168
Kim Phillipsb86c7702011-11-15 22:59:52 +0000169 for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
Andy Fleming865ff852011-04-13 00:37:12 -0500170 uec_info[i].enet_interface_type =
171 PHY_INTERFACE_MODE_RGMII_RXID;
172 uec_info[i].speed = SPEED_1000;
Kim Phillipsb86c7702011-11-15 22:59:52 +0000173 }
Anton Vorontsov89da44c2009-09-16 23:21:59 +0400174 }
175 return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
176}
177#endif /* CONFIG_UEC_ETH */
178
Peter Tyser9adda542009-06-30 17:15:50 -0500179#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Dave Liu5f820432006-11-03 19:33:44 -0600180extern void ddr_enable_ecc(unsigned int dram_size);
181#endif
182int fixed_sdram(void);
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400183static int sdram_init(unsigned int base);
Dave Liu5f820432006-11-03 19:33:44 -0600184
Becky Bruce9973e3c2008-06-09 16:03:40 -0500185phys_size_t initdram(int board_type)
Dave Liu5f820432006-11-03 19:33:44 -0600186{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600188 u32 msize = 0;
Anton Vorontsov034477b2009-09-16 23:21:57 +0400189 u32 lbc_sdram_size;
Dave Liu5f820432006-11-03 19:33:44 -0600190
191 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
192 return -1;
193
194 /* DDR SDRAM - Main SODIMM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
Dave Liu5f820432006-11-03 19:33:44 -0600196#if defined(CONFIG_SPD_EEPROM)
197 msize = spd_sdram();
198#else
199 msize = fixed_sdram();
200#endif
201
Peter Tyser9adda542009-06-30 17:15:50 -0500202#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
Dave Liu5f820432006-11-03 19:33:44 -0600203 /*
204 * Initialize DDR ECC byte
205 */
206 ddr_enable_ecc(msize * 1024 * 1024);
207#endif
208 /*
209 * Initialize SDRAM if it is on local bus.
210 */
Anton Vorontsov034477b2009-09-16 23:21:57 +0400211 lbc_sdram_size = sdram_init(msize * 1024 * 1024);
212 if (!msize)
213 msize = lbc_sdram_size;
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500214
Dave Liu5f820432006-11-03 19:33:44 -0600215 /* return total bus SDRAM size(bytes) -- DDR */
216 return (msize * 1024 * 1024);
217}
218
219#if !defined(CONFIG_SPD_EEPROM)
220/*************************************************************************
221 * fixed sdram init -- doesn't use serial presence detect.
222 ************************************************************************/
223int fixed_sdram(void)
224{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
Joe Hershberger2e651b22011-10-11 23:57:31 -0500226 u32 msize = CONFIG_SYS_DDR_SIZE;
227 u32 ddr_size = msize << 20;
228 u32 ddr_size_log2 = __ilog2(ddr_size);
229 u32 half_ddr_size = ddr_size >> 1;
Dave Liu5f820432006-11-03 19:33:44 -0600230
Joe Hershberger2e651b22011-10-11 23:57:31 -0500231 im->sysconf.ddrlaw[0].bar =
232 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Dave Liu5f820432006-11-03 19:33:44 -0600233 im->sysconf.ddrlaw[0].ar =
Joe Hershberger2e651b22011-10-11 23:57:31 -0500234 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#if (CONFIG_SYS_DDR_SIZE != 256)
Dave Liu5f820432006-11-03 19:33:44 -0600236#warning Currenly any ddr size other than 256 is not supported
237#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +0800238#ifdef CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
240 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
241 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
242 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
243 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
244 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
245 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
246 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
247 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
248 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
249 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
250 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800251#else
Dave Liu5f820432006-11-03 19:33:44 -0600252
Joe Hershberger2e651b22011-10-11 23:57:31 -0500253#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
254#warning Chip select bounds is only configurable in 16MB increments
255#endif
256 im->ddr.csbnds[0].csbnds =
257 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
258 (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
259 CSBNDS_EA_SHIFT) & CSBNDS_EA);
260 im->ddr.csbnds[1].csbnds =
261 (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
262 CSBNDS_SA_SHIFT) & CSBNDS_SA) |
263 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
264 CSBNDS_EA_SHIFT) & CSBNDS_EA);
265
266 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
267 im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
268
269 im->ddr.cs_config[2] = 0;
270 im->ddr.cs_config[3] = 0;
Dave Liu5f820432006-11-03 19:33:44 -0600271
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
273 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
274 im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
Dave Liu5f820432006-11-03 19:33:44 -0600275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
277 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800278#endif
Dave Liu5f820432006-11-03 19:33:44 -0600279 udelay(200);
280 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
281
282 return msize;
283}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#endif /*!CONFIG_SYS_SPD_EEPROM */
Dave Liu5f820432006-11-03 19:33:44 -0600285
286int checkboard(void)
287{
288 puts("Board: Freescale MPC8360EMDS\n");
289 return 0;
290}
291
292/*
293 * if MPC8360EMDS is soldered with SDRAM
294 */
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400295#ifdef CONFIG_SYS_LB_SDRAM
Dave Liu5f820432006-11-03 19:33:44 -0600296/*
297 * Initialize SDRAM memory on the Local Bus.
298 */
299
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400300static int sdram_init(unsigned int base)
Dave Liu5f820432006-11-03 19:33:44 -0600301{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500303 fsl_lbc_t *lbc = LBC_BASE_ADDR;
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400304 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
305 int rem = base % sdram_size;
306 uint *sdram_addr;
Dave Liu5f820432006-11-03 19:33:44 -0600307
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400308 /* window base address should be aligned to the window size */
309 if (rem)
310 base = base - rem + sdram_size;
311
Jerry Huangd37be072011-11-03 14:46:12 +0800312 /*
313 * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
314 * After relocated to DDR, reuse BAT5 for PCI MEM space
315 */
316 if (base > CONFIG_MAX_MEM_MAPPED) {
317 unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
318 unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
319
320 /* Setup the BAT6 for SDRAM */
321 write_bat(DBAT6, batu, batl);
322 write_bat(IBAT6, batu, batl);
323 }
324
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400325 sdram_addr = (uint *)base;
Dave Liu5f820432006-11-03 19:33:44 -0600326 /*
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400327 * Setup SDRAM Base and Option Registers
Dave Liu5f820432006-11-03 19:33:44 -0600328 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500329 set_lbc_br(2, base | CONFIG_SYS_BR2);
330 set_lbc_or(2, CONFIG_SYS_OR2);
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400331 immap->sysconf.lblaw[2].bar = base;
332 immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
333
Dave Liu5f820432006-11-03 19:33:44 -0600334 /*setup mtrpt, lsrt and lbcr for LB bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
336 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
337 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Dave Liu5f820432006-11-03 19:33:44 -0600338 asm("sync");
339
340 /*
341 * Configure the SDRAM controller Machine Mode Register.
342 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
344 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
Dave Liu5f820432006-11-03 19:33:44 -0600345 asm("sync");
346 *sdram_addr = 0xff;
347 udelay(100);
348
349 /*
350 * We need do 8 times auto refresh operation.
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
Dave Liu5f820432006-11-03 19:33:44 -0600353 asm("sync");
354 *sdram_addr = 0xff; /* 1 times */
355 udelay(100);
356 *sdram_addr = 0xff; /* 2 times */
357 udelay(100);
358 *sdram_addr = 0xff; /* 3 times */
359 udelay(100);
360 *sdram_addr = 0xff; /* 4 times */
361 udelay(100);
362 *sdram_addr = 0xff; /* 5 times */
363 udelay(100);
364 *sdram_addr = 0xff; /* 6 times */
365 udelay(100);
366 *sdram_addr = 0xff; /* 7 times */
367 udelay(100);
368 *sdram_addr = 0xff; /* 8 times */
369 udelay(100);
370
371 /* Mode register write operation */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Dave Liu5f820432006-11-03 19:33:44 -0600373 asm("sync");
374 *(sdram_addr + 0xcc) = 0xff;
375 udelay(100);
376
377 /* Normal operation */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
Dave Liu5f820432006-11-03 19:33:44 -0600379 asm("sync");
380 *sdram_addr = 0xff;
381 udelay(100);
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400382
383 /*
384 * In non-aligned case we don't [normally] use that memory because
385 * there is a hole.
386 */
387 if (rem)
388 return 0;
389 return CONFIG_SYS_LBC_SDRAM_SIZE;
Dave Liu5f820432006-11-03 19:33:44 -0600390}
391#else
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400392static int sdram_init(unsigned int base) { return 0; }
Dave Liu5f820432006-11-03 19:33:44 -0600393#endif
394
Kim Phillips3fde9e82007-08-15 22:30:33 -0500395#if defined(CONFIG_OF_BOARD_SETUP)
Anton Vorontsovda6eea02009-09-16 23:22:08 +0400396static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
397{
398 if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
399 return;
400
401 do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
402 "peripheral", sizeof("peripheral"), 1);
403}
404
Kim Phillips3fde9e82007-08-15 22:30:33 -0500405void ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600406{
Kim Phillips3fde9e82007-08-15 22:30:33 -0500407 ft_cpu_setup(blob, bd);
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400408#ifdef CONFIG_PCI
409 ft_pci_setup(blob, bd);
410#endif
Anton Vorontsovda6eea02009-09-16 23:22:08 +0400411 ft_board_fixup_qe_usb(blob, bd);
Kim Phillips24f86842007-11-09 14:28:08 -0600412 /*
413 * mpc8360ea pb mds errata 2: RGMII timing
414 * if on mpc8360ea rev. 2.1,
415 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
416 */
Anton Vorontsov89da44c2009-09-16 23:21:59 +0400417 if (board_handle_erratum2()) {
Kim Phillips24f86842007-11-09 14:28:08 -0600418 int nodeoffset;
Kim Phillipsf6020822007-12-10 14:16:22 -0600419 const char *prop;
Kim Phillips363eea92008-01-15 09:51:12 -0600420 int path;
Kim Phillips24f86842007-11-09 14:28:08 -0600421
Kim Phillipsf09880e2008-01-14 16:14:46 -0600422 nodeoffset = fdt_path_offset(blob, "/aliases");
Kim Phillips24f86842007-11-09 14:28:08 -0600423 if (nodeoffset >= 0) {
Kim Phillips5b8bc602007-12-20 14:09:22 -0600424#if defined(CONFIG_HAS_ETH0)
425 /* fixup UCC 1 if using rgmii-id mode */
Kim Phillips363eea92008-01-15 09:51:12 -0600426 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
427 if (prop) {
428 path = fdt_path_offset(blob, prop);
Kim Phillipsf09880e2008-01-14 16:14:46 -0600429 prop = fdt_getprop(blob, path,
Wolfgang Denk93e14592013-10-04 17:43:24 +0200430 "phy-connection-type", 0);
Kim Phillips5b8bc602007-12-20 14:09:22 -0600431 if (prop && (strcmp(prop, "rgmii-id") == 0))
Kumar Galaa1964ea2010-09-30 09:15:03 -0500432 fdt_fixup_phy_connection(blob, path,
Andy Fleming865ff852011-04-13 00:37:12 -0500433 PHY_INTERFACE_MODE_RGMII_RXID);
Kim Phillips5b8bc602007-12-20 14:09:22 -0600434 }
435#endif
436#if defined(CONFIG_HAS_ETH1)
437 /* fixup UCC 2 if using rgmii-id mode */
Kim Phillips363eea92008-01-15 09:51:12 -0600438 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
439 if (prop) {
440 path = fdt_path_offset(blob, prop);
Kim Phillipsf09880e2008-01-14 16:14:46 -0600441 prop = fdt_getprop(blob, path,
Wolfgang Denk93e14592013-10-04 17:43:24 +0200442 "phy-connection-type", 0);
Kim Phillips5b8bc602007-12-20 14:09:22 -0600443 if (prop && (strcmp(prop, "rgmii-id") == 0))
Kumar Galaa1964ea2010-09-30 09:15:03 -0500444 fdt_fixup_phy_connection(blob, path,
Andy Fleming865ff852011-04-13 00:37:12 -0500445 PHY_INTERFACE_MODE_RGMII_RXID);
Kim Phillips5b8bc602007-12-20 14:09:22 -0600446 }
447#endif
Kim Phillips24f86842007-11-09 14:28:08 -0600448 }
449 }
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600450}
Kim Phillips3fde9e82007-08-15 22:30:33 -0500451#endif