Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| 4 | * Michal Simek <michal.simek@xilinx.com> |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <common.h> |
Simon Glass | 049f8d6 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 8 | #include <time.h> |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 9 | #include <asm/arch/hardware.h> |
| 10 | #include <asm/arch/sys_proto.h> |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 11 | #include <asm/armv8/mmu.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame^] | 12 | #include <asm/cache.h> |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 13 | #include <asm/io.h> |
Ibai Erkiaga | 009ab7b | 2019-09-27 11:37:01 +0100 | [diff] [blame] | 14 | #include <zynqmp_firmware.h> |
Ovidiu Panait | 6184858 | 2020-03-29 20:57:40 +0300 | [diff] [blame] | 15 | #include <asm/cache.h> |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 16 | |
| 17 | #define ZYNQ_SILICON_VER_MASK 0xF000 |
| 18 | #define ZYNQ_SILICON_VER_SHIFT 12 |
| 19 | |
| 20 | DECLARE_GLOBAL_DATA_PTR; |
| 21 | |
Nitin Jain | 0678941 | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 22 | /* |
| 23 | * Number of filled static entries and also the first empty |
| 24 | * slot in zynqmp_mem_map. |
| 25 | */ |
| 26 | #define ZYNQMP_MEM_MAP_USED 4 |
| 27 | |
Siva Durga Prasad Paladugu | 3b644a3 | 2018-01-12 15:35:46 +0530 | [diff] [blame] | 28 | #if !defined(CONFIG_ZYNQMP_NO_DDR) |
Nitin Jain | 0678941 | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 29 | #define DRAM_BANKS CONFIG_NR_DRAM_BANKS |
| 30 | #else |
| 31 | #define DRAM_BANKS 0 |
Siva Durga Prasad Paladugu | 3b644a3 | 2018-01-12 15:35:46 +0530 | [diff] [blame] | 32 | #endif |
Nitin Jain | 0678941 | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 33 | |
| 34 | #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) |
| 35 | #define TCM_MAP 1 |
| 36 | #else |
| 37 | #define TCM_MAP 0 |
| 38 | #endif |
| 39 | |
| 40 | /* +1 is end of list which needs to be empty */ |
| 41 | #define ZYNQMP_MEM_MAP_MAX (ZYNQMP_MEM_MAP_USED + DRAM_BANKS + TCM_MAP + 1) |
| 42 | |
| 43 | static struct mm_region zynqmp_mem_map[ZYNQMP_MEM_MAP_MAX] = { |
Siva Durga Prasad Paladugu | 3b644a3 | 2018-01-12 15:35:46 +0530 | [diff] [blame] | 44 | { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 45 | .virt = 0x80000000UL, |
| 46 | .phys = 0x80000000UL, |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 47 | .size = 0x70000000UL, |
| 48 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 49 | PTE_BLOCK_NON_SHARE | |
| 50 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
Nitin Jain | 0678941 | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 51 | }, { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 52 | .virt = 0xf8000000UL, |
| 53 | .phys = 0xf8000000UL, |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 54 | .size = 0x07e00000UL, |
| 55 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 56 | PTE_BLOCK_NON_SHARE | |
| 57 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 58 | }, { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 59 | .virt = 0x400000000UL, |
| 60 | .phys = 0x400000000UL, |
Anders Hedlund | 501fbc6 | 2017-12-19 17:24:41 +0100 | [diff] [blame] | 61 | .size = 0x400000000UL, |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 62 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 63 | PTE_BLOCK_NON_SHARE | |
| 64 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
Nitin Jain | 0678941 | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 65 | }, { |
Anders Hedlund | 501fbc6 | 2017-12-19 17:24:41 +0100 | [diff] [blame] | 66 | .virt = 0x1000000000UL, |
| 67 | .phys = 0x1000000000UL, |
| 68 | .size = 0xf000000000UL, |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 69 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 70 | PTE_BLOCK_NON_SHARE | |
| 71 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 72 | } |
| 73 | }; |
Nitin Jain | 0678941 | 2018-04-20 12:30:40 +0530 | [diff] [blame] | 74 | |
| 75 | void mem_map_fill(void) |
| 76 | { |
| 77 | int banks = ZYNQMP_MEM_MAP_USED; |
| 78 | |
| 79 | #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) |
| 80 | zynqmp_mem_map[banks].virt = 0xffe00000UL; |
| 81 | zynqmp_mem_map[banks].phys = 0xffe00000UL; |
| 82 | zynqmp_mem_map[banks].size = 0x00200000UL; |
| 83 | zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 84 | PTE_BLOCK_INNER_SHARE; |
| 85 | banks = banks + 1; |
| 86 | #endif |
| 87 | |
| 88 | #if !defined(CONFIG_ZYNQMP_NO_DDR) |
| 89 | for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { |
| 90 | /* Zero size means no more DDR that's this is end */ |
| 91 | if (!gd->bd->bi_dram[i].size) |
| 92 | break; |
| 93 | |
| 94 | zynqmp_mem_map[banks].virt = gd->bd->bi_dram[i].start; |
| 95 | zynqmp_mem_map[banks].phys = gd->bd->bi_dram[i].start; |
| 96 | zynqmp_mem_map[banks].size = gd->bd->bi_dram[i].size; |
| 97 | zynqmp_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 98 | PTE_BLOCK_INNER_SHARE; |
| 99 | banks = banks + 1; |
| 100 | } |
| 101 | #endif |
| 102 | } |
| 103 | |
Alexander Graf | 96519f3 | 2016-03-04 01:09:49 +0100 | [diff] [blame] | 104 | struct mm_region *mem_map = zynqmp_mem_map; |
| 105 | |
Michal Simek | 9c152ed | 2016-05-30 10:41:26 +0200 | [diff] [blame] | 106 | u64 get_page_table_size(void) |
| 107 | { |
| 108 | return 0x14000; |
| 109 | } |
| 110 | |
Siva Durga Prasad Paladugu | 5860bc1 | 2018-10-05 15:09:05 +0530 | [diff] [blame] | 111 | #if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP) |
| 112 | void tcm_init(u8 mode) |
Siva Durga Prasad Paladugu | 12ad299 | 2018-10-05 15:09:04 +0530 | [diff] [blame] | 113 | { |
| 114 | puts("WARNING: Initializing TCM overwrites TCM content\n"); |
| 115 | initialize_tcm(mode); |
| 116 | memset((void *)ZYNQMP_TCM_BASE_ADDR, 0, ZYNQMP_TCM_SIZE); |
| 117 | } |
Siva Durga Prasad Paladugu | 5860bc1 | 2018-10-05 15:09:05 +0530 | [diff] [blame] | 118 | #endif |
Siva Durga Prasad Paladugu | 12ad299 | 2018-10-05 15:09:04 +0530 | [diff] [blame] | 119 | |
Siva Durga Prasad Paladugu | 5860bc1 | 2018-10-05 15:09:05 +0530 | [diff] [blame] | 120 | #ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU |
Ovidiu Panait | 6184858 | 2020-03-29 20:57:40 +0300 | [diff] [blame] | 121 | int arm_reserve_mmu(void) |
Siva Durga Prasad Paladugu | e042d36 | 2017-07-13 19:01:11 +0530 | [diff] [blame] | 122 | { |
Siva Durga Prasad Paladugu | 12ad299 | 2018-10-05 15:09:04 +0530 | [diff] [blame] | 123 | tcm_init(TCM_LOCK); |
Siva Durga Prasad Paladugu | e042d36 | 2017-07-13 19:01:11 +0530 | [diff] [blame] | 124 | gd->arch.tlb_size = PGTABLE_SIZE; |
| 125 | gd->arch.tlb_addr = ZYNQMP_TCM_BASE_ADDR; |
| 126 | |
| 127 | return 0; |
| 128 | } |
| 129 | #endif |
| 130 | |
Michal Simek | 0785dfd | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 131 | static unsigned int zynqmp_get_silicon_version_secure(void) |
| 132 | { |
| 133 | u32 ver; |
| 134 | |
| 135 | ver = readl(&csu_base->version); |
| 136 | ver &= ZYNQMP_SILICON_VER_MASK; |
| 137 | ver >>= ZYNQMP_SILICON_VER_SHIFT; |
| 138 | |
| 139 | return ver; |
| 140 | } |
| 141 | |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 142 | unsigned int zynqmp_get_silicon_version(void) |
| 143 | { |
Michal Simek | 0785dfd | 2015-11-05 08:34:35 +0100 | [diff] [blame] | 144 | if (current_el() == 3) |
| 145 | return zynqmp_get_silicon_version_secure(); |
| 146 | |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 147 | gd->cpu_clk = get_tbclk(); |
| 148 | |
| 149 | switch (gd->cpu_clk) { |
| 150 | case 50000000: |
| 151 | return ZYNQMP_CSU_VERSION_QEMU; |
| 152 | } |
| 153 | |
Michal Simek | be6f6af | 2015-08-20 14:01:39 +0200 | [diff] [blame] | 154 | return ZYNQMP_CSU_VERSION_SILICON; |
Michal Simek | 84c7204 | 2015-01-15 10:01:51 +0100 | [diff] [blame] | 155 | } |
Siva Durga Prasad Paladugu | e0752bc | 2017-02-02 01:10:46 +0530 | [diff] [blame] | 156 | |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 157 | static int zynqmp_mmio_rawwrite(const u32 address, |
Siva Durga Prasad Paladugu | e0752bc | 2017-02-02 01:10:46 +0530 | [diff] [blame] | 158 | const u32 mask, |
| 159 | const u32 value) |
| 160 | { |
| 161 | u32 data; |
| 162 | u32 value_local = value; |
Michal Simek | e3c26b8 | 2018-06-13 10:38:33 +0200 | [diff] [blame] | 163 | int ret; |
Siva Durga Prasad Paladugu | e0752bc | 2017-02-02 01:10:46 +0530 | [diff] [blame] | 164 | |
Michal Simek | e3c26b8 | 2018-06-13 10:38:33 +0200 | [diff] [blame] | 165 | ret = zynqmp_mmio_read(address, &data); |
| 166 | if (ret) |
| 167 | return ret; |
| 168 | |
Siva Durga Prasad Paladugu | e0752bc | 2017-02-02 01:10:46 +0530 | [diff] [blame] | 169 | data &= ~mask; |
| 170 | value_local &= mask; |
| 171 | value_local |= data; |
| 172 | writel(value_local, (ulong)address); |
| 173 | return 0; |
| 174 | } |
| 175 | |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 176 | static int zynqmp_mmio_rawread(const u32 address, u32 *value) |
Siva Durga Prasad Paladugu | e0752bc | 2017-02-02 01:10:46 +0530 | [diff] [blame] | 177 | { |
| 178 | *value = readl((ulong)address); |
| 179 | return 0; |
| 180 | } |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 181 | |
| 182 | int zynqmp_mmio_write(const u32 address, |
| 183 | const u32 mask, |
| 184 | const u32 value) |
| 185 | { |
| 186 | if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) |
| 187 | return zynqmp_mmio_rawwrite(address, mask, value); |
Michal Simek | 866225f | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 188 | #if defined(CONFIG_ZYNQMP_FIRMWARE) |
Heinrich Schuchardt | 549d684 | 2017-10-13 01:14:27 +0200 | [diff] [blame] | 189 | else |
Michal Simek | 4036195 | 2019-10-04 15:35:45 +0200 | [diff] [blame] | 190 | return xilinx_pm_request(PM_MMIO_WRITE, address, mask, |
| 191 | value, 0, NULL); |
Michal Simek | 866225f | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 192 | #endif |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 193 | |
| 194 | return -EINVAL; |
| 195 | } |
| 196 | |
| 197 | int zynqmp_mmio_read(const u32 address, u32 *value) |
| 198 | { |
Michal Simek | 866225f | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 199 | u32 ret = -EINVAL; |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 200 | |
| 201 | if (!value) |
Michal Simek | 866225f | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 202 | return ret; |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 203 | |
| 204 | if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { |
| 205 | ret = zynqmp_mmio_rawread(address, value); |
Michal Simek | 866225f | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 206 | } |
| 207 | #if defined(CONFIG_ZYNQMP_FIRMWARE) |
| 208 | else { |
| 209 | u32 ret_payload[PAYLOAD_ARG_CNT]; |
| 210 | |
Michal Simek | 4036195 | 2019-10-04 15:35:45 +0200 | [diff] [blame] | 211 | ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, |
| 212 | 0, ret_payload); |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 213 | *value = ret_payload[1]; |
| 214 | } |
Michal Simek | 866225f | 2019-10-04 15:45:29 +0200 | [diff] [blame] | 215 | #endif |
Siva Durga Prasad Paladugu | cb186e7 | 2017-07-13 19:01:12 +0530 | [diff] [blame] | 216 | |
| 217 | return ret; |
| 218 | } |