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wdenkf8cac652002-08-26 22:36:39 +00001/*
Wolfgang Denk7c803be2008-09-16 18:02:19 +02002 * (C) Copyright 2000-2008
wdenkf8cac652002-08-26 22:36:39 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Heiko Schocher6ed3b9d2010-02-09 15:50:21 +010025#include <hwconfig.h>
wdenkf8cac652002-08-26 22:36:39 +000026#include <mpc8xx.h>
wdenk1c437712004-01-16 00:30:56 +000027#ifdef CONFIG_PS2MULT
28#include <ps2mult.h>
29#endif
wdenkf8cac652002-08-26 22:36:39 +000030
Heiko Schocher6ed3b9d2010-02-09 15:50:21 +010031#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
32#include <libfdt.h>
33#endif
34
Wolfgang Denk7c803be2008-09-16 18:02:19 +020035extern flash_info_t flash_info[]; /* FLASH chips info */
36
Wolfgang Denkd87080b2006-03-31 18:32:53 +020037DECLARE_GLOBAL_DATA_PTR;
wdenkf8cac652002-08-26 22:36:39 +000038
39static long int dram_size (long int, long int *, long int);
40
wdenkf8cac652002-08-26 22:36:39 +000041#define _NOT_USED_ 0xFFFFFFFF
42
Jens Gehrlein22d1a562007-09-26 17:55:54 +020043/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
wdenkf8cac652002-08-26 22:36:39 +000044const uint sdram_table[] =
45{
46 /*
47 * Single Read. (Offset 0 in UPMA RAM)
48 */
49 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
50 0x1FF5FC47, /* last */
51 /*
52 * SDRAM Initialization (offset 5 in UPMA RAM)
53 *
54 * This is no UPM entry point. The following definition uses
55 * the remaining space to establish an initialization
56 * sequence, which is executed by a RUN command.
57 *
58 */
59 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
60 /*
61 * Burst Read. (Offset 8 in UPMA RAM)
62 */
63 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
64 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
65 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
66 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
67 /*
68 * Single Write. (Offset 18 in UPMA RAM)
69 */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020070 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
71 0x1FF5FC47, /* last */
72 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000073 /*
74 * Burst Write. (Offset 20 in UPMA RAM)
75 */
76 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
Jens Gehrlein22d1a562007-09-26 17:55:54 +020077 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
wdenkf8cac652002-08-26 22:36:39 +000078 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 /*
81 * Refresh (Offset 30 in UPMA RAM)
82 */
83 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
84 0xFFFFFC84, 0xFFFFFC07, /* last */
85 _NOT_USED_, _NOT_USED_,
86 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
87 /*
88 * Exception. (Offset 3c in UPMA RAM)
89 */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020090 0xFFFFFC07, /* last */
wdenkf8cac652002-08-26 22:36:39 +000091 _NOT_USED_, _NOT_USED_, _NOT_USED_,
92};
93
94/* ------------------------------------------------------------------------- */
95
96
97/*
98 * Check Board Identity:
99 *
100 * Test TQ ID string (TQM8xx...)
101 * If present, check for "L" type (no second DRAM bank),
102 * otherwise "L" type is assumed as default.
103 *
wdenkd4ca31c2004-01-02 14:00:00 +0000104 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
wdenkf8cac652002-08-26 22:36:39 +0000105 */
106
107int checkboard (void)
108{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200109 char *s = getenv ("serial#");
wdenkf8cac652002-08-26 22:36:39 +0000110
111 puts ("Board: ");
112
113 if (!s || strncmp (s, "TQM8", 4)) {
114 puts ("### No HW ID - assuming TQM8xxL\n");
115 return (0);
116 }
117
118 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
119 gd->board_type = 'L';
120 }
121
wdenkd4ca31c2004-01-02 14:00:00 +0000122 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
123 gd->board_type = 'M';
124 }
125
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200126 if ((*(s + 6) == 'D')) { /* a TQM885D type */
127 gd->board_type = 'D';
128 }
129
wdenkf8cac652002-08-26 22:36:39 +0000130 for (; *s; ++s) {
131 if (*s == ' ')
132 break;
133 putc (*s);
134 }
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200135#ifdef CONFIG_VIRTLAB2
136 puts (" (Virtlab2)");
137#endif
wdenkf8cac652002-08-26 22:36:39 +0000138 putc ('\n');
139
140 return (0);
141}
142
143/* ------------------------------------------------------------------------- */
144
Becky Bruce9973e3c2008-06-09 16:03:40 -0500145phys_size_t initdram (int board_type)
wdenkf8cac652002-08-26 22:36:39 +0000146{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkf8cac652002-08-26 22:36:39 +0000148 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkc178d3d2004-01-24 20:25:54 +0000149 long int size8, size9, size10;
wdenkf8cac652002-08-26 22:36:39 +0000150 long int size_b0 = 0;
151 long int size_b1 = 0;
152
153 upmconfig (UPMA, (uint *) sdram_table,
154 sizeof (sdram_table) / sizeof (uint));
155
156 /*
157 * Preliminary prescaler for refresh (depends on number of
158 * banks): This value is selected for four cycles every 62.4 us
159 * with two SDRAM banks or four cycles every 31.2 us with one
160 * bank. It will be adjusted after memory sizing.
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
wdenkf8cac652002-08-26 22:36:39 +0000163
164 /*
165 * The following value is used as an address (i.e. opcode) for
166 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
167 * the port size is 32bit the SDRAM does NOT "see" the lower two
168 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
169 * MICRON SDRAMs:
170 * -> 0 00 010 0 010
171 * | | | | +- Burst Length = 4
172 * | | | +----- Burst Type = Sequential
173 * | | +------- CAS Latency = 2
174 * | +----------- Operating Mode = Standard
175 * +-------------- Write Burst Mode = Programmed Burst Length
176 */
177 memctl->memc_mar = 0x00000088;
178
179 /*
180 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
181 * preliminary addresses - these have to be modified after the
182 * SDRAM size has been determined.
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
185 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
wdenkf8cac652002-08-26 22:36:39 +0000186
187#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000188 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200189 (board_type != 'M') &&
Martin Krause11d9eec2007-09-26 17:55:56 +0200190 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
192 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
wdenkf8cac652002-08-26 22:36:39 +0000193 }
194#endif /* CONFIG_CAN_DRIVER */
195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
wdenkf8cac652002-08-26 22:36:39 +0000197
198 udelay (200);
199
200 /* perform SDRAM initializsation sequence */
201
202 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
203 udelay (1);
204 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
205 udelay (1);
206
207#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000208 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200209 (board_type != 'M') &&
Wolfgang Denkfc1840e2006-07-21 18:51:56 +0200210 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
wdenkf8cac652002-08-26 22:36:39 +0000211 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
212 udelay (1);
213 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
214 udelay (1);
215 }
216#endif /* CONFIG_CAN_DRIVER */
217
218 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
219
220 udelay (1000);
221
222 /*
223 * Check Bank 0 Memory Size for re-configuration
224 *
225 * try 8 column mode
226 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000228 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000229
230 udelay (1000);
231
232 /*
233 * try 9 column mode
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000236 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000237
wdenkc178d3d2004-01-24 20:25:54 +0000238 udelay(1000);
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#if defined(CONFIG_SYS_MAMR_10COL)
wdenkc178d3d2004-01-24 20:25:54 +0000241 /*
242 * try 10 column mode
243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244 size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkc178d3d2004-01-24 20:25:54 +0000245 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
246#else
247 size10 = 0;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#endif /* CONFIG_SYS_MAMR_10COL */
wdenkc178d3d2004-01-24 20:25:54 +0000249
250 if ((size8 < size10) && (size9 < size10)) {
251 size_b0 = size10;
252 } else if ((size8 < size9) && (size10 < size9)) {
wdenkf8cac652002-08-26 22:36:39 +0000253 size_b0 = size9;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254 memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
wdenkc178d3d2004-01-24 20:25:54 +0000255 udelay (500);
256 } else {
wdenkf8cac652002-08-26 22:36:39 +0000257 size_b0 = size8;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
wdenkf8cac652002-08-26 22:36:39 +0000259 udelay (500);
wdenkf8cac652002-08-26 22:36:39 +0000260 }
wdenkd4ca31c2004-01-02 14:00:00 +0000261 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000262
263#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000264 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200265 (board_type != 'M') &&
Martin Krause11d9eec2007-09-26 17:55:56 +0200266 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
wdenkf8cac652002-08-26 22:36:39 +0000267 /*
268 * Check Bank 1 Memory Size
269 * use current column settings
270 * [9 column SDRAM may also be used in 8 column mode,
271 * but then only half the real size will be used.]
272 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200273 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
wdenkd4ca31c2004-01-02 14:00:00 +0000274 SDRAM_MAX_SIZE);
275 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000276 } else {
277 size_b1 = 0;
278 }
wdenkd4ca31c2004-01-02 14:00:00 +0000279#endif /* CONFIG_CAN_DRIVER */
wdenkf8cac652002-08-26 22:36:39 +0000280
281 udelay (1000);
282
283 /*
284 * Adjust refresh rate depending on SDRAM type, both banks
285 * For types > 128 MBit leave it at the current (fast) rate
286 */
287 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
288 /* reduce to 15.6 us (62.4 us / quad) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
wdenkf8cac652002-08-26 22:36:39 +0000290 udelay (1000);
291 }
292
293 /*
294 * Final mapping: map bigger bank first
295 */
296 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
297
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
299 memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000300
301 if (size_b0 > 0) {
302 /*
303 * Position Bank 0 immediately above Bank 1
304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
306 memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
wdenkc178d3d2004-01-24 20:25:54 +0000307 + size_b1;
wdenkf8cac652002-08-26 22:36:39 +0000308 } else {
309 unsigned long reg;
310
311 /*
312 * No bank 0
313 *
314 * invalidate bank
315 */
316 memctl->memc_br2 = 0;
317
318 /* adjust refresh rate depending on SDRAM type, one bank */
319 reg = memctl->memc_mptpr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
wdenkf8cac652002-08-26 22:36:39 +0000321 memctl->memc_mptpr = reg;
322 }
323
324 } else { /* SDRAM Bank 0 is bigger - map first */
325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkf8cac652002-08-26 22:36:39 +0000327 memctl->memc_br2 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000329
330 if (size_b1 > 0) {
331 /*
332 * Position Bank 1 immediately above Bank 0
333 */
334 memctl->memc_or3 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
wdenkf8cac652002-08-26 22:36:39 +0000336 memctl->memc_br3 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
wdenkf8cac652002-08-26 22:36:39 +0000338 + size_b0;
339 } else {
340 unsigned long reg;
341
342#ifndef CONFIG_CAN_DRIVER
343 /*
344 * No bank 1
345 *
346 * invalidate bank
347 */
348 memctl->memc_br3 = 0;
349#endif /* CONFIG_CAN_DRIVER */
350
351 /* adjust refresh rate depending on SDRAM type, one bank */
352 reg = memctl->memc_mptpr;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
wdenkf8cac652002-08-26 22:36:39 +0000354 memctl->memc_mptpr = reg;
355 }
356 }
357
358 udelay (10000);
359
360#ifdef CONFIG_CAN_DRIVER
Jens Gehrlein9d292502007-09-26 17:55:54 +0200361 /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
362
wdenkf8cac652002-08-26 22:36:39 +0000363 /* Initialize OR3 / BR3 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364 memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
365 memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
wdenkf8cac652002-08-26 22:36:39 +0000366
367 /* Initialize MBMR */
wdenkfd3103b2003-11-25 16:55:19 +0000368 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
wdenkf8cac652002-08-26 22:36:39 +0000369
370 /* Initialize UPMB for CAN: single read */
Jens Gehrlein9d292502007-09-26 17:55:54 +0200371 memctl->memc_mdr = 0xFFFFCC04;
wdenkf8cac652002-08-26 22:36:39 +0000372 memctl->memc_mcr = 0x0100 | UPMB;
373
374 memctl->memc_mdr = 0x0FFFD004;
375 memctl->memc_mcr = 0x0101 | UPMB;
376
377 memctl->memc_mdr = 0x0FFFC000;
378 memctl->memc_mcr = 0x0102 | UPMB;
379
380 memctl->memc_mdr = 0x3FFFC004;
381 memctl->memc_mcr = 0x0103 | UPMB;
382
Jens Gehrlein9d292502007-09-26 17:55:54 +0200383 memctl->memc_mdr = 0xFFFFDC07;
wdenkf8cac652002-08-26 22:36:39 +0000384 memctl->memc_mcr = 0x0104 | UPMB;
385
386 /* Initialize UPMB for CAN: single write */
Jens Gehrlein9d292502007-09-26 17:55:54 +0200387 memctl->memc_mdr = 0xFFFCCC04;
wdenkf8cac652002-08-26 22:36:39 +0000388 memctl->memc_mcr = 0x0118 | UPMB;
389
Jens Gehrlein9d292502007-09-26 17:55:54 +0200390 memctl->memc_mdr = 0xCFFCDC04;
wdenkf8cac652002-08-26 22:36:39 +0000391 memctl->memc_mcr = 0x0119 | UPMB;
392
Jens Gehrlein9d292502007-09-26 17:55:54 +0200393 memctl->memc_mdr = 0x3FFCC000;
wdenkf8cac652002-08-26 22:36:39 +0000394 memctl->memc_mcr = 0x011A | UPMB;
395
Jens Gehrlein9d292502007-09-26 17:55:54 +0200396 memctl->memc_mdr = 0xFFFCC004;
wdenkf8cac652002-08-26 22:36:39 +0000397 memctl->memc_mcr = 0x011B | UPMB;
398
Jens Gehrlein9d292502007-09-26 17:55:54 +0200399 memctl->memc_mdr = 0xFFFDC405;
wdenkf8cac652002-08-26 22:36:39 +0000400 memctl->memc_mcr = 0x011C | UPMB;
401#endif /* CONFIG_CAN_DRIVER */
402
wdenkbdccc4f2003-08-05 17:43:17 +0000403#ifdef CONFIG_ISP1362_USB
404 /* Initialize OR5 / BR5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405 memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
406 memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
wdenkbdccc4f2003-08-05 17:43:17 +0000407#endif /* CONFIG_ISP1362_USB */
wdenkf8cac652002-08-26 22:36:39 +0000408 return (size_b0 + size_b1);
409}
410
411/* ------------------------------------------------------------------------- */
412
413/*
414 * Check memory range for valid RAM. A simple memory test determines
415 * the actually available RAM size between addresses `base' and
416 * `base + maxsize'. Some (not all) hardware errors are detected:
417 * - short between address lines
418 * - short between data lines
419 */
420
wdenkd4ca31c2004-01-02 14:00:00 +0000421static long int dram_size (long int mamr_value, long int *base, long int maxsize)
wdenkf8cac652002-08-26 22:36:39 +0000422{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200423 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenkf8cac652002-08-26 22:36:39 +0000424 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkf8cac652002-08-26 22:36:39 +0000425
426 memctl->memc_mamr = mamr_value;
427
wdenkc83bf6a2004-01-06 22:38:14 +0000428 return (get_ram_size(base, maxsize));
wdenkf8cac652002-08-26 22:36:39 +0000429}
430
431/* ------------------------------------------------------------------------- */
wdenk1c437712004-01-16 00:30:56 +0000432
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200433#ifdef CONFIG_MISC_INIT_R
Mike Frysinger9c150102009-02-11 20:09:52 -0500434extern void load_sernum_ethaddr(void);
wdenk1c437712004-01-16 00:30:56 +0000435int misc_init_r (void)
436{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200438 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk1c437712004-01-16 00:30:56 +0000439
Mike Frysinger9c150102009-02-11 20:09:52 -0500440 load_sernum_ethaddr();
441
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200442#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200443 int scy, trlx, flash_or_timing, clk_diff;
444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445 scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
446 if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200447 trlx = OR_TRLX;
448 scy *= 2;
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200449 } else {
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200450 trlx = 0;
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200451 }
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200452
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200453 /*
454 * We assume that each 10MHz of bus clock require 1-clk SCY
455 * adjustment.
456 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200457 clk_diff = (gd->bus_clk / 1000000) - 50;
458
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200459 /*
460 * We need proper rounding here. This is what the "+5" and "-5"
461 * are here for.
462 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200463 if (clk_diff >= 0)
464 scy += (clk_diff + 5) / 10;
465 else
466 scy += (clk_diff - 5) / 10;
467
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200468 /*
469 * For bus frequencies above 50MHz, we want to use relaxed timing
470 * (OR_TRLX).
471 */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200472 if (gd->bus_clk >= 50000000)
473 trlx = OR_TRLX;
474 else
475 trlx = 0;
476
477 if (trlx)
478 scy /= 2;
479
480 if (scy > 0xf)
481 scy = 0xf;
482 if (scy < 1)
483 scy = 1;
484
485 flash_or_timing = (scy << 4) | trlx |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200486 (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200487
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200488 memctl->memc_or0 =
489 flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200490#else
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200491 memctl->memc_or0 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200492 CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200493#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494 memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200495
496 debug ("## BR0: 0x%08x OR0: 0x%08x\n",
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200497 memctl->memc_br0, memctl->memc_or0);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200498
499 if (flash_info[1].size) {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200501 memctl->memc_or1 = flash_or_timing |
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200502 (-flash_info[1].size & 0xFFFF8000);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200503#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504 memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200505 (-flash_info[1].size & 0xFFFF8000);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200506#endif
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200507 memctl->memc_br1 =
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508 ((CONFIG_SYS_FLASH_BASE +
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200509 flash_info[0].
510 size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200511
512 debug ("## BR1: 0x%08x OR1: 0x%08x\n",
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200513 memctl->memc_br1, memctl->memc_or1);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200514 } else {
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200515 memctl->memc_br1 = 0; /* invalidate bank */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200516
517 debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200518 memctl->memc_br1, memctl->memc_or1);
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200519 }
520
521# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000522 /* Configure PA15 as output port */
523 immap->im_ioport.iop_padir |= 0x0001;
524 immap->im_ioport.iop_paodr |= 0x0001;
525 immap->im_ioport.iop_papar &= ~0x0001;
526 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
wdenkcfca5e62004-08-01 13:09:47 +0000527# endif
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200528
529#ifdef CONFIG_NSCU
530 /* wake up ethernet module */
Wolfgang Denk87b4ef52008-09-17 10:17:55 +0200531 immap->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
532 immap->im_ioport.iop_pcdir |= 0x0004; /* output */
533 immap->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
534 immap->im_ioport.iop_pcdat |= 0x0004; /* enable */
535#endif /* CONFIG_NSCU */
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200536
wdenk1c437712004-01-16 00:30:56 +0000537 return (0);
538}
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200539#endif /* CONFIG_MISC_INIT_R */
540
wdenk1c437712004-01-16 00:30:56 +0000541
wdenkcfca5e62004-08-01 13:09:47 +0000542# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000543void ide_led (uchar led, uchar status)
544{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk1c437712004-01-16 00:30:56 +0000546
547 /* We have one led for both pcmcia slots */
548 if (status) { /* led on */
549 immap->im_ioport.iop_padat |= 0x0001;
550 } else {
551 immap->im_ioport.iop_padat &= ~0x0001;
552 }
553}
wdenkcfca5e62004-08-01 13:09:47 +0000554# endif
wdenkcfca5e62004-08-01 13:09:47 +0000555
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200556#ifdef CONFIG_LCD_INFO
557#include <lcd.h>
Anatolij Gustschin1450c4a2008-11-03 15:30:34 +0100558#include <version.h>
Peter Tyser561858e2008-11-03 09:30:59 -0600559#include <timestamp.h>
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200560
561void lcd_show_board_info(void)
562{
Anatolij Gustschin1450c4a2008-11-03 15:30:34 +0100563 char temp[32];
564
Peter Tyser561858e2008-11-03 09:30:59 -0600565 lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200566 lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
567 lcd_printf (" Wolfgang DENK, wd@denx.de\n");
568#ifdef CONFIG_LCD_INFO_BELOW_LOGO
569 lcd_printf ("MPC823 CPU at %s MHz\n",
570 strmhz(temp, gd->cpu_clk));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200571 lcd_printf (" %ld MB RAM, %ld MB Flash\n",
572 gd->ram_size >> 20,
573 gd->bd->bi_flashsize >> 20 );
574#else
575 /* leave one blank line */
576 lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
577 strmhz(temp, gd->cpu_clk),
578 gd->ram_size >> 20,
579 gd->bd->bi_flashsize >> 20 );
580#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
581}
582#endif /* CONFIG_LCD_INFO */
583
Heiko Schocher6ed3b9d2010-02-09 15:50:21 +0100584/*
585 * Device Tree Support
586 */
587#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
588int fdt_set_node_and_value (void *blob,
589 char *nodename,
590 char *regname,
591 void *var,
592 int size)
593{
594 int ret = 0;
595 int nodeoffset = 0;
596
597 nodeoffset = fdt_path_offset (blob, nodename);
598 if (nodeoffset >= 0) {
599 ret = fdt_setprop (blob, nodeoffset, regname, var,
600 size);
601 if (ret < 0) {
602 printf("ft_blob_update(): "
603 "cannot set %s/%s property; err: %s\n",
604 nodename, regname, fdt_strerror (ret));
605 }
606 } else {
607 printf("ft_blob_update(): "
608 "cannot find %s node err:%s\n",
609 nodename, fdt_strerror (nodeoffset));
610 }
611 return ret;
612}
613
614int fdt_del_node_name (void *blob, char *nodename)
615{
616 int ret = 0;
617 int nodeoffset = 0;
618
619 nodeoffset = fdt_path_offset (blob, nodename);
620 if (nodeoffset >= 0) {
621 ret = fdt_del_node (blob, nodeoffset);
622 if (ret < 0) {
623 printf("%s: cannot delete %s; err: %s\n",
624 __func__, nodename, fdt_strerror (ret));
625 }
626 } else {
627 printf("%s: cannot find %s node err:%s\n",
628 __func__, nodename, fdt_strerror (nodeoffset));
629 }
630 return ret;
631}
632
633int fdt_del_prop_name (void *blob, char *nodename, char *propname)
634{
635 int ret = 0;
636 int nodeoffset = 0;
637
638 nodeoffset = fdt_path_offset (blob, nodename);
639 if (nodeoffset >= 0) {
640 ret = fdt_delprop (blob, nodeoffset, propname);
641 if (ret < 0) {
642 printf("%s: cannot delete %s %s; err: %s\n",
643 __func__, nodename, propname,
644 fdt_strerror (ret));
645 }
646 } else {
647 printf("%s: cannot find %s node err:%s\n",
648 __func__, nodename, fdt_strerror (nodeoffset));
649 }
650 return ret;
651}
652
653/*
654 * update "brg" property in the blob
655 */
656void ft_blob_update (void *blob, bd_t *bd)
657{
658 uchar enetaddr[6];
659 ulong brg_data = 0;
660
661 /* BRG */
662 brg_data = cpu_to_be32(bd->bi_busfreq);
663 fdt_set_node_and_value(blob,
664 "/soc/cpm", "brg-frequency",
665 &brg_data, sizeof(brg_data));
666
667 /* MAC addr */
668 if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
669 fdt_set_node_and_value(blob,
670 "ethernet0", "local-mac-address",
671 enetaddr, sizeof(u8) * 6);
672 }
673
674 if (hwconfig_arg_cmp("fec", "off")) {
675 /* no FEC on this plattform, delete DTS nodes */
676 fdt_del_node_name (blob, "ethernet1");
677 fdt_del_node_name (blob, "mdio1");
678 /* also the aliases entries */
679 fdt_del_prop_name (blob, "/aliases", "ethernet1");
680 fdt_del_prop_name (blob, "/aliases", "mdio1");
681 } else {
682 /* adjust local-mac-address for FEC ethernet */
683 if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
684 fdt_set_node_and_value(blob,
685 "ethernet1", "local-mac-address",
686 enetaddr, sizeof(u8) * 6);
687 }
688 }
689}
690
691void ft_board_setup(void *blob, bd_t *bd)
692{
693 ft_cpu_setup(blob, bd);
694 ft_blob_update(blob, bd);
695}
696#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
697
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100698/* ---------------------------------------------------------------------------- */
699/* TK885D specific initializaion */
700/* ---------------------------------------------------------------------------- */
701#ifdef CONFIG_TK885D
702#include <miiphy.h>
703int last_stage_init(void)
704{
705 const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY};
706 unsigned short reg;
707 int ret, i = 100;
708 char *s;
709
710 mii_init();
711 /* Without this delay 0xff is read from the UART buffer later in
712 * abortboot() and autoboot is aborted */
713 udelay(10000);
714 while (tstc() && i--)
715 (void)getc();
716
717 /* Check if auto-negotiation is prohibited */
718 s = getenv("phy_auto_nego");
719
720 if (!s || !strcmp(s, "on"))
721 /* Nothing to do - autonegotiation by default */
722 return 0;
723
724 for (i = 0; i < 2; i++) {
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500725 ret = miiphy_read("FEC", phy[i], MII_BMCR, &reg);
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100726 if (ret) {
727 printf("Cannot read BMCR on PHY %d\n", phy[i]);
728 return 0;
729 }
730 /* Auto-negotiation off, hard set full duplex, 100Mbps */
Heiko Schocher48690d82010-07-20 17:45:02 +0200731 ret = miiphy_write("FEC", phy[i],
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500732 MII_BMCR, (reg | BMCR_SPEED100 |
733 BMCR_FULLDPLX) & ~BMCR_ANENABLE);
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100734 if (ret) {
735 printf("Cannot write BMCR on PHY %d\n", phy[i]);
736 return 0;
737 }
738 }
739
740 return 0;
741}
Guennadi Liakhovetskiefc6f442008-01-10 17:59:07 +0100742#endif