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wdenkf8cac652002-08-26 22:36:39 +00001/*
Wolfgang Denk8cba0902006-05-12 16:15:46 +02002 * (C) Copyright 2000-2006
wdenkf8cac652002-08-26 22:36:39 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenkd4ca31c2004-01-02 14:00:00 +000024#if 0
25#define DEBUG
26#endif
27
wdenkf8cac652002-08-26 22:36:39 +000028#include <common.h>
29#include <mpc8xx.h>
wdenk1c437712004-01-16 00:30:56 +000030#ifdef CONFIG_PS2MULT
31#include <ps2mult.h>
32#endif
wdenkf8cac652002-08-26 22:36:39 +000033
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
wdenkf8cac652002-08-26 22:36:39 +000035
36static long int dram_size (long int, long int *, long int);
37
wdenkf8cac652002-08-26 22:36:39 +000038#define _NOT_USED_ 0xFFFFFFFF
39
Jens Gehrlein22d1a562007-09-26 17:55:54 +020040/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
wdenkf8cac652002-08-26 22:36:39 +000041const uint sdram_table[] =
42{
43 /*
44 * Single Read. (Offset 0 in UPMA RAM)
45 */
46 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
47 0x1FF5FC47, /* last */
48 /*
49 * SDRAM Initialization (offset 5 in UPMA RAM)
50 *
51 * This is no UPM entry point. The following definition uses
52 * the remaining space to establish an initialization
53 * sequence, which is executed by a RUN command.
54 *
55 */
56 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
57 /*
58 * Burst Read. (Offset 8 in UPMA RAM)
59 */
60 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
61 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
64 /*
65 * Single Write. (Offset 18 in UPMA RAM)
66 */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020067 0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
68 0x1FF5FC47, /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenkf8cac652002-08-26 22:36:39 +000070 /*
71 * Burst Write. (Offset 20 in UPMA RAM)
72 */
73 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
Jens Gehrlein22d1a562007-09-26 17:55:54 +020074 0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
wdenkf8cac652002-08-26 22:36:39 +000075 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
77 /*
78 * Refresh (Offset 30 in UPMA RAM)
79 */
80 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
81 0xFFFFFC84, 0xFFFFFC07, /* last */
82 _NOT_USED_, _NOT_USED_,
83 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
84 /*
85 * Exception. (Offset 3c in UPMA RAM)
86 */
Jens Gehrlein22d1a562007-09-26 17:55:54 +020087 0xFFFFFC07, /* last */
wdenkf8cac652002-08-26 22:36:39 +000088 _NOT_USED_, _NOT_USED_, _NOT_USED_,
89};
90
91/* ------------------------------------------------------------------------- */
92
93
94/*
95 * Check Board Identity:
96 *
97 * Test TQ ID string (TQM8xx...)
98 * If present, check for "L" type (no second DRAM bank),
99 * otherwise "L" type is assumed as default.
100 *
wdenkd4ca31c2004-01-02 14:00:00 +0000101 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
wdenkf8cac652002-08-26 22:36:39 +0000102 */
103
104int checkboard (void)
105{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200106 char *s = getenv ("serial#");
wdenkf8cac652002-08-26 22:36:39 +0000107
108 puts ("Board: ");
109
110 if (!s || strncmp (s, "TQM8", 4)) {
111 puts ("### No HW ID - assuming TQM8xxL\n");
112 return (0);
113 }
114
115 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
116 gd->board_type = 'L';
117 }
118
wdenkd4ca31c2004-01-02 14:00:00 +0000119 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
120 gd->board_type = 'M';
121 }
122
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200123 if ((*(s + 6) == 'D')) { /* a TQM885D type */
124 gd->board_type = 'D';
125 }
126
wdenkf8cac652002-08-26 22:36:39 +0000127 for (; *s; ++s) {
128 if (*s == ' ')
129 break;
130 putc (*s);
131 }
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200132#ifdef CONFIG_VIRTLAB2
133 puts (" (Virtlab2)");
134#endif
wdenkf8cac652002-08-26 22:36:39 +0000135 putc ('\n');
136
137 return (0);
138}
139
140/* ------------------------------------------------------------------------- */
141
142long int initdram (int board_type)
143{
144 volatile immap_t *immap = (immap_t *) CFG_IMMR;
145 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkc178d3d2004-01-24 20:25:54 +0000146 long int size8, size9, size10;
wdenkf8cac652002-08-26 22:36:39 +0000147 long int size_b0 = 0;
148 long int size_b1 = 0;
149
150 upmconfig (UPMA, (uint *) sdram_table,
151 sizeof (sdram_table) / sizeof (uint));
152
153 /*
154 * Preliminary prescaler for refresh (depends on number of
155 * banks): This value is selected for four cycles every 62.4 us
156 * with two SDRAM banks or four cycles every 31.2 us with one
157 * bank. It will be adjusted after memory sizing.
158 */
159 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
160
161 /*
162 * The following value is used as an address (i.e. opcode) for
163 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
164 * the port size is 32bit the SDRAM does NOT "see" the lower two
165 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
166 * MICRON SDRAMs:
167 * -> 0 00 010 0 010
168 * | | | | +- Burst Length = 4
169 * | | | +----- Burst Type = Sequential
170 * | | +------- CAS Latency = 2
171 * | +----------- Operating Mode = Standard
172 * +-------------- Write Burst Mode = Programmed Burst Length
173 */
174 memctl->memc_mar = 0x00000088;
175
176 /*
177 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
178 * preliminary addresses - these have to be modified after the
179 * SDRAM size has been determined.
180 */
181 memctl->memc_or2 = CFG_OR2_PRELIM;
182 memctl->memc_br2 = CFG_BR2_PRELIM;
183
184#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000185 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200186 (board_type != 'M') &&
187 (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
wdenkf8cac652002-08-26 22:36:39 +0000188 memctl->memc_or3 = CFG_OR3_PRELIM;
189 memctl->memc_br3 = CFG_BR3_PRELIM;
190 }
191#endif /* CONFIG_CAN_DRIVER */
192
193 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
194
195 udelay (200);
196
197 /* perform SDRAM initializsation sequence */
198
199 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
200 udelay (1);
201 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
202 udelay (1);
203
204#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000205 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200206 (board_type != 'M') &&
Wolfgang Denkfc1840e2006-07-21 18:51:56 +0200207 (board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
wdenkf8cac652002-08-26 22:36:39 +0000208 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
209 udelay (1);
210 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
211 udelay (1);
212 }
213#endif /* CONFIG_CAN_DRIVER */
214
215 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
216
217 udelay (1000);
218
219 /*
220 * Check Bank 0 Memory Size for re-configuration
221 *
222 * try 8 column mode
223 */
Wolfgang Denkfc1840e2006-07-21 18:51:56 +0200224 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000225 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000226
227 udelay (1000);
228
229 /*
230 * try 9 column mode
231 */
Wolfgang Denkfc1840e2006-07-21 18:51:56 +0200232 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000233 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000234
wdenkc178d3d2004-01-24 20:25:54 +0000235 udelay(1000);
236
237#if defined(CFG_MAMR_10COL)
238 /*
239 * try 10 column mode
240 */
Wolfgang Denkfc1840e2006-07-21 18:51:56 +0200241 size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
wdenkc178d3d2004-01-24 20:25:54 +0000242 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
243#else
244 size10 = 0;
245#endif /* CFG_MAMR_10COL */
246
247 if ((size8 < size10) && (size9 < size10)) {
248 size_b0 = size10;
249 } else if ((size8 < size9) && (size10 < size9)) {
wdenkf8cac652002-08-26 22:36:39 +0000250 size_b0 = size9;
wdenkc178d3d2004-01-24 20:25:54 +0000251 memctl->memc_mamr = CFG_MAMR_9COL;
252 udelay (500);
253 } else {
wdenkf8cac652002-08-26 22:36:39 +0000254 size_b0 = size8;
255 memctl->memc_mamr = CFG_MAMR_8COL;
256 udelay (500);
wdenkf8cac652002-08-26 22:36:39 +0000257 }
wdenkd4ca31c2004-01-02 14:00:00 +0000258 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000259
260#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000261 if ((board_type != 'L') &&
Markus Klotzbuecher090eb732006-07-12 15:26:01 +0200262 (board_type != 'M') &&
263 (board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
wdenkf8cac652002-08-26 22:36:39 +0000264 /*
265 * Check Bank 1 Memory Size
266 * use current column settings
267 * [9 column SDRAM may also be used in 8 column mode,
268 * but then only half the real size will be used.]
269 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200270 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
wdenkd4ca31c2004-01-02 14:00:00 +0000271 SDRAM_MAX_SIZE);
272 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000273 } else {
274 size_b1 = 0;
275 }
wdenkd4ca31c2004-01-02 14:00:00 +0000276#endif /* CONFIG_CAN_DRIVER */
wdenkf8cac652002-08-26 22:36:39 +0000277
278 udelay (1000);
279
280 /*
281 * Adjust refresh rate depending on SDRAM type, both banks
282 * For types > 128 MBit leave it at the current (fast) rate
283 */
284 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
285 /* reduce to 15.6 us (62.4 us / quad) */
286 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
287 udelay (1000);
288 }
289
290 /*
291 * Final mapping: map bigger bank first
292 */
293 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
294
295 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
wdenkc178d3d2004-01-24 20:25:54 +0000296 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000297
298 if (size_b0 > 0) {
299 /*
300 * Position Bank 0 immediately above Bank 1
301 */
wdenkc178d3d2004-01-24 20:25:54 +0000302 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
303 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
304 + size_b1;
wdenkf8cac652002-08-26 22:36:39 +0000305 } else {
306 unsigned long reg;
307
308 /*
309 * No bank 0
310 *
311 * invalidate bank
312 */
313 memctl->memc_br2 = 0;
314
315 /* adjust refresh rate depending on SDRAM type, one bank */
316 reg = memctl->memc_mptpr;
317 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
318 memctl->memc_mptpr = reg;
319 }
320
321 } else { /* SDRAM Bank 0 is bigger - map first */
322
323 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
324 memctl->memc_br2 =
325 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
326
327 if (size_b1 > 0) {
328 /*
329 * Position Bank 1 immediately above Bank 0
330 */
331 memctl->memc_or3 =
332 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
333 memctl->memc_br3 =
334 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
335 + size_b0;
336 } else {
337 unsigned long reg;
338
339#ifndef CONFIG_CAN_DRIVER
340 /*
341 * No bank 1
342 *
343 * invalidate bank
344 */
345 memctl->memc_br3 = 0;
346#endif /* CONFIG_CAN_DRIVER */
347
348 /* adjust refresh rate depending on SDRAM type, one bank */
349 reg = memctl->memc_mptpr;
350 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
351 memctl->memc_mptpr = reg;
352 }
353 }
354
355 udelay (10000);
356
357#ifdef CONFIG_CAN_DRIVER
Jens Gehrlein9d292502007-09-26 17:55:54 +0200358 /* UPM initialization for CAN @ CLKOUT <= 66 MHz */
359
wdenkf8cac652002-08-26 22:36:39 +0000360 /* Initialize OR3 / BR3 */
361 memctl->memc_or3 = CFG_OR3_CAN;
362 memctl->memc_br3 = CFG_BR3_CAN;
363
364 /* Initialize MBMR */
wdenkfd3103b2003-11-25 16:55:19 +0000365 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
wdenkf8cac652002-08-26 22:36:39 +0000366
367 /* Initialize UPMB for CAN: single read */
Jens Gehrlein9d292502007-09-26 17:55:54 +0200368 memctl->memc_mdr = 0xFFFFCC04;
wdenkf8cac652002-08-26 22:36:39 +0000369 memctl->memc_mcr = 0x0100 | UPMB;
370
371 memctl->memc_mdr = 0x0FFFD004;
372 memctl->memc_mcr = 0x0101 | UPMB;
373
374 memctl->memc_mdr = 0x0FFFC000;
375 memctl->memc_mcr = 0x0102 | UPMB;
376
377 memctl->memc_mdr = 0x3FFFC004;
378 memctl->memc_mcr = 0x0103 | UPMB;
379
Jens Gehrlein9d292502007-09-26 17:55:54 +0200380 memctl->memc_mdr = 0xFFFFDC07;
wdenkf8cac652002-08-26 22:36:39 +0000381 memctl->memc_mcr = 0x0104 | UPMB;
382
383 /* Initialize UPMB for CAN: single write */
Jens Gehrlein9d292502007-09-26 17:55:54 +0200384 memctl->memc_mdr = 0xFFFCCC04;
wdenkf8cac652002-08-26 22:36:39 +0000385 memctl->memc_mcr = 0x0118 | UPMB;
386
Jens Gehrlein9d292502007-09-26 17:55:54 +0200387 memctl->memc_mdr = 0xCFFCDC04;
wdenkf8cac652002-08-26 22:36:39 +0000388 memctl->memc_mcr = 0x0119 | UPMB;
389
Jens Gehrlein9d292502007-09-26 17:55:54 +0200390 memctl->memc_mdr = 0x3FFCC000;
wdenkf8cac652002-08-26 22:36:39 +0000391 memctl->memc_mcr = 0x011A | UPMB;
392
Jens Gehrlein9d292502007-09-26 17:55:54 +0200393 memctl->memc_mdr = 0xFFFCC004;
wdenkf8cac652002-08-26 22:36:39 +0000394 memctl->memc_mcr = 0x011B | UPMB;
395
Jens Gehrlein9d292502007-09-26 17:55:54 +0200396 memctl->memc_mdr = 0xFFFDC405;
wdenkf8cac652002-08-26 22:36:39 +0000397 memctl->memc_mcr = 0x011C | UPMB;
398#endif /* CONFIG_CAN_DRIVER */
399
wdenkbdccc4f2003-08-05 17:43:17 +0000400#ifdef CONFIG_ISP1362_USB
401 /* Initialize OR5 / BR5 */
402 memctl->memc_or5 = CFG_OR5_ISP1362;
403 memctl->memc_br5 = CFG_BR5_ISP1362;
404#endif /* CONFIG_ISP1362_USB */
wdenk42d1f032003-10-15 23:53:47 +0000405
406
wdenkf8cac652002-08-26 22:36:39 +0000407 return (size_b0 + size_b1);
408}
409
410/* ------------------------------------------------------------------------- */
411
412/*
413 * Check memory range for valid RAM. A simple memory test determines
414 * the actually available RAM size between addresses `base' and
415 * `base + maxsize'. Some (not all) hardware errors are detected:
416 * - short between address lines
417 * - short between data lines
418 */
419
wdenkd4ca31c2004-01-02 14:00:00 +0000420static long int dram_size (long int mamr_value, long int *base, long int maxsize)
wdenkf8cac652002-08-26 22:36:39 +0000421{
422 volatile immap_t *immap = (immap_t *) CFG_IMMR;
423 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkf8cac652002-08-26 22:36:39 +0000424
425 memctl->memc_mamr = mamr_value;
426
wdenkc83bf6a2004-01-06 22:38:14 +0000427 return (get_ram_size(base, maxsize));
wdenkf8cac652002-08-26 22:36:39 +0000428}
429
430/* ------------------------------------------------------------------------- */
wdenk1c437712004-01-16 00:30:56 +0000431
432#ifdef CONFIG_PS2MULT
433
wdenkc40b2952004-03-13 23:29:43 +0000434#ifdef CONFIG_HMI10
wdenk1c437712004-01-16 00:30:56 +0000435#define BASE_BAUD ( 1843200 / 16 )
436struct serial_state rs_table[] = {
437 { BASE_BAUD, 4, (void*)0xec140000 },
438 { BASE_BAUD, 2, (void*)0xec150000 },
439 { BASE_BAUD, 6, (void*)0xec160000 },
440 { BASE_BAUD, 10, (void*)0xec170000 },
441};
wdenkc837dcb2004-01-20 23:12:12 +0000442
443#ifdef CONFIG_BOARD_EARLY_INIT_R
444int board_early_init_r (void)
445{
446 ps2mult_early_init();
447 return (0);
448}
449#endif
wdenkc40b2952004-03-13 23:29:43 +0000450#endif /* CONFIG_HMI10 */
wdenk1c437712004-01-16 00:30:56 +0000451
452#endif /* CONFIG_PS2MULT */
453
wdenkcfca5e62004-08-01 13:09:47 +0000454/* ---------------------------------------------------------------------------- */
455/* HMI10 specific stuff */
456/* ---------------------------------------------------------------------------- */
wdenkc40b2952004-03-13 23:29:43 +0000457#ifdef CONFIG_HMI10
wdenk1c437712004-01-16 00:30:56 +0000458
459int misc_init_r (void)
460{
wdenkcfca5e62004-08-01 13:09:47 +0000461# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000462 volatile immap_t *immap = (immap_t *) CFG_IMMR;
463
464 /* Configure PA15 as output port */
465 immap->im_ioport.iop_padir |= 0x0001;
466 immap->im_ioport.iop_paodr |= 0x0001;
467 immap->im_ioport.iop_papar &= ~0x0001;
468 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
wdenkcfca5e62004-08-01 13:09:47 +0000469# endif
wdenk1c437712004-01-16 00:30:56 +0000470 return (0);
471}
472
wdenkcfca5e62004-08-01 13:09:47 +0000473# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000474void ide_led (uchar led, uchar status)
475{
476 volatile immap_t *immap = (immap_t *) CFG_IMMR;
477
478 /* We have one led for both pcmcia slots */
479 if (status) { /* led on */
480 immap->im_ioport.iop_padat |= 0x0001;
481 } else {
482 immap->im_ioport.iop_padat &= ~0x0001;
483 }
484}
wdenkcfca5e62004-08-01 13:09:47 +0000485# endif
486#endif /* CONFIG_HMI10 */
wdenk1c437712004-01-16 00:30:56 +0000487
wdenkcfca5e62004-08-01 13:09:47 +0000488/* ---------------------------------------------------------------------------- */
489/* NSCU specific stuff */
490/* ---------------------------------------------------------------------------- */
491#ifdef CONFIG_NSCU
492
493int misc_init_r (void)
494{
495 volatile immap_t *immr = (immap_t *) CFG_IMMR;
496
497 /* wake up ethernet module */
498 immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
499 immr->im_ioport.iop_pcdir |= 0x0004; /* output */
500 immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
501 immr->im_ioport.iop_pcdat |= 0x0004; /* enable */
502
503 return (0);
504}
505#endif /* CONFIG_NSCU */
506
wdenk1c437712004-01-16 00:30:56 +0000507/* ------------------------------------------------------------------------- */