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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "x86"
6
Masahiro Yamadadd840582014-07-30 14:08:14 +09007choice
Bin Meng65c4ac02015-04-27 23:22:24 +08008 prompt "Mainboard vendor"
Bin Meng99a309f2015-05-07 21:34:09 +08009 default VENDOR_EMULATION
Masahiro Yamadadd840582014-07-30 14:08:14 +090010
Bin Meng65c4ac02015-04-27 23:22:24 +080011config VENDOR_COREBOOT
12 bool "coreboot"
Simon Glass8ef07572014-11-12 22:42:07 -070013
Ben Stoltz3dcdd172015-08-04 12:33:46 -060014config VENDOR_EFI
15 bool "efi"
16
Bin Menga65b25d2015-05-07 21:34:08 +080017config VENDOR_EMULATION
18 bool "emulation"
19
Bin Meng65c4ac02015-04-27 23:22:24 +080020config VENDOR_GOOGLE
21 bool "Google"
Masahiro Yamadadd840582014-07-30 14:08:14 +090022
Bin Meng65c4ac02015-04-27 23:22:24 +080023config VENDOR_INTEL
24 bool "Intel"
Bin Mengef46bea2015-02-02 22:35:29 +080025
Masahiro Yamadadd840582014-07-30 14:08:14 +090026endchoice
27
Bin Meng65c4ac02015-04-27 23:22:24 +080028# board-specific options below
29source "board/coreboot/Kconfig"
Ben Stoltz3e9aa322015-08-04 12:33:47 -060030source "board/efi/Kconfig"
Bin Menga65b25d2015-05-07 21:34:08 +080031source "board/emulation/Kconfig"
Bin Meng65c4ac02015-04-27 23:22:24 +080032source "board/google/Kconfig"
33source "board/intel/Kconfig"
34
Bin Meng029194a2015-04-27 23:22:25 +080035# platform-specific options below
36source "arch/x86/cpu/baytrail/Kconfig"
37source "arch/x86/cpu/coreboot/Kconfig"
38source "arch/x86/cpu/ivybridge/Kconfig"
Bin Menga65b25d2015-05-07 21:34:08 +080039source "arch/x86/cpu/qemu/Kconfig"
Bin Meng029194a2015-04-27 23:22:25 +080040source "arch/x86/cpu/quark/Kconfig"
41source "arch/x86/cpu/queensbay/Kconfig"
42
43# architecture-specific options below
44
Simon Glassb724bd72015-02-11 16:32:59 -070045config SYS_MALLOC_F_LEN
46 default 0x800
47
Simon Glass70a09c62014-11-12 22:42:10 -070048config RAMBASE
49 hex
50 default 0x100000
51
Simon Glass70a09c62014-11-12 22:42:10 -070052config XIP_ROM_SIZE
53 hex
Bin Meng7698d362015-01-06 22:14:16 +080054 depends on X86_RESET_VECTOR
Simon Glassbbd43d62015-01-01 16:17:54 -070055 default ROM_SIZE
Simon Glass70a09c62014-11-12 22:42:10 -070056
57config CPU_ADDR_BITS
58 int
59 default 36
60
Simon Glass65dd74a2014-11-12 22:42:28 -070061config HPET_ADDRESS
62 hex
63 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
64
65config SMM_TSEG
66 bool
67 default n
68
69config SMM_TSEG_SIZE
70 hex
71
Bin Meng8cb20cc2015-01-06 22:14:15 +080072config X86_RESET_VECTOR
73 bool
74 default n
75
Bin Meng343fb992015-06-07 11:33:12 +080076config RESET_SEG_START
77 hex
78 depends on X86_RESET_VECTOR
79 default 0xffff0000
80
81config RESET_SEG_SIZE
82 hex
83 depends on X86_RESET_VECTOR
84 default 0x10000
85
86config RESET_VEC_LOC
87 hex
88 depends on X86_RESET_VECTOR
89 default 0xfffffff0
90
Bin Meng8cb20cc2015-01-06 22:14:15 +080091config SYS_X86_START16
92 hex
93 depends on X86_RESET_VECTOR
94 default 0xfffff800
95
Bin Meng64542f42014-12-12 21:05:19 +080096config BOARD_ROMSIZE_KB_512
97 bool
98config BOARD_ROMSIZE_KB_1024
99 bool
100config BOARD_ROMSIZE_KB_2048
101 bool
102config BOARD_ROMSIZE_KB_4096
103 bool
104config BOARD_ROMSIZE_KB_8192
105 bool
106config BOARD_ROMSIZE_KB_16384
107 bool
108
109choice
110 prompt "ROM chip size"
Bin Meng7698d362015-01-06 22:14:16 +0800111 depends on X86_RESET_VECTOR
Bin Meng64542f42014-12-12 21:05:19 +0800112 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
113 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
114 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
115 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
116 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
117 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
118 help
119 Select the size of the ROM chip you intend to flash U-Boot on.
120
121 The build system will take care of creating a u-boot.rom file
122 of the matching size.
123
124config UBOOT_ROMSIZE_KB_512
125 bool "512 KB"
126 help
127 Choose this option if you have a 512 KB ROM chip.
128
129config UBOOT_ROMSIZE_KB_1024
130 bool "1024 KB (1 MB)"
131 help
132 Choose this option if you have a 1024 KB (1 MB) ROM chip.
133
134config UBOOT_ROMSIZE_KB_2048
135 bool "2048 KB (2 MB)"
136 help
137 Choose this option if you have a 2048 KB (2 MB) ROM chip.
138
139config UBOOT_ROMSIZE_KB_4096
140 bool "4096 KB (4 MB)"
141 help
142 Choose this option if you have a 4096 KB (4 MB) ROM chip.
143
144config UBOOT_ROMSIZE_KB_8192
145 bool "8192 KB (8 MB)"
146 help
147 Choose this option if you have a 8192 KB (8 MB) ROM chip.
148
149config UBOOT_ROMSIZE_KB_16384
150 bool "16384 KB (16 MB)"
151 help
152 Choose this option if you have a 16384 KB (16 MB) ROM chip.
153
154endchoice
155
156# Map the config names to an integer (KB).
157config UBOOT_ROMSIZE_KB
158 int
159 default 512 if UBOOT_ROMSIZE_KB_512
160 default 1024 if UBOOT_ROMSIZE_KB_1024
161 default 2048 if UBOOT_ROMSIZE_KB_2048
162 default 4096 if UBOOT_ROMSIZE_KB_4096
163 default 8192 if UBOOT_ROMSIZE_KB_8192
164 default 16384 if UBOOT_ROMSIZE_KB_16384
165
166# Map the config names to a hex value (bytes).
Simon Glassfce7b272014-11-12 22:42:08 -0700167config ROM_SIZE
168 hex
Bin Meng64542f42014-12-12 21:05:19 +0800169 default 0x80000 if UBOOT_ROMSIZE_KB_512
170 default 0x100000 if UBOOT_ROMSIZE_KB_1024
171 default 0x200000 if UBOOT_ROMSIZE_KB_2048
172 default 0x400000 if UBOOT_ROMSIZE_KB_4096
173 default 0x800000 if UBOOT_ROMSIZE_KB_8192
174 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
175 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
Simon Glassfce7b272014-11-12 22:42:08 -0700176
177config HAVE_INTEL_ME
178 bool "Platform requires Intel Management Engine"
179 help
180 Newer higher-end devices have an Intel Management Engine (ME)
181 which is a very large binary blob (typically 1.5MB) which is
182 required for the platform to work. This enforces a particular
183 SPI flash format. You will need to supply the me.bin file in
184 your board directory.
185
Simon Glass65dd74a2014-11-12 22:42:28 -0700186config X86_RAMTEST
187 bool "Perform a simple RAM test after SDRAM initialisation"
188 help
189 If there is something wrong with SDRAM then the platform will
190 often crash within U-Boot or the kernel. This option enables a
191 very simple RAM test that quickly checks whether the SDRAM seems
192 to work correctly. It is not exhaustive but can save time by
193 detecting obvious failures.
194
Simon Glass8ce24cd2015-01-27 22:13:41 -0700195config HAVE_FSP
196 bool "Add an Firmware Support Package binary"
Simon Glasse49ccea2015-08-04 12:34:00 -0600197 depends on !EFI
Simon Glass8ce24cd2015-01-27 22:13:41 -0700198 help
199 Select this option to add an Firmware Support Package binary to
200 the resulting U-Boot image. It is a binary blob which U-Boot uses
201 to set up SDRAM and other chipset specific initialization.
202
203 Note: Without this binary U-Boot will not be able to set up its
204 SDRAM so will not boot.
205
206config FSP_FILE
207 string "Firmware Support Package binary filename"
208 depends on HAVE_FSP
209 default "fsp.bin"
210 help
211 The filename of the file to use as Firmware Support Package binary
212 in the board directory.
213
214config FSP_ADDR
215 hex "Firmware Support Package binary location"
216 depends on HAVE_FSP
217 default 0xfffc0000
218 help
219 FSP is not Position Independent Code (PIC) and the whole FSP has to
220 be rebased if it is placed at a location which is different from the
221 perferred base address specified during the FSP build. Use Intel's
222 Binary Configuration Tool (BCT) to do the rebase.
223
224 The default base address of 0xfffc0000 indicates that the binary must
225 be located at offset 0xc0000 from the beginning of a 1MB flash device.
226
227config FSP_TEMP_RAM_ADDR
228 hex
Bin Mengd04e30b2015-06-01 21:07:23 +0800229 depends on HAVE_FSP
Simon Glass8ce24cd2015-01-27 22:13:41 -0700230 default 0x2000000
231 help
232 Stack top address which is used in FspInit after DRAM is ready and
233 CAR is disabled.
234
Simon Glass45b5a372015-04-29 22:25:59 -0600235config SMP
236 bool "Enable Symmetric Multiprocessing"
237 default n
238 help
239 Enable use of more than one CPU in U-Boot and the Operating System
240 when loaded. Each CPU will be started up and information can be
241 obtained using the 'cpu' command. If this option is disabled, then
242 only one CPU will be enabled regardless of the number of CPUs
243 available.
244
Bin Meng4c713222015-06-12 14:52:23 +0800245config MAX_CPUS
246 int "Maximum number of CPUs permitted"
247 depends on SMP
248 default 4
249 help
250 When using multi-CPU chips it is possible for U-Boot to start up
251 more than one CPU. The stack memory used by all of these CPUs is
252 pre-allocated so at present U-Boot wants to know the maximum
253 number of CPUs that may be present. Set this to at least as high
254 as the number of CPUs in your system (it uses about 4KB of RAM for
255 each CPU).
256
Simon Glass45b5a372015-04-29 22:25:59 -0600257config AP_STACK_SIZE
258 hex
Bin Meng063374d2015-06-12 14:52:22 +0800259 depends on SMP
Simon Glass45b5a372015-04-29 22:25:59 -0600260 default 0x1000
261 help
262 Each additional CPU started by U-Boot requires its own stack. This
263 option sets the stack size used by each CPU and directly affects
264 the memory used by this initialisation process. Typically 4KB is
265 enough space.
266
Bin Mengf56aeaa2015-02-05 23:42:20 +0800267config TSC_CALIBRATION_BYPASS
268 bool "Bypass Time-Stamp Counter (TSC) calibration"
269 default n
270 help
271 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
272 running frequency via Model-Specific Register (MSR) and Programmable
273 Interval Timer (PIT). If the calibration does not work on your board,
274 select this option and provide a hardcoded TSC running frequency with
275 CONFIG_TSC_FREQ_IN_MHZ below.
276
277 Normally this option should be turned on in a simulation environment
278 like qemu.
279
280config TSC_FREQ_IN_MHZ
281 int "Time-Stamp Counter (TSC) running frequency in MHz"
282 depends on TSC_CALIBRATION_BYPASS
283 default 1000
284 help
285 The running frequency in MHz of Time-Stamp Counter (TSC).
286
Bin Meng786a08e2015-07-06 16:31:33 +0800287config HAVE_VGA_BIOS
288 bool "Add a VGA BIOS image"
289 help
290 Select this option if you have a VGA BIOS image that you would
291 like to add to your ROM.
292
293config VGA_BIOS_FILE
294 string "VGA BIOS image filename"
295 depends on HAVE_VGA_BIOS
296 default "vga.bin"
297 help
298 The filename of the VGA BIOS image in the board directory.
299
300config VGA_BIOS_ADDR
301 hex "VGA BIOS image location"
302 depends on HAVE_VGA_BIOS
303 default 0xfff90000
304 help
305 The location of VGA BIOS image in the SPI flash. For example, base
306 address of 0xfff90000 indicates that the image will be put at offset
307 0x90000 from the beginning of a 1MB flash device.
308
Bin Mengb5b6b012015-04-24 18:10:05 +0800309menu "System tables"
Bin Meng8744bef2015-08-13 00:29:13 -0700310 depends on !EFI && !SYS_COREBOOT
Bin Mengb5b6b012015-04-24 18:10:05 +0800311
312config GENERATE_PIRQ_TABLE
313 bool "Generate a PIRQ table"
314 default n
315 help
316 Generate a PIRQ routing table for this board. The PIRQ routing table
317 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
318 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
319 It specifies the interrupt router information as well how all the PCI
320 devices' interrupt pins are wired to PIRQs.
321
Simon Glass6388e352015-04-28 20:25:10 -0600322config GENERATE_SFI_TABLE
323 bool "Generate a SFI (Simple Firmware Interface) table"
324 help
325 The Simple Firmware Interface (SFI) provides a lightweight method
326 for platform firmware to pass information to the operating system
327 via static tables in memory. Kernel SFI support is required to
328 boot on SFI-only platforms. If you have ACPI tables then these are
329 used instead.
330
331 U-Boot writes this table in write_sfi_table() just before booting
332 the OS.
333
334 For more information, see http://simplefirmware.org
335
Bin Meng07545d82015-06-23 12:18:52 +0800336config GENERATE_MP_TABLE
337 bool "Generate an MP (Multi-Processor) table"
338 default n
339 help
340 Generate an MP (Multi-Processor) table for this board. The MP table
341 provides a way for the operating system to support for symmetric
342 multiprocessing as well as symmetric I/O interrupt handling with
343 the local APIC and I/O APIC.
344
Bin Mengb5b6b012015-04-24 18:10:05 +0800345endmenu
346
347config MAX_PIRQ_LINKS
348 int
349 default 8
350 help
351 This variable specifies the number of PIRQ interrupt links which are
352 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
353 Some newer chipsets offer more than four links, commonly up to PIRQH.
354
355config IRQ_SLOT_COUNT
356 int
357 default 128
358 help
359 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
360 which in turns forms a table of exact 4KiB. The default value 128
361 should be enough for most boards. If this does not fit your board,
362 change it according to your needs.
363
Simon Glass2d934e52015-01-27 22:13:33 -0700364config PCIE_ECAM_BASE
365 hex
Bin Mengba877ef2015-02-02 21:25:09 +0800366 default 0xe0000000
Simon Glass2d934e52015-01-27 22:13:33 -0700367 help
368 This is the memory-mapped address of PCI configuration space, which
369 is only available through the Enhanced Configuration Access
370 Mechanism (ECAM) with PCI Express. It can be set up almost
371 anywhere. Before it is set up, it is possible to access PCI
372 configuration space through I/O access, but memory access is more
373 convenient. Using this, PCI can be scanned and configured. This
374 should be set to a region that does not conflict with memory
375 assigned to PCI devices - i.e. the memory and prefetch regions, as
376 passed to pci_set_region().
377
Bin Meng1ed66482015-07-22 01:21:15 -0700378config PCIE_ECAM_SIZE
379 hex
380 default 0x10000000
381 help
382 This is the size of memory-mapped address of PCI configuration space,
383 which is only available through the Enhanced Configuration Access
384 Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
385 so a default 0x10000000 size covers all of the 256 buses which is the
386 maximum number of PCI buses as defined by the PCI specification.
387
Simon Glasse49ccea2015-08-04 12:34:00 -0600388source "arch/x86/lib/efi/Kconfig"
389
Masahiro Yamadadd840582014-07-30 14:08:14 +0900390endmenu