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Masahiro Yamadadd840582014-07-30 14:08:14 +09001menu "x86 architecture"
2 depends on X86
3
4config SYS_ARCH
Masahiro Yamadadd840582014-07-30 14:08:14 +09005 default "x86"
6
Masahiro Yamadadd840582014-07-30 14:08:14 +09007choice
Bin Meng65c4ac02015-04-27 23:22:24 +08008 prompt "Mainboard vendor"
Bin Meng99a309f2015-05-07 21:34:09 +08009 default VENDOR_EMULATION
Masahiro Yamadadd840582014-07-30 14:08:14 +090010
Bin Meng65c4ac02015-04-27 23:22:24 +080011config VENDOR_COREBOOT
12 bool "coreboot"
Simon Glass8ef07572014-11-12 22:42:07 -070013
Bin Menga65b25d2015-05-07 21:34:08 +080014config VENDOR_EMULATION
15 bool "emulation"
16
Bin Meng65c4ac02015-04-27 23:22:24 +080017config VENDOR_GOOGLE
18 bool "Google"
Masahiro Yamadadd840582014-07-30 14:08:14 +090019
Bin Meng65c4ac02015-04-27 23:22:24 +080020config VENDOR_INTEL
21 bool "Intel"
Bin Mengef46bea2015-02-02 22:35:29 +080022
Masahiro Yamadadd840582014-07-30 14:08:14 +090023endchoice
24
Bin Meng65c4ac02015-04-27 23:22:24 +080025# board-specific options below
26source "board/coreboot/Kconfig"
Bin Menga65b25d2015-05-07 21:34:08 +080027source "board/emulation/Kconfig"
Bin Meng65c4ac02015-04-27 23:22:24 +080028source "board/google/Kconfig"
29source "board/intel/Kconfig"
30
Bin Meng029194a2015-04-27 23:22:25 +080031# platform-specific options below
32source "arch/x86/cpu/baytrail/Kconfig"
33source "arch/x86/cpu/coreboot/Kconfig"
34source "arch/x86/cpu/ivybridge/Kconfig"
Bin Menga65b25d2015-05-07 21:34:08 +080035source "arch/x86/cpu/qemu/Kconfig"
Bin Meng029194a2015-04-27 23:22:25 +080036source "arch/x86/cpu/quark/Kconfig"
37source "arch/x86/cpu/queensbay/Kconfig"
38
39# architecture-specific options below
40
Simon Glassb724bd72015-02-11 16:32:59 -070041config SYS_MALLOC_F_LEN
42 default 0x800
43
Simon Glass70a09c62014-11-12 22:42:10 -070044config RAMBASE
45 hex
46 default 0x100000
47
Simon Glass70a09c62014-11-12 22:42:10 -070048config XIP_ROM_SIZE
49 hex
Bin Meng7698d362015-01-06 22:14:16 +080050 depends on X86_RESET_VECTOR
Simon Glassbbd43d62015-01-01 16:17:54 -070051 default ROM_SIZE
Simon Glass70a09c62014-11-12 22:42:10 -070052
53config CPU_ADDR_BITS
54 int
55 default 36
56
Simon Glass65dd74a2014-11-12 22:42:28 -070057config HPET_ADDRESS
58 hex
59 default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
60
61config SMM_TSEG
62 bool
63 default n
64
65config SMM_TSEG_SIZE
66 hex
67
Bin Meng8cb20cc2015-01-06 22:14:15 +080068config X86_RESET_VECTOR
69 bool
70 default n
71
Bin Meng343fb992015-06-07 11:33:12 +080072config RESET_SEG_START
73 hex
74 depends on X86_RESET_VECTOR
75 default 0xffff0000
76
77config RESET_SEG_SIZE
78 hex
79 depends on X86_RESET_VECTOR
80 default 0x10000
81
82config RESET_VEC_LOC
83 hex
84 depends on X86_RESET_VECTOR
85 default 0xfffffff0
86
Bin Meng8cb20cc2015-01-06 22:14:15 +080087config SYS_X86_START16
88 hex
89 depends on X86_RESET_VECTOR
90 default 0xfffff800
91
Bin Meng64542f42014-12-12 21:05:19 +080092config BOARD_ROMSIZE_KB_512
93 bool
94config BOARD_ROMSIZE_KB_1024
95 bool
96config BOARD_ROMSIZE_KB_2048
97 bool
98config BOARD_ROMSIZE_KB_4096
99 bool
100config BOARD_ROMSIZE_KB_8192
101 bool
102config BOARD_ROMSIZE_KB_16384
103 bool
104
105choice
106 prompt "ROM chip size"
Bin Meng7698d362015-01-06 22:14:16 +0800107 depends on X86_RESET_VECTOR
Bin Meng64542f42014-12-12 21:05:19 +0800108 default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
109 default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
110 default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
111 default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
112 default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
113 default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
114 help
115 Select the size of the ROM chip you intend to flash U-Boot on.
116
117 The build system will take care of creating a u-boot.rom file
118 of the matching size.
119
120config UBOOT_ROMSIZE_KB_512
121 bool "512 KB"
122 help
123 Choose this option if you have a 512 KB ROM chip.
124
125config UBOOT_ROMSIZE_KB_1024
126 bool "1024 KB (1 MB)"
127 help
128 Choose this option if you have a 1024 KB (1 MB) ROM chip.
129
130config UBOOT_ROMSIZE_KB_2048
131 bool "2048 KB (2 MB)"
132 help
133 Choose this option if you have a 2048 KB (2 MB) ROM chip.
134
135config UBOOT_ROMSIZE_KB_4096
136 bool "4096 KB (4 MB)"
137 help
138 Choose this option if you have a 4096 KB (4 MB) ROM chip.
139
140config UBOOT_ROMSIZE_KB_8192
141 bool "8192 KB (8 MB)"
142 help
143 Choose this option if you have a 8192 KB (8 MB) ROM chip.
144
145config UBOOT_ROMSIZE_KB_16384
146 bool "16384 KB (16 MB)"
147 help
148 Choose this option if you have a 16384 KB (16 MB) ROM chip.
149
150endchoice
151
152# Map the config names to an integer (KB).
153config UBOOT_ROMSIZE_KB
154 int
155 default 512 if UBOOT_ROMSIZE_KB_512
156 default 1024 if UBOOT_ROMSIZE_KB_1024
157 default 2048 if UBOOT_ROMSIZE_KB_2048
158 default 4096 if UBOOT_ROMSIZE_KB_4096
159 default 8192 if UBOOT_ROMSIZE_KB_8192
160 default 16384 if UBOOT_ROMSIZE_KB_16384
161
162# Map the config names to a hex value (bytes).
Simon Glassfce7b272014-11-12 22:42:08 -0700163config ROM_SIZE
164 hex
Bin Meng64542f42014-12-12 21:05:19 +0800165 default 0x80000 if UBOOT_ROMSIZE_KB_512
166 default 0x100000 if UBOOT_ROMSIZE_KB_1024
167 default 0x200000 if UBOOT_ROMSIZE_KB_2048
168 default 0x400000 if UBOOT_ROMSIZE_KB_4096
169 default 0x800000 if UBOOT_ROMSIZE_KB_8192
170 default 0xc00000 if UBOOT_ROMSIZE_KB_12288
171 default 0x1000000 if UBOOT_ROMSIZE_KB_16384
Simon Glassfce7b272014-11-12 22:42:08 -0700172
173config HAVE_INTEL_ME
174 bool "Platform requires Intel Management Engine"
175 help
176 Newer higher-end devices have an Intel Management Engine (ME)
177 which is a very large binary blob (typically 1.5MB) which is
178 required for the platform to work. This enforces a particular
179 SPI flash format. You will need to supply the me.bin file in
180 your board directory.
181
Simon Glass65dd74a2014-11-12 22:42:28 -0700182config X86_RAMTEST
183 bool "Perform a simple RAM test after SDRAM initialisation"
184 help
185 If there is something wrong with SDRAM then the platform will
186 often crash within U-Boot or the kernel. This option enables a
187 very simple RAM test that quickly checks whether the SDRAM seems
188 to work correctly. It is not exhaustive but can save time by
189 detecting obvious failures.
190
Simon Glass22465fc2014-11-14 20:56:30 -0700191config MARK_GRAPHICS_MEM_WRCOMB
Bin Mengd99b9012015-04-27 23:22:26 +0800192 bool "Mark graphics memory as write-combining"
Simon Glass22465fc2014-11-14 20:56:30 -0700193 default n
194 help
Bin Mengd99b9012015-04-27 23:22:26 +0800195 The graphics performance may increase if the graphics
196 memory is set as write-combining cache type. This option
197 enables marking the graphics memory as write-combining.
Simon Glass22465fc2014-11-14 20:56:30 -0700198
Simon Glass8ce24cd2015-01-27 22:13:41 -0700199config HAVE_FSP
200 bool "Add an Firmware Support Package binary"
201 help
202 Select this option to add an Firmware Support Package binary to
203 the resulting U-Boot image. It is a binary blob which U-Boot uses
204 to set up SDRAM and other chipset specific initialization.
205
206 Note: Without this binary U-Boot will not be able to set up its
207 SDRAM so will not boot.
208
209config FSP_FILE
210 string "Firmware Support Package binary filename"
211 depends on HAVE_FSP
212 default "fsp.bin"
213 help
214 The filename of the file to use as Firmware Support Package binary
215 in the board directory.
216
217config FSP_ADDR
218 hex "Firmware Support Package binary location"
219 depends on HAVE_FSP
220 default 0xfffc0000
221 help
222 FSP is not Position Independent Code (PIC) and the whole FSP has to
223 be rebased if it is placed at a location which is different from the
224 perferred base address specified during the FSP build. Use Intel's
225 Binary Configuration Tool (BCT) to do the rebase.
226
227 The default base address of 0xfffc0000 indicates that the binary must
228 be located at offset 0xc0000 from the beginning of a 1MB flash device.
229
230config FSP_TEMP_RAM_ADDR
231 hex
Bin Mengd04e30b2015-06-01 21:07:23 +0800232 depends on HAVE_FSP
Simon Glass8ce24cd2015-01-27 22:13:41 -0700233 default 0x2000000
234 help
235 Stack top address which is used in FspInit after DRAM is ready and
236 CAR is disabled.
237
Simon Glass45b5a372015-04-29 22:25:59 -0600238config SMP
239 bool "Enable Symmetric Multiprocessing"
240 default n
241 help
242 Enable use of more than one CPU in U-Boot and the Operating System
243 when loaded. Each CPU will be started up and information can be
244 obtained using the 'cpu' command. If this option is disabled, then
245 only one CPU will be enabled regardless of the number of CPUs
246 available.
247
Bin Meng4c713222015-06-12 14:52:23 +0800248config MAX_CPUS
249 int "Maximum number of CPUs permitted"
250 depends on SMP
251 default 4
252 help
253 When using multi-CPU chips it is possible for U-Boot to start up
254 more than one CPU. The stack memory used by all of these CPUs is
255 pre-allocated so at present U-Boot wants to know the maximum
256 number of CPUs that may be present. Set this to at least as high
257 as the number of CPUs in your system (it uses about 4KB of RAM for
258 each CPU).
259
Simon Glass45b5a372015-04-29 22:25:59 -0600260config AP_STACK_SIZE
261 hex
Bin Meng063374d2015-06-12 14:52:22 +0800262 depends on SMP
Simon Glass45b5a372015-04-29 22:25:59 -0600263 default 0x1000
264 help
265 Each additional CPU started by U-Boot requires its own stack. This
266 option sets the stack size used by each CPU and directly affects
267 the memory used by this initialisation process. Typically 4KB is
268 enough space.
269
Bin Mengf56aeaa2015-02-05 23:42:20 +0800270config TSC_CALIBRATION_BYPASS
271 bool "Bypass Time-Stamp Counter (TSC) calibration"
272 default n
273 help
274 By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
275 running frequency via Model-Specific Register (MSR) and Programmable
276 Interval Timer (PIT). If the calibration does not work on your board,
277 select this option and provide a hardcoded TSC running frequency with
278 CONFIG_TSC_FREQ_IN_MHZ below.
279
280 Normally this option should be turned on in a simulation environment
281 like qemu.
282
283config TSC_FREQ_IN_MHZ
284 int "Time-Stamp Counter (TSC) running frequency in MHz"
285 depends on TSC_CALIBRATION_BYPASS
286 default 1000
287 help
288 The running frequency in MHz of Time-Stamp Counter (TSC).
289
Bin Mengb5b6b012015-04-24 18:10:05 +0800290menu "System tables"
291
292config GENERATE_PIRQ_TABLE
293 bool "Generate a PIRQ table"
294 default n
295 help
296 Generate a PIRQ routing table for this board. The PIRQ routing table
297 is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
298 at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
299 It specifies the interrupt router information as well how all the PCI
300 devices' interrupt pins are wired to PIRQs.
301
Simon Glass6388e352015-04-28 20:25:10 -0600302config GENERATE_SFI_TABLE
303 bool "Generate a SFI (Simple Firmware Interface) table"
304 help
305 The Simple Firmware Interface (SFI) provides a lightweight method
306 for platform firmware to pass information to the operating system
307 via static tables in memory. Kernel SFI support is required to
308 boot on SFI-only platforms. If you have ACPI tables then these are
309 used instead.
310
311 U-Boot writes this table in write_sfi_table() just before booting
312 the OS.
313
314 For more information, see http://simplefirmware.org
315
Bin Mengb5b6b012015-04-24 18:10:05 +0800316endmenu
317
318config MAX_PIRQ_LINKS
319 int
320 default 8
321 help
322 This variable specifies the number of PIRQ interrupt links which are
323 routable. On most older chipsets, this is 4, PIRQA through PIRQD.
324 Some newer chipsets offer more than four links, commonly up to PIRQH.
325
326config IRQ_SLOT_COUNT
327 int
328 default 128
329 help
330 U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
331 which in turns forms a table of exact 4KiB. The default value 128
332 should be enough for most boards. If this does not fit your board,
333 change it according to your needs.
334
Simon Glass2d934e52015-01-27 22:13:33 -0700335config PCIE_ECAM_BASE
336 hex
Bin Mengba877ef2015-02-02 21:25:09 +0800337 default 0xe0000000
Simon Glass2d934e52015-01-27 22:13:33 -0700338 help
339 This is the memory-mapped address of PCI configuration space, which
340 is only available through the Enhanced Configuration Access
341 Mechanism (ECAM) with PCI Express. It can be set up almost
342 anywhere. Before it is set up, it is possible to access PCI
343 configuration space through I/O access, but memory access is more
344 convenient. Using this, PCI can be scanned and configured. This
345 should be set to a region that does not conflict with memory
346 assigned to PCI devices - i.e. the memory and prefetch regions, as
347 passed to pci_set_region().
348
Masahiro Yamadadd840582014-07-30 14:08:14 +0900349endmenu