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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek185f7d92012-09-13 20:23:34 +00002/*
3 * (C) Copyright 2011 Michal Simek
4 *
5 * Michal SIMEK <monstr@monstr.eu>
6 *
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
Michal Simek185f7d92012-09-13 20:23:34 +00009 */
10
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +053011#include <clk.h>
Michal Simek185f7d92012-09-13 20:23:34 +000012#include <common.h>
Michal Simek6889ca72015-11-30 14:14:56 +010013#include <dm.h>
Michal Simek185f7d92012-09-13 20:23:34 +000014#include <net.h>
Michal Simek2fd24892014-04-25 14:17:38 +020015#include <netdev.h>
Michal Simek185f7d92012-09-13 20:23:34 +000016#include <config.h>
Michal Simekb8de29f2015-09-24 20:13:45 +020017#include <console.h>
Michal Simek185f7d92012-09-13 20:23:34 +000018#include <malloc.h>
19#include <asm/io.h>
20#include <phy.h>
21#include <miiphy.h>
Mateusz Kulikowskie7138b32016-01-23 11:54:33 +010022#include <wait_bit.h>
Michal Simek185f7d92012-09-13 20:23:34 +000023#include <watchdog.h>
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +053024#include <asm/system.h>
David Andrey01fbf312013-04-05 17:24:24 +020025#include <asm/arch/hardware.h>
Michal Simek80243522012-10-15 14:01:23 +020026#include <asm/arch/sys_proto.h>
Masahiro Yamada5d97dff2016-09-21 11:28:57 +090027#include <linux/errno.h>
Michal Simek185f7d92012-09-13 20:23:34 +000028
Michal Simek6889ca72015-11-30 14:14:56 +010029DECLARE_GLOBAL_DATA_PTR;
30
Michal Simek185f7d92012-09-13 20:23:34 +000031/* Bit/mask specification */
32#define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
33#define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
34#define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
35#define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
36#define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37
38#define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
39#define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
40#define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41
42#define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
43#define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
44#define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45
46/* Wrap bit, last descriptor */
47#define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
48#define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
Michal Simek23a598f2015-08-17 09:58:54 +020049#define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
Michal Simek185f7d92012-09-13 20:23:34 +000050
Michal Simek185f7d92012-09-13 20:23:34 +000051#define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
52#define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
53#define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
54#define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
55
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053056#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
57#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
58#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
59#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
Siva Durga Prasad Paladugu4eaf8f52016-05-16 15:31:38 +053060#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053061#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
Michal Simekf17ea712015-09-08 17:20:01 +020062#ifdef CONFIG_ARM64
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053063#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
Michal Simekf17ea712015-09-08 17:20:01 +020064#else
Siva Durga Prasad Paladugu27183d72016-05-16 15:31:37 +053065#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
Michal Simekf17ea712015-09-08 17:20:01 +020066#endif
Michal Simek185f7d92012-09-13 20:23:34 +000067
Siva Durga Prasad Paladugu8a584c82014-07-08 15:31:03 +053068#ifdef CONFIG_ARM64
69# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
70#else
71# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
72#endif
73
74#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
75 ZYNQ_GEM_NWCFG_FDEN | \
Michal Simek185f7d92012-09-13 20:23:34 +000076 ZYNQ_GEM_NWCFG_FSREM | \
77 ZYNQ_GEM_NWCFG_MDCCLKDIV)
78
79#define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
80
81#define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
82/* Use full configured addressable space (8 Kb) */
83#define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
84/* Use full configured addressable space (4 Kb) */
85#define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
86/* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
87#define ZYNQ_GEM_DMACR_RXBUF 0x00180000
88
89#define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
90 ZYNQ_GEM_DMACR_RXSIZE | \
91 ZYNQ_GEM_DMACR_TXSIZE | \
92 ZYNQ_GEM_DMACR_RXBUF)
93
Michal Simeke4d23182015-08-17 09:57:46 +020094#define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
95
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +053096#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
97
Michal Simekf97d7e82013-04-22 14:41:09 +020098/* Use MII register 1 (MII status register) to detect PHY */
99#define PHY_DETECT_REG 1
100
101/* Mask used to verify certain PHY features (or register contents)
102 * in the register above:
103 * 0x1000: 10Mbps full duplex support
104 * 0x0800: 10Mbps half duplex support
105 * 0x0008: Auto-negotiation support
106 */
107#define PHY_DETECT_MASK 0x1808
108
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530109/* TX BD status masks */
110#define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
111#define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
112#define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
113
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800114/* Clock frequencies for different speeds */
115#define ZYNQ_GEM_FREQUENCY_10 2500000UL
116#define ZYNQ_GEM_FREQUENCY_100 25000000UL
117#define ZYNQ_GEM_FREQUENCY_1000 125000000UL
118
Michal Simek185f7d92012-09-13 20:23:34 +0000119/* Device registers */
120struct zynq_gem_regs {
Michal Simek97a51a02015-10-05 11:49:43 +0200121 u32 nwctrl; /* 0x0 - Network Control reg */
122 u32 nwcfg; /* 0x4 - Network Config reg */
123 u32 nwsr; /* 0x8 - Network Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000124 u32 reserved1;
Michal Simek97a51a02015-10-05 11:49:43 +0200125 u32 dmacr; /* 0x10 - DMA Control reg */
126 u32 txsr; /* 0x14 - TX Status reg */
127 u32 rxqbase; /* 0x18 - RX Q Base address reg */
128 u32 txqbase; /* 0x1c - TX Q Base address reg */
129 u32 rxsr; /* 0x20 - RX Status reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000130 u32 reserved2[2];
Michal Simek97a51a02015-10-05 11:49:43 +0200131 u32 idr; /* 0x2c - Interrupt Disable reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000132 u32 reserved3;
Michal Simek97a51a02015-10-05 11:49:43 +0200133 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000134 u32 reserved4[18];
Michal Simek97a51a02015-10-05 11:49:43 +0200135 u32 hashl; /* 0x80 - Hash Low address reg */
136 u32 hashh; /* 0x84 - Hash High address reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000137#define LADDR_LOW 0
138#define LADDR_HIGH 1
Michal Simek97a51a02015-10-05 11:49:43 +0200139 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
140 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
Michal Simek185f7d92012-09-13 20:23:34 +0000141 u32 reserved6[18];
Michal Simek0ebf4042015-10-05 12:49:48 +0200142#define STAT_SIZE 44
143 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530144 u32 reserved9[20];
145 u32 pcscntrl;
146 u32 reserved7[143];
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700147 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
148 u32 reserved8[15];
149 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
Michal Simek185f7d92012-09-13 20:23:34 +0000150};
151
152/* BD descriptors */
153struct emac_bd {
154 u32 addr; /* Next descriptor pointer */
155 u32 status;
156};
157
Siva Durga Prasad Paladugueda9d302015-04-15 12:15:01 +0530158#define RX_BUF 32
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530159/* Page table entries are set to 1MB, or multiples of 1MB
160 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
161 */
162#define BD_SPACE 0x100000
163/* BD separation space */
Michal Simekff475872015-08-17 09:45:53 +0200164#define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
Michal Simek185f7d92012-09-13 20:23:34 +0000165
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700166/* Setup the first free TX descriptor */
167#define TX_FREE_DESC 2
168
Michal Simek185f7d92012-09-13 20:23:34 +0000169/* Initialized, rxbd_current, rx_first_buf must be 0 after init */
170struct zynq_gem_priv {
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530171 struct emac_bd *tx_bd;
172 struct emac_bd *rx_bd;
173 char *rxbuffers;
Michal Simek185f7d92012-09-13 20:23:34 +0000174 u32 rxbd_current;
175 u32 rx_first_buf;
176 int phyaddr;
Michal Simek05868752013-01-24 13:04:12 +0100177 int init;
Michal Simekf2fc2762015-11-30 10:24:15 +0100178 struct zynq_gem_regs *iobase;
Michal Simek16ce6de2015-10-07 16:42:56 +0200179 phy_interface_t interface;
Michal Simek185f7d92012-09-13 20:23:34 +0000180 struct phy_device *phydev;
Dan Murphy20671a92016-05-02 15:45:57 -0500181 int phy_of_handle;
Michal Simek185f7d92012-09-13 20:23:34 +0000182 struct mii_dev *bus;
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530183 struct clk clk;
Siva Durga Prasad Paladugu69065e82018-04-12 12:22:17 +0200184 u32 max_speed;
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530185 bool int_pcs;
Michal Simek185f7d92012-09-13 20:23:34 +0000186};
187
Michal Simekf2fc2762015-11-30 10:24:15 +0100188static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
189 u32 op, u16 *data)
Michal Simek185f7d92012-09-13 20:23:34 +0000190{
191 u32 mgtcr;
Michal Simekf2fc2762015-11-30 10:24:15 +0100192 struct zynq_gem_regs *regs = priv->iobase;
Michal Simekb908fca2016-12-12 09:47:26 +0100193 int err;
Michal Simek185f7d92012-09-13 20:23:34 +0000194
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100195 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
196 true, 20000, false);
Michal Simekb908fca2016-12-12 09:47:26 +0100197 if (err)
198 return err;
Michal Simek185f7d92012-09-13 20:23:34 +0000199
200 /* Construct mgtcr mask for the operation */
201 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
202 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
203 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
204
205 /* Write mgtcr and wait for completion */
206 writel(mgtcr, &regs->phymntnc);
207
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100208 err = wait_for_bit_le32(&regs->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
209 true, 20000, false);
Michal Simekb908fca2016-12-12 09:47:26 +0100210 if (err)
211 return err;
Michal Simek185f7d92012-09-13 20:23:34 +0000212
213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
214 *data = readl(&regs->phymntnc);
215
216 return 0;
217}
218
Michal Simekf2fc2762015-11-30 10:24:15 +0100219static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
220 u32 regnum, u16 *val)
Michal Simek185f7d92012-09-13 20:23:34 +0000221{
Michal Simek198e9a42015-10-07 16:34:51 +0200222 u32 ret;
223
Michal Simekf2fc2762015-11-30 10:24:15 +0100224 ret = phy_setup_op(priv, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
Michal Simek198e9a42015-10-07 16:34:51 +0200226
227 if (!ret)
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
230
231 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000232}
233
Michal Simekf2fc2762015-11-30 10:24:15 +0100234static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
235 u32 regnum, u16 data)
Michal Simek185f7d92012-09-13 20:23:34 +0000236{
Michal Simek198e9a42015-10-07 16:34:51 +0200237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
238 regnum, data);
239
Michal Simekf2fc2762015-11-30 10:24:15 +0100240 return phy_setup_op(priv, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
Michal Simek185f7d92012-09-13 20:23:34 +0000242}
243
Michal Simek6889ca72015-11-30 14:14:56 +0100244static int phy_detection(struct udevice *dev)
Michal Simekf97d7e82013-04-22 14:41:09 +0200245{
246 int i;
247 u16 phyreg;
248 struct zynq_gem_priv *priv = dev->priv;
249
250 if (priv->phyaddr != -1) {
Michal Simekf2fc2762015-11-30 10:24:15 +0100251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
Michal Simekf97d7e82013-04-22 14:41:09 +0200252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
256 priv->phyaddr);
Michal Simekb9047252015-11-30 13:38:32 +0100257 return 0;
Michal Simekf97d7e82013-04-22 14:41:09 +0200258 } else {
259 debug("PHY address is not setup correctly %d\n",
260 priv->phyaddr);
261 priv->phyaddr = -1;
262 }
263 }
264
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
Michal Simekf2fc2762015-11-30 10:24:15 +0100269 phyread(priv, i, PHY_DETECT_REG, &phyreg);
Michal Simekf97d7e82013-04-22 14:41:09 +0200270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
273 priv->phyaddr = i;
274 debug("Found valid phy address, %d\n", i);
Michal Simekb9047252015-11-30 13:38:32 +0100275 return 0;
Michal Simekf97d7e82013-04-22 14:41:09 +0200276 }
277 }
278 }
279 printf("PHY is not detected\n");
Michal Simekb9047252015-11-30 13:38:32 +0100280 return -1;
Michal Simekf97d7e82013-04-22 14:41:09 +0200281}
282
Michal Simek6889ca72015-11-30 14:14:56 +0100283static int zynq_gem_setup_mac(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000284{
285 u32 i, macaddrlow, macaddrhigh;
Michal Simek6889ca72015-11-30 14:14:56 +0100286 struct eth_pdata *pdata = dev_get_platdata(dev);
287 struct zynq_gem_priv *priv = dev_get_priv(dev);
288 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000289
290 /* Set the MAC bits [31:0] in BOT */
Michal Simek6889ca72015-11-30 14:14:56 +0100291 macaddrlow = pdata->enetaddr[0];
292 macaddrlow |= pdata->enetaddr[1] << 8;
293 macaddrlow |= pdata->enetaddr[2] << 16;
294 macaddrlow |= pdata->enetaddr[3] << 24;
Michal Simek185f7d92012-09-13 20:23:34 +0000295
296 /* Set MAC bits [47:32] in TOP */
Michal Simek6889ca72015-11-30 14:14:56 +0100297 macaddrhigh = pdata->enetaddr[4];
298 macaddrhigh |= pdata->enetaddr[5] << 8;
Michal Simek185f7d92012-09-13 20:23:34 +0000299
300 for (i = 0; i < 4; i++) {
301 writel(0, &regs->laddr[i][LADDR_LOW]);
302 writel(0, &regs->laddr[i][LADDR_HIGH]);
303 /* Do not use MATCHx register */
304 writel(0, &regs->match[i]);
305 }
306
307 writel(macaddrlow, &regs->laddr[0][LADDR_LOW]);
308 writel(macaddrhigh, &regs->laddr[0][LADDR_HIGH]);
309
310 return 0;
311}
312
Michal Simek6889ca72015-11-30 14:14:56 +0100313static int zynq_phy_init(struct udevice *dev)
Michal Simek68cc3bd2015-11-30 13:54:43 +0100314{
315 int ret;
Michal Simek6889ca72015-11-30 14:14:56 +0100316 struct zynq_gem_priv *priv = dev_get_priv(dev);
317 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100318 const u32 supported = SUPPORTED_10baseT_Half |
319 SUPPORTED_10baseT_Full |
320 SUPPORTED_100baseT_Half |
321 SUPPORTED_100baseT_Full |
322 SUPPORTED_1000baseT_Half |
323 SUPPORTED_1000baseT_Full;
324
Michal Simekc8e29272015-11-30 13:58:36 +0100325 /* Enable only MDIO bus */
326 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, &regs->nwctrl);
327
Siva Durga Prasad Paladugud77081c2018-02-20 11:56:19 +0530328 if ((priv->interface != PHY_INTERFACE_MODE_SGMII) &&
329 (priv->interface != PHY_INTERFACE_MODE_GMII)) {
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530330 ret = phy_detection(dev);
331 if (ret) {
332 printf("GEM PHY init failed\n");
333 return ret;
334 }
Michal Simek68cc3bd2015-11-30 13:54:43 +0100335 }
336
337 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
338 priv->interface);
Michal Simek90c6f2e2015-11-30 14:03:37 +0100339 if (!priv->phydev)
340 return -ENODEV;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100341
Nathan Rossi2c2ab8d2017-03-06 00:36:23 +1000342 priv->phydev->supported &= supported | ADVERTISED_Pause |
Michal Simek68cc3bd2015-11-30 13:54:43 +0100343 ADVERTISED_Asym_Pause;
Siva Durga Prasad Paladugu69065e82018-04-12 12:22:17 +0200344 if (priv->max_speed) {
345 ret = phy_set_supported(priv->phydev, priv->max_speed);
346 if (ret)
347 return ret;
348 }
349
Michal Simek68cc3bd2015-11-30 13:54:43 +0100350 priv->phydev->advertising = priv->phydev->supported;
Michal Simek68cc3bd2015-11-30 13:54:43 +0100351
Dan Murphy20671a92016-05-02 15:45:57 -0500352 if (priv->phy_of_handle > 0)
Simon Glasse160f7d2017-01-17 16:52:55 -0700353 dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle);
Dan Murphy20671a92016-05-02 15:45:57 -0500354
Michal Simek7a673f02016-05-18 14:37:23 +0200355 return phy_config(priv->phydev);
Michal Simek68cc3bd2015-11-30 13:54:43 +0100356}
357
Michal Simek6889ca72015-11-30 14:14:56 +0100358static int zynq_gem_init(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000359{
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530360 u32 i, nwconfig;
Michal Simek55259e72016-05-18 12:37:22 +0200361 int ret;
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800362 unsigned long clk_rate = 0;
Michal Simek6889ca72015-11-30 14:14:56 +0100363 struct zynq_gem_priv *priv = dev_get_priv(dev);
364 struct zynq_gem_regs *regs = priv->iobase;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700365 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
366 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
Michal Simek185f7d92012-09-13 20:23:34 +0000367
Michal Simek05868752013-01-24 13:04:12 +0100368 if (!priv->init) {
369 /* Disable all interrupts */
370 writel(0xFFFFFFFF, &regs->idr);
Michal Simek185f7d92012-09-13 20:23:34 +0000371
Michal Simek05868752013-01-24 13:04:12 +0100372 /* Disable the receiver & transmitter */
373 writel(0, &regs->nwctrl);
374 writel(0, &regs->txsr);
375 writel(0, &regs->rxsr);
376 writel(0, &regs->phymntnc);
Michal Simek185f7d92012-09-13 20:23:34 +0000377
Michal Simek05868752013-01-24 13:04:12 +0100378 /* Clear the Hash registers for the mac address
379 * pointed by AddressPtr
380 */
381 writel(0x0, &regs->hashl);
382 /* Write bits [63:32] in TOP */
383 writel(0x0, &regs->hashh);
Michal Simek185f7d92012-09-13 20:23:34 +0000384
Michal Simek05868752013-01-24 13:04:12 +0100385 /* Clear all counters */
Michal Simek0ebf4042015-10-05 12:49:48 +0200386 for (i = 0; i < STAT_SIZE; i++)
Michal Simek05868752013-01-24 13:04:12 +0100387 readl(&regs->stat[i]);
Michal Simek185f7d92012-09-13 20:23:34 +0000388
Michal Simek05868752013-01-24 13:04:12 +0100389 /* Setup RxBD space */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530390 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000391
Michal Simek05868752013-01-24 13:04:12 +0100392 for (i = 0; i < RX_BUF; i++) {
393 priv->rx_bd[i].status = 0xF0000000;
394 priv->rx_bd[i].addr =
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530395 ((ulong)(priv->rxbuffers) +
Michal Simek185f7d92012-09-13 20:23:34 +0000396 (i * PKTSIZE_ALIGN));
Michal Simek05868752013-01-24 13:04:12 +0100397 }
398 /* WRAP bit to last BD */
399 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
400 /* Write RxBDs to IP */
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530401 writel((ulong)priv->rx_bd, &regs->rxqbase);
Michal Simek185f7d92012-09-13 20:23:34 +0000402
Michal Simek05868752013-01-24 13:04:12 +0100403 /* Setup for DMA Configuration register */
404 writel(ZYNQ_GEM_DMACR_INIT, &regs->dmacr);
Michal Simek185f7d92012-09-13 20:23:34 +0000405
Michal Simek05868752013-01-24 13:04:12 +0100406 /* Setup for Network Control register, MDIO, Rx and Tx enable */
Michal Simek80243522012-10-15 14:01:23 +0200407 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
Michal Simek185f7d92012-09-13 20:23:34 +0000408
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700409 /* Disable the second priority queue */
410 dummy_tx_bd->addr = 0;
411 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
412 ZYNQ_GEM_TXBUF_LAST_MASK|
413 ZYNQ_GEM_TXBUF_USED_MASK;
414
415 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
416 ZYNQ_GEM_RXBUF_NEW_MASK;
417 dummy_rx_bd->status = 0;
Edgar E. Iglesias603ff002015-09-25 23:50:07 -0700418
419 writel((ulong)dummy_tx_bd, &regs->transmit_q1_ptr);
420 writel((ulong)dummy_rx_bd, &regs->receive_q1_ptr);
421
Michal Simek05868752013-01-24 13:04:12 +0100422 priv->init++;
423 }
424
Michal Simek55259e72016-05-18 12:37:22 +0200425 ret = phy_startup(priv->phydev);
426 if (ret)
427 return ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000428
Michal Simek64a7ead2015-11-30 13:44:49 +0100429 if (!priv->phydev->link) {
430 printf("%s: No link.\n", priv->phydev->dev->name);
Michal Simek4ed4aa22013-11-12 14:25:29 +0100431 return -1;
432 }
433
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530434 nwconfig = ZYNQ_GEM_NWCFG_INIT;
435
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530436 /*
437 * Set SGMII enable PCS selection only if internal PCS/PMA
438 * core is used and interface is SGMII.
439 */
440 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
441 priv->int_pcs) {
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530442 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
443 ZYNQ_GEM_NWCFG_PCS_SEL;
Siva Durga Prasad Paladugu845ee5f2016-03-25 12:53:44 +0530444#ifdef CONFIG_ARM64
445 writel(readl(&regs->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
446 &regs->pcscntrl);
447#endif
448 }
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530449
Michal Simek64a7ead2015-11-30 13:44:49 +0100450 switch (priv->phydev->speed) {
Michal Simek80243522012-10-15 14:01:23 +0200451 case SPEED_1000:
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530452 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
Michal Simek80243522012-10-15 14:01:23 +0200453 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800454 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
Michal Simek80243522012-10-15 14:01:23 +0200455 break;
456 case SPEED_100:
Siva Durga Prasad Paladugua06c3412016-02-05 13:22:11 +0530457 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
Michal Simek242b1542015-09-08 16:55:42 +0200458 &regs->nwcfg);
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800459 clk_rate = ZYNQ_GEM_FREQUENCY_100;
Michal Simek80243522012-10-15 14:01:23 +0200460 break;
461 case SPEED_10:
Soren Brinkmann97598fc2013-11-21 13:39:01 -0800462 clk_rate = ZYNQ_GEM_FREQUENCY_10;
Michal Simek80243522012-10-15 14:01:23 +0200463 break;
464 }
David Andrey01fbf312013-04-05 17:24:24 +0200465
Stefan Herbrechtsmeiereff55c52017-01-17 16:27:25 +0100466 ret = clk_set_rate(&priv->clk, clk_rate);
467 if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
468 dev_err(dev, "failed to set tx clock rate\n");
469 return ret;
470 }
471
472 ret = clk_enable(&priv->clk);
473 if (ret && ret != -ENOSYS) {
474 dev_err(dev, "failed to enable tx clock\n");
475 return ret;
476 }
Michal Simek80243522012-10-15 14:01:23 +0200477
478 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
479 ZYNQ_GEM_NWCTRL_TXEN_MASK);
480
Michal Simek185f7d92012-09-13 20:23:34 +0000481 return 0;
482}
483
Michal Simek6889ca72015-11-30 14:14:56 +0100484static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
Michal Simek185f7d92012-09-13 20:23:34 +0000485{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530486 u32 addr, size;
Michal Simek6889ca72015-11-30 14:14:56 +0100487 struct zynq_gem_priv *priv = dev_get_priv(dev);
488 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek23a598f2015-08-17 09:58:54 +0200489 struct emac_bd *current_bd = &priv->tx_bd[1];
Michal Simek185f7d92012-09-13 20:23:34 +0000490
Michal Simek185f7d92012-09-13 20:23:34 +0000491 /* Setup Tx BD */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530492 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
Michal Simek185f7d92012-09-13 20:23:34 +0000493
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530494 priv->tx_bd->addr = (ulong)ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530495 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
Michal Simek23a598f2015-08-17 09:58:54 +0200496 ZYNQ_GEM_TXBUF_LAST_MASK;
497 /* Dummy descriptor to mark it as the last in descriptor chain */
498 current_bd->addr = 0x0;
499 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
500 ZYNQ_GEM_TXBUF_LAST_MASK|
501 ZYNQ_GEM_TXBUF_USED_MASK;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530502
Michal Simek45c07742015-08-17 09:50:09 +0200503 /* setup BD */
504 writel((ulong)priv->tx_bd, &regs->txqbase);
505
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530506 addr = (ulong) ptr;
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530507 addr &= ~(ARCH_DMA_MINALIGN - 1);
508 size = roundup(len, ARCH_DMA_MINALIGN);
509 flush_dcache_range(addr, addr + size);
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530510
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530511 addr = (ulong)priv->rxbuffers;
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530512 addr &= ~(ARCH_DMA_MINALIGN - 1);
513 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
514 flush_dcache_range(addr, addr + size);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530515 barrier();
Michal Simek185f7d92012-09-13 20:23:34 +0000516
517 /* Start transmit */
518 setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
519
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530520 /* Read TX BD status */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530521 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
522 printf("TX buffers exhausted in mid frame\n");
Michal Simek185f7d92012-09-13 20:23:34 +0000523
Álvaro Fernández Rojas48263502018-01-23 17:14:55 +0100524 return wait_for_bit_le32(&regs->txsr, ZYNQ_GEM_TSR_DONE,
525 true, 20000, true);
Michal Simek185f7d92012-09-13 20:23:34 +0000526}
527
528/* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
Michal Simek6889ca72015-11-30 14:14:56 +0100529static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
Michal Simek185f7d92012-09-13 20:23:34 +0000530{
531 int frame_len;
Michal Simek9d9211a2015-12-09 14:26:48 +0100532 u32 addr;
Michal Simek6889ca72015-11-30 14:14:56 +0100533 struct zynq_gem_priv *priv = dev_get_priv(dev);
Michal Simek185f7d92012-09-13 20:23:34 +0000534 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
Michal Simek185f7d92012-09-13 20:23:34 +0000535
536 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
Michal Simek9d9211a2015-12-09 14:26:48 +0100537 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000538
539 if (!(current_bd->status &
540 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
541 printf("GEM: SOF or EOF not set for last buffer received!\n");
Michal Simek9d9211a2015-12-09 14:26:48 +0100542 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000543 }
544
545 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
Michal Simek9d9211a2015-12-09 14:26:48 +0100546 if (!frame_len) {
547 printf("%s: Zero size packet?\n", __func__);
548 return -1;
Michal Simek185f7d92012-09-13 20:23:34 +0000549 }
550
Michal Simek9d9211a2015-12-09 14:26:48 +0100551 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
552 addr &= ~(ARCH_DMA_MINALIGN - 1);
553 *packetp = (uchar *)(uintptr_t)addr;
554
555 return frame_len;
556}
557
558static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
559{
560 struct zynq_gem_priv *priv = dev_get_priv(dev);
561 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
562 struct emac_bd *first_bd;
563
564 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
565 priv->rx_first_buf = priv->rxbd_current;
566 } else {
567 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
568 current_bd->status = 0xF0000000; /* FIXME */
569 }
570
571 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
572 first_bd = &priv->rx_bd[priv->rx_first_buf];
573 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
574 first_bd->status = 0xF0000000;
575 }
576
577 if ((++priv->rxbd_current) >= RX_BUF)
578 priv->rxbd_current = 0;
579
Michal Simekda872d72015-12-09 14:16:32 +0100580 return 0;
Michal Simek185f7d92012-09-13 20:23:34 +0000581}
582
Michal Simek6889ca72015-11-30 14:14:56 +0100583static void zynq_gem_halt(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000584{
Michal Simek6889ca72015-11-30 14:14:56 +0100585 struct zynq_gem_priv *priv = dev_get_priv(dev);
586 struct zynq_gem_regs *regs = priv->iobase;
Michal Simek185f7d92012-09-13 20:23:34 +0000587
Michal Simek80243522012-10-15 14:01:23 +0200588 clrsetbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
589 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
Michal Simek185f7d92012-09-13 20:23:34 +0000590}
591
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600592__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
593{
594 return -ENOSYS;
595}
596
597static int zynq_gem_read_rom_mac(struct udevice *dev)
598{
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600599 struct eth_pdata *pdata = dev_get_platdata(dev);
600
Olliver Schinaglb2330892017-04-03 16:18:53 +0200601 if (!pdata)
602 return -ENOSYS;
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600603
Olliver Schinaglb2330892017-04-03 16:18:53 +0200604 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600605}
606
Michal Simek6889ca72015-11-30 14:14:56 +0100607static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
608 int devad, int reg)
Michal Simek185f7d92012-09-13 20:23:34 +0000609{
Michal Simek6889ca72015-11-30 14:14:56 +0100610 struct zynq_gem_priv *priv = bus->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000611 int ret;
Michal Simek6889ca72015-11-30 14:14:56 +0100612 u16 val;
Michal Simek185f7d92012-09-13 20:23:34 +0000613
Michal Simek6889ca72015-11-30 14:14:56 +0100614 ret = phyread(priv, addr, reg, &val);
615 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
616 return val;
Michal Simek185f7d92012-09-13 20:23:34 +0000617}
618
Michal Simek6889ca72015-11-30 14:14:56 +0100619static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
620 int reg, u16 value)
Michal Simek185f7d92012-09-13 20:23:34 +0000621{
Michal Simek6889ca72015-11-30 14:14:56 +0100622 struct zynq_gem_priv *priv = bus->priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000623
Michal Simek6889ca72015-11-30 14:14:56 +0100624 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
625 return phywrite(priv, addr, reg, value);
Michal Simek185f7d92012-09-13 20:23:34 +0000626}
627
Michal Simek6889ca72015-11-30 14:14:56 +0100628static int zynq_gem_probe(struct udevice *dev)
Michal Simek185f7d92012-09-13 20:23:34 +0000629{
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530630 void *bd_space;
Michal Simek6889ca72015-11-30 14:14:56 +0100631 struct zynq_gem_priv *priv = dev_get_priv(dev);
632 int ret;
Michal Simek185f7d92012-09-13 20:23:34 +0000633
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530634 /* Align rxbuffers to ARCH_DMA_MINALIGN */
635 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
636 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
637
Siva Durga Prasad Paladugu96f4f142014-12-06 12:57:53 +0530638 /* Align bd_space to MMU_SECTION_SHIFT */
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530639 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
Michal Simek9ce1edc2015-04-15 13:31:28 +0200640 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
641 BD_SPACE, DCACHE_OFF);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530642
643 /* Initialize the bd spaces for tx and rx bd's */
644 priv->tx_bd = (struct emac_bd *)bd_space;
Prabhakar Kushwaha5b47d402015-10-25 13:18:54 +0530645 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
Srikanth Thokalaa5144232013-11-08 22:55:48 +0530646
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530647 ret = clk_get_by_name(dev, "tx_clk", &priv->clk);
648 if (ret < 0) {
649 dev_err(dev, "failed to get clock\n");
650 return -EINVAL;
651 }
Siva Durga Prasad Paladugua765bdd2016-11-15 16:15:42 +0530652
Michal Simek6889ca72015-11-30 14:14:56 +0100653 priv->bus = mdio_alloc();
654 priv->bus->read = zynq_gem_miiphy_read;
655 priv->bus->write = zynq_gem_miiphy_write;
656 priv->bus->priv = priv;
Michal Simek185f7d92012-09-13 20:23:34 +0000657
Michal Simek6516e3f2016-12-08 10:25:44 +0100658 ret = mdio_register_seq(priv->bus, dev->seq);
Michal Simekc8e29272015-11-30 13:58:36 +0100659 if (ret)
660 return ret;
661
Siva Durga Prasad Paladugue76d2dc2016-03-30 12:29:49 +0530662 return zynq_phy_init(dev);
Michal Simek185f7d92012-09-13 20:23:34 +0000663}
Michal Simek6889ca72015-11-30 14:14:56 +0100664
665static int zynq_gem_remove(struct udevice *dev)
666{
667 struct zynq_gem_priv *priv = dev_get_priv(dev);
668
669 free(priv->phydev);
670 mdio_unregister(priv->bus);
671 mdio_free(priv->bus);
672
673 return 0;
674}
675
676static const struct eth_ops zynq_gem_ops = {
677 .start = zynq_gem_init,
678 .send = zynq_gem_send,
679 .recv = zynq_gem_recv,
Michal Simek9d9211a2015-12-09 14:26:48 +0100680 .free_pkt = zynq_gem_free_pkt,
Michal Simek6889ca72015-11-30 14:14:56 +0100681 .stop = zynq_gem_halt,
682 .write_hwaddr = zynq_gem_setup_mac,
Joe Hershbergera509a1d2016-01-26 11:57:03 -0600683 .read_rom_hwaddr = zynq_gem_read_rom_mac,
Michal Simek6889ca72015-11-30 14:14:56 +0100684};
685
686static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
687{
688 struct eth_pdata *pdata = dev_get_platdata(dev);
689 struct zynq_gem_priv *priv = dev_get_priv(dev);
Simon Glasse160f7d2017-01-17 16:52:55 -0700690 int node = dev_of_offset(dev);
Michal Simek3cdb1452015-11-30 14:17:50 +0100691 const char *phy_mode;
Michal Simek6889ca72015-11-30 14:14:56 +0100692
Simon Glassa821c4a2017-05-17 17:18:05 -0600693 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
Michal Simek6889ca72015-11-30 14:14:56 +0100694 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
695 /* Hardcode for now */
Michal Simekbcdfef72015-12-09 09:29:12 +0100696 priv->phyaddr = -1;
Michal Simek6889ca72015-11-30 14:14:56 +0100697
Simon Glasse160f7d2017-01-17 16:52:55 -0700698 priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node,
699 "phy-handle");
Dan Murphy20671a92016-05-02 15:45:57 -0500700 if (priv->phy_of_handle > 0)
701 priv->phyaddr = fdtdec_get_int(gd->fdt_blob,
702 priv->phy_of_handle, "reg", -1);
Michal Simek6889ca72015-11-30 14:14:56 +0100703
Simon Glasse160f7d2017-01-17 16:52:55 -0700704 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
Michal Simek3cdb1452015-11-30 14:17:50 +0100705 if (phy_mode)
706 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
707 if (pdata->phy_interface == -1) {
708 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
709 return -EINVAL;
710 }
711 priv->interface = pdata->phy_interface;
712
Siva Durga Prasad Paladugu69065e82018-04-12 12:22:17 +0200713 priv->max_speed = fdtdec_get_uint(gd->fdt_blob, priv->phy_of_handle,
714 "max-speed", SPEED_1000);
Siva Durga Prasad Paladugudd12a272017-11-23 12:56:55 +0530715 priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node,
716 "is-internal-pcspma");
717
Michal Simek15a2acd2016-11-16 08:41:01 +0100718 printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase,
Michal Simek3cdb1452015-11-30 14:17:50 +0100719 priv->phyaddr, phy_string_for_interface(priv->interface));
Michal Simek6889ca72015-11-30 14:14:56 +0100720
721 return 0;
722}
723
724static const struct udevice_id zynq_gem_ids[] = {
725 { .compatible = "cdns,zynqmp-gem" },
726 { .compatible = "cdns,zynq-gem" },
727 { .compatible = "cdns,gem" },
728 { }
729};
730
731U_BOOT_DRIVER(zynq_gem) = {
732 .name = "zynq_gem",
733 .id = UCLASS_ETH,
734 .of_match = zynq_gem_ids,
735 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
736 .probe = zynq_gem_probe,
737 .remove = zynq_gem_remove,
738 .ops = &zynq_gem_ops,
739 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
740 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
741};